Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
| 5 | * 2012 secunet Security Networks AG |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; version 2 of |
| 10 | * the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
Paul Menzel | a46a712 | 2013-02-23 18:37:27 +0100 | [diff] [blame] | 19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 20 | */ |
| 21 | |
| 22 | #include <console/console.h> |
| 23 | #include <device/device.h> |
| 24 | #include <device/pci.h> |
| 25 | #include <device/pciexp.h> |
| 26 | #include <device/pci_ids.h> |
| 27 | |
| 28 | static void pci_init(struct device *dev) |
| 29 | { |
| 30 | u16 reg16; |
| 31 | u32 reg32; |
| 32 | |
| 33 | printk(BIOS_DEBUG, "Initializing ICH9 PCIe root port.\n"); |
| 34 | |
| 35 | /* Enable Bus Master */ |
| 36 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 37 | reg32 |= PCI_COMMAND_MASTER; |
| 38 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 39 | |
| 40 | /* Set Cache Line Size to 0x10 */ |
| 41 | // This has no effect but the OS might expect it |
| 42 | pci_write_config8(dev, 0x0c, 0x10); |
| 43 | |
| 44 | reg16 = pci_read_config16(dev, 0x3e); |
| 45 | reg16 &= ~(1 << 0); /* disable parity error response */ |
| 46 | reg16 |= (1 << 2); /* ISA enable */ |
| 47 | pci_write_config16(dev, 0x3e, reg16); |
| 48 | |
| 49 | /* Enable IO xAPIC on this PCIe port */ |
| 50 | reg32 = pci_read_config32(dev, 0xd8); |
| 51 | reg32 |= (1 << 7); |
| 52 | pci_write_config32(dev, 0xd8, reg32); |
| 53 | |
| 54 | /* Enable Backbone Clock Gating */ |
| 55 | reg32 = pci_read_config32(dev, 0xe1); |
| 56 | reg32 |= (1 << 3) | (1 << 2) | (1 << 1) | (1 << 0); |
| 57 | pci_write_config32(dev, 0xe1, reg32); |
| 58 | |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 59 | /* Set VC0 transaction class */ |
Kyösti Mälkki | 9b143e1 | 2013-07-26 08:35:09 +0300 | [diff] [blame^] | 60 | reg32 = pci_read_config32(dev, 0x114); |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 61 | reg32 &= 0xffffff00; |
| 62 | reg32 |= 1; |
Kyösti Mälkki | 9b143e1 | 2013-07-26 08:35:09 +0300 | [diff] [blame^] | 63 | pci_write_config32(dev, 0x114, reg32); |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 64 | |
| 65 | /* Mask completion timeouts */ |
Kyösti Mälkki | 9b143e1 | 2013-07-26 08:35:09 +0300 | [diff] [blame^] | 66 | reg32 = pci_read_config32(dev, 0x148); |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 67 | reg32 |= (1 << 14); |
Kyösti Mälkki | 9b143e1 | 2013-07-26 08:35:09 +0300 | [diff] [blame^] | 68 | pci_write_config32(dev, 0x148, reg32); |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 69 | |
| 70 | /* Lock R/WO Correctable Error Mask. */ |
Kyösti Mälkki | 9b143e1 | 2013-07-26 08:35:09 +0300 | [diff] [blame^] | 71 | pci_write_config32(dev, 0x154, pci_read_config32(dev, 0x154)); |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 72 | |
| 73 | /* Clear errors in status registers */ |
| 74 | reg16 = pci_read_config16(dev, 0x06); |
| 75 | pci_write_config16(dev, 0x06, reg16); |
| 76 | reg16 = pci_read_config16(dev, 0x1e); |
| 77 | pci_write_config16(dev, 0x1e, reg16); |
| 78 | |
| 79 | /* Get configured ASPM state */ |
| 80 | const enum aspm_type apmc = pci_read_config32(dev, 0x50) & 3; |
| 81 | |
| 82 | /* If both L0s and L1 enabled then set root port 0xE8[1]=1 */ |
| 83 | if (apmc == PCIE_ASPM_BOTH) { |
| 84 | reg32 = pci_read_config32(dev, 0xe8); |
| 85 | reg32 |= (1 << 1); |
| 86 | pci_write_config32(dev, 0xe8, reg32); |
| 87 | } |
| 88 | } |
| 89 | |
| 90 | static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device) |
| 91 | { |
| 92 | /* NOTE: 0x94 is not the default position! */ |
| 93 | if (!vendor || !device) { |
| 94 | pci_write_config32(dev, 0x94, |
| 95 | pci_read_config32(dev, 0)); |
| 96 | } else { |
| 97 | pci_write_config32(dev, 0x94, |
| 98 | ((device & 0xffff) << 16) | (vendor & 0xffff)); |
| 99 | } |
| 100 | } |
| 101 | |
| 102 | static struct pci_operations pci_ops = { |
| 103 | .set_subsystem = pcie_set_subsystem, |
| 104 | }; |
| 105 | |
| 106 | static struct device_operations device_ops = { |
| 107 | .read_resources = pci_bus_read_resources, |
| 108 | .set_resources = pci_dev_set_resources, |
| 109 | .enable_resources = pci_bus_enable_resources, |
| 110 | .init = pci_init, |
| 111 | .scan_bus = pciexp_scan_bridge, |
| 112 | .ops_pci = &pci_ops, |
| 113 | }; |
| 114 | |
| 115 | /* 82801Ix (ICH9DH/ICH9DO/ICH9R/ICH9/ICH9M-E/ICH9M) */ |
| 116 | static const unsigned short pci_device_ids[] = { |
| 117 | 0x2940, /* Port 1 */ |
| 118 | 0x2942, /* Port 2 */ |
| 119 | 0x2944, /* Port 3 */ |
| 120 | 0x2946, /* Port 4 */ |
| 121 | 0x2948, /* Port 5 */ |
| 122 | 0x294a, /* Port 6 */ |
| 123 | 0 |
| 124 | }; |
| 125 | static const struct pci_driver ich9_pcie __pci_driver = { |
| 126 | .ops = &device_ops, |
| 127 | .vendor = PCI_VENDOR_ID_INTEL, |
| 128 | .devices = pci_device_ids, |
| 129 | }; |
| 130 | |