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review.coreboot.org / coreboot / 9aebc19182971deb5dbade7b5e0c5e1f62ac718b / . / src / mainboard / amd / mayan / early_gpio.c
blob: dbda552d34104d46d833c11ac7cba45154e8b08b [file] [log] [blame]
Ritul Guruf123ffe2022-11-25 11:31:26 +0530[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-only */
2
Elyes Haouas9aebc192023-01-30 20:02:03 +0100[diff] [blame^]3#include <gpio.h>
Ritul Guruf123ffe2022-11-25 11:31:26 +0530[diff] [blame]4#include "gpio.h"
5
Ritul Guruf123ffe2022-11-25 11:31:26 +0530[diff] [blame]6/* GPIO pins used by coreboot should be initialized in bootblock */
7
8static const struct soc_amd_gpio gpio_set_stage_reset[] = {
Fred Reitberger8a979d92022-12-01 07:43:11 -0500[diff] [blame]9 /* TPM CS */
10 PAD_NF(GPIO_29, SPI_TPM_CS_L, PULL_NONE),
11 /* ESPI_CS_L */
12 PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE),
13 /* ESPI_SOC_CLK */
14 PAD_NF(GPIO_77, SPI1_CLK, PULL_NONE),
15 /* ESPI_DATA0 */
16 PAD_NF(GPIO_81, SPI1_DAT0, PULL_NONE),
17 /* ESPI_DATA1 */
18 PAD_NF(GPIO_80, SPI1_DAT1, PULL_NONE),
19 /* ESPI_DATA2 */
20 PAD_NF(GPIO_68, SPI1_DAT2, PULL_NONE),
21 /* ESPI_DATA3 */
22 PAD_NF(GPIO_69, SPI1_DAT3, PULL_NONE),
23 /* ESPI_ALERT_L */
24 PAD_NF(GPIO_22, ESPI_ALERT_D1, PULL_NONE),
25 /* TPM IRQ */
26 PAD_SCI(GPIO_90, PULL_UP, EDGE_LOW),
27 /* SPI_ROM_REQ */
28 PAD_NF(GPIO_67, SPI_ROM_REQ, PULL_NONE),
29 /* SPI_ROM_GNT */
30 PAD_NF(GPIO_76, SPI_ROM_GNT, PULL_NONE),
31 /* KBRST_L */
32 PAD_NF(GPIO_21, KBRST_L, PULL_NONE),
33
34 /* Deassert PCIe Reset lines */
35 /* PCIE_RST0_L */
36 PAD_NFO(GPIO_26, PCIE_RST0_L, HIGH),
37 /* PCIE_RST1_L */
38 PAD_NFO(GPIO_27, PCIE_RST1_L, HIGH),
39 /* M2_SSD0_RST_L */
40 PAD_GPO(GPIO_78, HIGH),
41 /* M2_SSD1_RST_L */
42 PAD_GPO(GPIO_79, HIGH),
43
44 /* Enable UART 2 */
45 /* UART2_RXD */
46 PAD_NF(GPIO_136, UART2_RXD, PULL_NONE),
47 /* UART2_TXD */
48 PAD_NF(GPIO_138, UART2_TXD, PULL_NONE),
49 /* Enable UART 0 */
50 /* UART0_RXD */
51 PAD_NF(GPIO_141, UART0_RXD, PULL_NONE),
52 /* UART0_TXD */
53 PAD_NF(GPIO_143, UART0_TXD, PULL_NONE),
54 /* FANOUT0 */
55 PAD_NF(GPIO_85, FANOUT0, PULL_NONE),
56
57 /* I2C0 SCL */
58 PAD_NF(GPIO_145, I2C0_SCL, PULL_NONE),
59 /* I2C0 SDA */
60 PAD_NF(GPIO_146, I2C0_SDA, PULL_NONE),
61 /* I2C1 SCL */
62 PAD_NF(GPIO_147, I2C1_SCL, PULL_NONE),
63 /* I2C1 SDA */
64 PAD_NF(GPIO_148, I2C1_SDA, PULL_NONE),
65 /* I2C2_SCL */
66 PAD_NF(GPIO_113, I2C2_SCL, PULL_NONE),
67 /* I2C2_SDA */
68 PAD_NF(GPIO_114, I2C2_SDA, PULL_NONE),
69 /* I2C3_SCL */
70 PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE),
71 /* I2C3_SDA */
72 PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE),
Ritul Guruf123ffe2022-11-25 11:31:26 +0530[diff] [blame]73};
74
75void mainboard_program_early_gpios(void)
76{
77 gpio_configure_pads(gpio_set_stage_reset, ARRAY_SIZE(gpio_set_stage_reset));
78}