Angel Pons | 5c59680 | 2020-04-03 01:21:01 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Marc Jones | 91135fe | 2016-09-20 20:36:08 -0600 | [diff] [blame] | 2 | |
Marc Jones | 91135fe | 2016-09-20 20:36:08 -0600 | [diff] [blame] | 3 | #include <device/device.h> |
Richard Spiegel | 0ad74ac | 2017-12-08 16:53:29 -0700 | [diff] [blame] | 4 | #include <amdblocks/agesawrapper.h> |
Richard Spiegel | 2bbc3dc | 2017-12-06 16:14:58 -0700 | [diff] [blame] | 5 | #include <amdblocks/amd_pci_util.h> |
Elyes Haouas | 9aebc19 | 2023-01-30 20:02:03 +0100 | [diff] [blame^] | 6 | #include <gpio.h> |
Justin TerAvest | 3fe3f04 | 2018-02-14 19:10:15 -0700 | [diff] [blame] | 7 | #include <soc/southbridge.h> |
| 8 | |
| 9 | #include "gpio.h" |
Marc Jones | 91135fe | 2016-09-20 20:36:08 -0600 | [diff] [blame] | 10 | |
Felix Held | cf92ecf | 2022-10-26 00:59:13 +0200 | [diff] [blame] | 11 | /* The IRQ mapping in fch_irq_map ends up getting written to the indirect address space that is |
| 12 | accessed via I/O ports 0xc00/0xc01. */ |
Felix Held | 9a1da4b | 2022-10-25 22:45:58 +0200 | [diff] [blame] | 13 | static const struct fch_irq_routing fch_irq_map[] = { |
| 14 | { PIRQ_A, 3, 16 }, |
| 15 | { PIRQ_B, 4, 17 }, |
| 16 | { PIRQ_C, 5, 18 }, |
| 17 | { PIRQ_D, 7, 19 }, |
| 18 | { PIRQ_E, 11, 20 }, |
| 19 | { PIRQ_F, 10, 21 }, |
| 20 | { PIRQ_G, PIRQ_NC, 22 }, |
| 21 | { PIRQ_H, PIRQ_NC, 23 }, |
| 22 | { PIRQ_SCI, PIRQ_NC, 9 }, |
| 23 | { PIRQ_SMBUS, PIRQ_NC, PIRQ_NC }, |
| 24 | { PIRQ_HDA, 3, 16 }, |
| 25 | { PIRQ_SD, PIRQ_NC, 16 }, |
| 26 | { PIRQ_SDIO, PIRQ_NC, PIRQ_NC }, |
| 27 | { PIRQ_EHCI, 5, 18 }, |
| 28 | { PIRQ_XHCI, 4, 18 }, |
| 29 | { PIRQ_SATA, PIRQ_NC, 19 }, |
| 30 | { PIRQ_GPIO, 7, 7 }, |
| 31 | { PIRQ_I2C0, 3, 3 }, |
| 32 | { PIRQ_I2C1, 15, 15 }, |
| 33 | { PIRQ_I2C2, 6, 6 }, |
| 34 | { PIRQ_I2C3, 14, 14 }, |
| 35 | { PIRQ_UART0, 10, 10 }, |
| 36 | { PIRQ_UART1, 11, 11 }, |
| 37 | |
| 38 | /* The MISC registers are not interrupt numbers */ |
| 39 | { PIRQ_MISC, 0xfa, 0x00 }, |
| 40 | { PIRQ_MISC0, 0xf1, 0x00 }, |
| 41 | { PIRQ_MISC1, 0x00, 0x00 }, |
| 42 | { PIRQ_MISC2, 0x00, 0x00 }, |
Marc Jones | 91135fe | 2016-09-20 20:36:08 -0600 | [diff] [blame] | 43 | }; |
| 44 | |
Felix Held | cf92ecf | 2022-10-26 00:59:13 +0200 | [diff] [blame] | 45 | const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length) |
Felix Held | 9a1da4b | 2022-10-25 22:45:58 +0200 | [diff] [blame] | 46 | { |
| 47 | *length = ARRAY_SIZE(fch_irq_map); |
| 48 | return fch_irq_map; |
| 49 | } |
| 50 | |
Justin TerAvest | 3fe3f04 | 2018-02-14 19:10:15 -0700 | [diff] [blame] | 51 | static void mainboard_init(void *chip_info) |
| 52 | { |
| 53 | size_t num_gpios; |
Richard Spiegel | 6fcb9b0 | 2018-04-18 08:06:33 -0700 | [diff] [blame] | 54 | const struct soc_amd_gpio *gpios; |
Justin TerAvest | 3fe3f04 | 2018-02-14 19:10:15 -0700 | [diff] [blame] | 55 | gpios = gpio_table(&num_gpios); |
Felix Held | 7011fa1 | 2021-09-22 16:36:12 +0200 | [diff] [blame] | 56 | gpio_configure_pads(gpios, num_gpios); |
Justin TerAvest | 3fe3f04 | 2018-02-14 19:10:15 -0700 | [diff] [blame] | 57 | } |
Marc Jones | 91135fe | 2016-09-20 20:36:08 -0600 | [diff] [blame] | 58 | |
Marc Jones | 91135fe | 2016-09-20 20:36:08 -0600 | [diff] [blame] | 59 | struct chip_operations mainboard_ops = { |
Justin TerAvest | 3fe3f04 | 2018-02-14 19:10:15 -0700 | [diff] [blame] | 60 | .init = mainboard_init, |
Marc Jones | 91135fe | 2016-09-20 20:36:08 -0600 | [diff] [blame] | 61 | }; |