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Felix Helda8d7c042022-01-11 16:22:35 +01001/* SPDX-License-Identifier: GPL-2.0-only */
2
Fred Reitberger248916a2022-04-22 17:37:47 -04003#include <console/console.h>
4#include <device/i2c_simple.h>
Elyes Haouas9aebc192023-01-30 20:02:03 +01005#include <gpio.h>
Felix Helda8d7c042022-01-11 16:22:35 +01006#include <soc/platform_descriptors.h>
7#include <types.h>
8
Fred Reitberger0cbde302022-03-31 08:15:57 -04009static const fsp_dxio_descriptor chausie_dxio_descriptors[] = {
Felix Held2b4d1482022-02-13 23:26:44 +010010 { /* GBE*/
Felix Helda8d7c042022-01-11 16:22:35 +010011 .engine_type = PCIE_ENGINE,
12 .port_present = true,
13 .start_logical_lane = 0,
Felix Held2b4d1482022-02-13 23:26:44 +010014 .end_logical_lane = 0,
Felix Helda8d7c042022-01-11 16:22:35 +010015 .device_number = 2,
16 .function_number = 1,
Felix Held2b4d1482022-02-13 23:26:44 +010017 .link_speed_capability = GEN3,
Felix Helda8d7c042022-01-11 16:22:35 +010018 .turn_off_unused_lanes = true,
Felix Held2b4d1482022-02-13 23:26:44 +010019 .link_aspm = 2,
20 .link_hotplug = 3,
21 .clk_req = CLK_REQ3,
Felix Helda8d7c042022-01-11 16:22:35 +010022 },
Felix Held2b4d1482022-02-13 23:26:44 +010023 { /* WIFI */
Felix Helda8d7c042022-01-11 16:22:35 +010024 .engine_type = PCIE_ENGINE,
25 .port_present = true,
Felix Held2b4d1482022-02-13 23:26:44 +010026 .start_logical_lane = 1,
27 .end_logical_lane = 1,
Felix Helda8d7c042022-01-11 16:22:35 +010028 .device_number = 2,
29 .function_number = 2,
Felix Held2b4d1482022-02-13 23:26:44 +010030 .link_speed_capability = GEN3,
Felix Helda8d7c042022-01-11 16:22:35 +010031 .turn_off_unused_lanes = true,
Felix Held2b4d1482022-02-13 23:26:44 +010032 .link_aspm = 2,
33 .link_hotplug = 3,
Felix Helda8d7c042022-01-11 16:22:35 +010034 .clk_req = CLK_REQ1,
Felix Helda8d7c042022-01-11 16:22:35 +010035 },
Felix Held2b4d1482022-02-13 23:26:44 +010036 { /* NVMe SSD */
Felix Helda8d7c042022-01-11 16:22:35 +010037 .engine_type = PCIE_ENGINE,
38 .port_present = true,
Felix Helda8d7c042022-01-11 16:22:35 +010039 .start_logical_lane = 2,
40 .end_logical_lane = 3,
Felix Held2b4d1482022-02-13 23:26:44 +010041 .device_number = 2,
42 .function_number = 3,
43 .link_speed_capability = GEN3,
44 .turn_off_unused_lanes = true,
45 .link_aspm = 2,
46 .link_hotplug = 3,
47 .gpio_group_id = GPIO_27,
48 .clk_req = CLK_REQ0,
49 },
Felix Helda8d7c042022-01-11 16:22:35 +010050};
51
Fred Reitberger248916a2022-04-22 17:37:47 -040052static fsp_ddi_descriptor chausie_ddi_descriptors[] = {
Felix Helda84c00c2022-03-28 18:05:36 +020053 { /* DDI0 - eDP */
54 .connector_type = DDI_EDP,
Felix Helda8d7c042022-01-11 16:22:35 +010055 .aux_index = DDI_AUX1,
56 .hdp_index = DDI_HDP1
57 },
Fred Reitberger248916a2022-04-22 17:37:47 -040058 { /* DDI1 - HDMI/DP */
Felix Helda8d7c042022-01-11 16:22:35 +010059 .connector_type = DDI_HDMI,
60 .aux_index = DDI_AUX2,
61 .hdp_index = DDI_HDP2
62 },
Felix Helda84c00c2022-03-28 18:05:36 +020063 { /* DDI2 - DP (type C) */
Jason Nien29f15802022-08-17 17:04:44 -050064 .connector_type = DDI_DP_W_TYPEC,
Felix Helda8d7c042022-01-11 16:22:35 +010065 .aux_index = DDI_AUX3,
66 .hdp_index = DDI_HDP3,
67 },
68 { /* DDI3 - DP (type C) */
Jason Nien29f15802022-08-17 17:04:44 -050069 .connector_type = DDI_DP_W_TYPEC,
Felix Helda8d7c042022-01-11 16:22:35 +010070 .aux_index = DDI_AUX4,
71 .hdp_index = DDI_HDP4,
Felix Helda84c00c2022-03-28 18:05:36 +020072 },
73 { /* DDI4 - unused */
74 .connector_type = DDI_UNUSED_TYPE,
75 .aux_index = DDI_AUX5,
76 .hdp_index = DDI_HDP5,
Felix Helda8d7c042022-01-11 16:22:35 +010077 }
78};
79
Fred Reitberger248916a2022-04-22 17:37:47 -040080static uint8_t get_ddi1_type(void)
81{
82 const uint8_t eeprom_i2c_bus = 2;
83 const uint8_t eeprom_i2c_address = 0x55;
84 const uint16_t eeprom_connector_type_offset = 2;
85 uint8_t eeprom_connector_type_data[2];
86 uint16_t connector_type;
87
88 if (i2c_2ba_read_bytes(eeprom_i2c_bus, eeprom_i2c_address,
89 eeprom_connector_type_offset, eeprom_connector_type_data,
90 sizeof(eeprom_connector_type_data))) {
91 printk(BIOS_NOTICE,
92 "Display connector type couldn't be determined. Disabling DDI1.\n");
93 return DDI_UNUSED_TYPE;
94 }
95
96 connector_type = eeprom_connector_type_data[1] | eeprom_connector_type_data[0] << 8;
97
98 switch (connector_type) {
99 case 0xc:
100 printk(BIOS_DEBUG, "Configuring DDI1 as HDMI.\n");
101 return DDI_HDMI;
102 break;
103 case 0x13:
104 printk(BIOS_DEBUG, "Configuring DDI1 as DP.\n");
105 return DDI_DP;
106 break;
107 case 0x14:
108 printk(BIOS_DEBUG, "Configuring DDI1 as eDP.\n");
109 return DDI_EDP;
110 break;
111 default:
112 printk(BIOS_WARNING, "Unexpected display connector type %x. Disabling DDI1.\n",
113 connector_type);
114 return DDI_UNUSED_TYPE;
115 }
116}
117
Felix Helda8d7c042022-01-11 16:22:35 +0100118void mainboard_get_dxio_ddi_descriptors(
119 const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num,
120 const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num)
121{
Fred Reitberger248916a2022-04-22 17:37:47 -0400122 chausie_ddi_descriptors[1].connector_type = get_ddi1_type();
123
Fred Reitberger0cbde302022-03-31 08:15:57 -0400124 *dxio_descs = chausie_dxio_descriptors;
125 *dxio_num = ARRAY_SIZE(chausie_dxio_descriptors);
126 *ddi_descs = chausie_ddi_descriptors;
127 *ddi_num = ARRAY_SIZE(chausie_ddi_descriptors);
Felix Helda8d7c042022-01-11 16:22:35 +0100128}