Martin Roth | 3c963d9 | 2022-10-06 16:29:07 -0600 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
Elyes Haouas | 9aebc19 | 2023-01-30 20:02:03 +0100 | [diff] [blame^] | 3 | #include <gpio.h> |
Martin Roth | 3c963d9 | 2022-10-06 16:29:07 -0600 | [diff] [blame] | 4 | #include "gpio.h" |
| 5 | |
Martin Roth | 3c963d9 | 2022-10-06 16:29:07 -0600 | [diff] [blame] | 6 | /* |
| 7 | * As a rule of thumb, GPIO pins used by coreboot should be initialized at |
| 8 | * bootblock while GPIO pins used only by the OS should be initialized at |
| 9 | * ramstage. |
| 10 | */ |
| 11 | static const struct soc_amd_gpio gpio_set_stage_ram[] = { |
Fred Reitberger | 98d0574 | 2022-11-09 15:07:12 -0500 | [diff] [blame] | 12 | /* PWR_BTN_L */ |
| 13 | PAD_NF(GPIO_0, PWR_BTN_L, PULL_NONE), |
| 14 | /* SYS_RESET_L */ |
| 15 | PAD_NF(GPIO_1, SYS_RESET_L, PULL_NONE), |
| 16 | /* WAKE_L */ |
| 17 | PAD_NF_SCI(GPIO_2, WAKE_L, PULL_NONE, EDGE_LOW), |
| 18 | /* PCIE_SD_WAKE_L */ |
| 19 | PAD_SCI(GPIO_3, PULL_NONE, EDGE_LOW), |
| 20 | /* UART_WAKE_L_M2_APU */ |
| 21 | PAD_SCI(GPIO_4, PULL_UP, EDGE_LOW), |
| 22 | /* MPM_EVENT_L, input or OD output */ |
| 23 | PAD_GPI(GPIO_5, PULL_UP), |
| 24 | /* TPNL_INT_L */ |
| 25 | PAD_SCI(GPIO_6, PULL_UP, EDGE_LOW), |
| 26 | /* EC SCI */ |
| 27 | PAD_SCI(GPIO_7, PULL_UP, EDGE_LOW), |
| 28 | /* TPAD_INT_L */ |
| 29 | PAD_SCI(GPIO_8, PULL_UP, EDGE_LOW), |
| 30 | /* SD_CARD_PRSNT_L */ |
| 31 | PAD_GPI(GPIO_9, PULL_UP), /* Unclear if this needs to be SCI */ |
| 32 | /* VDD_MEM_VID0 */ |
| 33 | PAD_GPO(GPIO_10, HIGH), |
| 34 | /* HP_MIC_DET_L */ |
| 35 | PAD_GPI(GPIO_11, PULL_UP), |
| 36 | /* ALIGN_FLAG_MU_L */ |
| 37 | PAD_GPO(GPIO_12, HIGH), |
| 38 | /* GPIO_13 - GPIO_15: Not available */ |
| 39 | /* USB_OC0_L */ |
| 40 | PAD_NF(GPIO_16, USB_OC0_L, PULL_NONE), |
| 41 | /* WAKE_ON_WAN_L */ |
| 42 | PAD_SCI(GPIO_17, PULL_UP, EDGE_LOW), |
| 43 | /* PCIE_WLAN_WAKE_L */ |
| 44 | PAD_SCI(GPIO_18, PULL_UP, EDGE_LOW), |
| 45 | /* I2C3_SCL */ |
| 46 | PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), |
| 47 | /* I2C3_SDA */ |
| 48 | PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), |
| 49 | /* KBRST_L */ |
| 50 | PAD_NF(GPIO_21, KBRST_L, PULL_NONE), |
| 51 | /* ESPI_ALERT_L */ |
| 52 | PAD_NF(GPIO_22, ESPI_ALERT_D1, PULL_NONE), |
| 53 | /* AC_PRES */ |
| 54 | PAD_NF(GPIO_23, AC_PRES, PULL_NONE), |
| 55 | /* PCIE_LOM_WAKE_L */ |
| 56 | PAD_SCI(GPIO_24, PULL_UP, EDGE_LOW), |
| 57 | /* GPIO_25: Not available */ |
| 58 | /* PCIE_RST0_L */ |
| 59 | PAD_NFO(GPIO_26, PCIE_RST0_L, HIGH), |
| 60 | /* PCIE_RST1_L */ |
| 61 | PAD_NFO(GPIO_27, PCIE_RST1_L, HIGH), |
| 62 | /* GPIO_28: Not available */ |
| 63 | /* TPM CS */ |
| 64 | PAD_NF(GPIO_29, SPI_TPM_CS_L, PULL_NONE), |
| 65 | /* ESPI_CS_L */ |
| 66 | PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), |
| 67 | /* INT_CLKREQ_L */ |
Fred Reitberger | f68bd12 | 2022-12-02 16:03:05 -0500 | [diff] [blame] | 68 | PAD_INT(GPIO_31, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), |
Fred Reitberger | 98d0574 | 2022-11-09 15:07:12 -0500 | [diff] [blame] | 69 | /* LPC_RST_L */ |
| 70 | PAD_NF(GPIO_32, LPC_RST_L, PULL_NONE), |
| 71 | /* GPIO_33 - GPIO_37: Not available */ |
| 72 | /* CLK_REQ5_L */ |
| 73 | PAD_NF(GPIO_38, CLK_REQ5_L, PULL_NONE), |
| 74 | /* CLK_REQ6_L */ |
| 75 | PAD_NF(GPIO_39, CLK_REQ6_L, PULL_NONE), |
| 76 | /* USB2_HDR_P0/1_SMI */ |
| 77 | PAD_SCI(GPIO_40, PULL_UP, EDGE_LOW), |
| 78 | /* GPIO_41: Not available */ |
| 79 | /* VDD_MEM_VID1 */ |
| 80 | PAD_GPO(GPIO_42, HIGH), |
| 81 | /* GPIO_43 - GPIO_66: Not available */ |
| 82 | /* SPI_ROM_REQ */ |
| 83 | PAD_NF(GPIO_67, SPI_ROM_REQ, PULL_NONE), |
| 84 | /* ESPI_DATA2 */ |
| 85 | PAD_NF(GPIO_68, SPI1_DAT2, PULL_NONE), |
| 86 | /* ESPI_DATA3 */ |
| 87 | PAD_NF(GPIO_69, SPI1_DAT3, PULL_NONE), |
| 88 | /* SPI2_CLK */ |
| 89 | PAD_NF(GPIO_70, SPI2_CLK, PULL_NONE), |
| 90 | /* GPIO_71 - GPIO_73: Not available */ |
| 91 | /* APU_NFC_DWL_REQ_1V8 */ |
| 92 | PAD_GPO(GPIO_74, LOW), |
| 93 | /* SPI2_CS1_L */ |
| 94 | PAD_NF(GPIO_75, SPI2_CS1_L, PULL_NONE), |
| 95 | /* SPI_ROM_GNT */ |
| 96 | PAD_NF(GPIO_76, SPI_ROM_GNT, PULL_NONE), |
| 97 | /* ESPI_SOC_CLK */ |
| 98 | PAD_NF(GPIO_77, SPI1_CLK, PULL_NONE), |
| 99 | /* M2_SSD0_RST_L */ |
| 100 | PAD_GPO(GPIO_78, HIGH), |
| 101 | /* M2_SSD1_RST_L */ |
| 102 | PAD_GPO(GPIO_79, HIGH), |
| 103 | /* ESPI_DATA1 */ |
| 104 | PAD_NF(GPIO_80, SPI1_DAT1, PULL_NONE), |
| 105 | /* ESPI_DATA0 */ |
| 106 | PAD_NF(GPIO_81, SPI1_DAT0, PULL_NONE), |
| 107 | /* GPIO_82 - GPIO_83: Not available */ |
| 108 | /* FANIN0 */ |
| 109 | PAD_NF(GPIO_84, FANIN0, PULL_NONE), |
| 110 | /* FANOUT0 */ |
| 111 | PAD_NF(GPIO_85, FANOUT0, PULL_NONE), |
| 112 | /* GPIO_86 - GPIO_88: Not available */ |
| 113 | /* I2S CODEC INT */ |
| 114 | PAD_SCI(GPIO_89, PULL_UP, EDGE_LOW), |
| 115 | /* ALERT_L_M2_SSD0 */ |
| 116 | PAD_SCI(GPIO_90, PULL_UP, EDGE_LOW), |
| 117 | /* NFC IRQ */ |
| 118 | PAD_SCI(GPIO_91, PULL_UP, EDGE_LOW), |
| 119 | /* CLK_REQ0_L */ |
| 120 | PAD_NF(GPIO_92, CLK_REQ0_L, PULL_NONE), |
| 121 | /* GPIO_93 - GPIO_103: Not available */ |
| 122 | /* SPI2_DAT0 */ |
| 123 | PAD_NF(GPIO_104, SPI2_DAT0, PULL_NONE), |
| 124 | /* SPI2_DAT1 */ |
| 125 | PAD_NF(GPIO_105, SPI2_DAT1, PULL_NONE), |
| 126 | /* SPI2_DAT2 */ |
| 127 | PAD_NF(GPIO_106, SPI2_DAT2, PULL_NONE), |
| 128 | /* SPI2_DAT3 */ |
| 129 | PAD_NF(GPIO_107, SPI2_DAT3, PULL_NONE), |
| 130 | /* GPIO_108 - GPIO_112: Not available */ |
| 131 | /* I2C2_SCL */ |
| 132 | PAD_NF(GPIO_113, I2C2_SCL, PULL_NONE), |
| 133 | /* I2C2_SDA */ |
| 134 | PAD_NF(GPIO_114, I2C2_SDA, PULL_NONE), |
| 135 | /* CLK_REQ1_L */ |
| 136 | PAD_NF(GPIO_115, CLK_REQ1_L, PULL_NONE), |
| 137 | /* CLK_REQ2_L */ |
| 138 | PAD_NF(GPIO_116, CLK_REQ2_L, PULL_NONE), |
| 139 | /* GPIO_117 - GPIO_129: Not available */ |
| 140 | /* TPM IRQ */ |
Fred Reitberger | f68bd12 | 2022-12-02 16:03:05 -0500 | [diff] [blame] | 141 | PAD_INT(GPIO_130, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), |
Fred Reitberger | 98d0574 | 2022-11-09 15:07:12 -0500 | [diff] [blame] | 142 | /* CLK_REQ3_L */ |
| 143 | PAD_NF(GPIO_131, CLK_REQ3_L, PULL_NONE), |
| 144 | /* CLK_REQ4_L */ |
| 145 | PAD_NF(GPIO_132, CLK_REQ4_L, PULL_NONE), |
| 146 | /* GPIO_133 - GPIO_134: Not available */ |
| 147 | /* UART2_CTS_L */ |
| 148 | PAD_NF(GPIO_135, UART2_CTS_L, PULL_NONE), |
| 149 | /* UART2_RXD */ |
| 150 | PAD_NF(GPIO_136, UART2_RXD, PULL_NONE), |
| 151 | /* UART2_RTS_L */ |
| 152 | PAD_NF(GPIO_137, UART2_RTS_L, PULL_NONE), |
| 153 | /* UART2_TXD */ |
| 154 | PAD_NF(GPIO_138, UART2_TXD, PULL_NONE), |
| 155 | /* M2_SSD2_RST_L */ |
| 156 | PAD_GPO(GPIO_139, HIGH), |
| 157 | /* UART0_CTS_L */ |
| 158 | PAD_NF(GPIO_140, UART0_CTS_L, PULL_NONE), |
| 159 | /* UART0_RXD */ |
| 160 | PAD_NF(GPIO_141, UART0_RXD, PULL_NONE), |
| 161 | /* UART0_RTS_L */ |
| 162 | PAD_NF(GPIO_142, UART0_RTS_L, PULL_NONE), |
| 163 | /* UART0_TXD */ |
| 164 | PAD_NF(GPIO_143, UART0_TXD, PULL_NONE), |
| 165 | /* M2_SSD3_RST_L */ |
| 166 | PAD_GPO(GPIO_144, HIGH), |
| 167 | /* I2C0 SCL */ |
| 168 | PAD_NF(GPIO_145, I2C0_SCL, PULL_NONE), |
| 169 | /* I2C0 SDA */ |
| 170 | PAD_NF(GPIO_146, I2C0_SDA, PULL_NONE), |
| 171 | /* I2C1 SCL */ |
| 172 | PAD_NF(GPIO_147, I2C1_SCL, PULL_NONE), |
| 173 | /* I2C1 SDA */ |
| 174 | PAD_NF(GPIO_148, I2C1_SDA, PULL_NONE), |
| 175 | /* GPIO_149 - GPIO_152: Not available */ |
| 176 | /* UART4_CTS_L */ |
| 177 | PAD_NF(GPIO_153, UART4_CTS_L, PULL_NONE), |
| 178 | /* UART4_RTS_L */ |
| 179 | PAD_NF(GPIO_154, UART4_RTS_L, PULL_NONE), |
| 180 | /* UART4_RXD */ |
| 181 | PAD_NF(GPIO_155, UART4_RXD, PULL_NONE), |
| 182 | /* UART4_TXD */ |
| 183 | PAD_NF(GPIO_156, UART4_TXD, PULL_NONE), |
| 184 | /* M2_SSD4_RST_L */ |
| 185 | PAD_GPO(GPIO_157, HIGH), |
Martin Roth | 3c963d9 | 2022-10-06 16:29:07 -0600 | [diff] [blame] | 186 | }; |
| 187 | |
| 188 | void mainboard_program_gpios(void) |
| 189 | { |
| 190 | gpio_configure_pads(gpio_set_stage_ram, ARRAY_SIZE(gpio_set_stage_ram)); |
| 191 | } |