zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * mt.h |
| 6 | * |
| 7 | * Common Technology |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: (Mem) |
| 12 | * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ |
| 13 | * |
| 14 | **/ |
| 15 | /***************************************************************************** |
| 16 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 17 | * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. |
| 18 | * All rights reserved. |
| 19 | * |
| 20 | * Redistribution and use in source and binary forms, with or without |
| 21 | * modification, are permitted provided that the following conditions are met: |
| 22 | * * Redistributions of source code must retain the above copyright |
| 23 | * notice, this list of conditions and the following disclaimer. |
| 24 | * * Redistributions in binary form must reproduce the above copyright |
| 25 | * notice, this list of conditions and the following disclaimer in the |
| 26 | * documentation and/or other materials provided with the distribution. |
| 27 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 28 | * its contributors may be used to endorse or promote products derived |
| 29 | * from this software without specific prior written permission. |
| 30 | * |
| 31 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 32 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 33 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 34 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 35 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 36 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 37 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 38 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 39 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 40 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 41 | * *************************************************************************** |
| 42 | * |
| 43 | */ |
| 44 | |
| 45 | #ifndef _MT_H_ |
| 46 | #define _MT_H_ |
| 47 | |
| 48 | /*---------------------------------------------------------------------------- |
| 49 | * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) |
| 50 | * |
| 51 | *---------------------------------------------------------------------------- |
| 52 | */ |
| 53 | |
| 54 | /*----------------------------------------------------------------------------- |
| 55 | * DEFINITIONS AND MACROS |
| 56 | * |
| 57 | *----------------------------------------------------------------------------- |
| 58 | */ |
| 59 | |
| 60 | #define FIRST_PASS 1 |
| 61 | #define SECOND_PASS 2 |
| 62 | #define BIGPAGE_X8_RJ16 0x80 |
| 63 | #define BIGPAGE_X8 0x800000ul |
| 64 | #define DQS_FAIL 1 |
| 65 | #define DQS_PASS 0 |
| 66 | #define DQS_WRITE_DIR 1 |
| 67 | #define DQS_READ_DIR 0 |
| 68 | #define MIN_DQS_WNDW 3 |
| 69 | #define ST_UNSTEADY 0 |
| 70 | #define ST_STEADY 1 |
| 71 | #define ST_GROSS_SWEEP 2 |
| 72 | #define ST_FINE_SWEEP 3 |
| 73 | #define ST_FINISH 4 |
| 74 | #define NIBBLE_0 0 |
| 75 | #define NIBBLE_1 1 |
| 76 | |
| 77 | #define MAX_BYTELANES_PER_CHANNEL (8 + 1) ///< Max Bytelanes per channel |
| 78 | |
| 79 | #define MAX_FILTER_DLY_DDR2 0x20 |
| 80 | #define MAX_FILTER_DLY_DDR3 0x28 |
| 81 | |
| 82 | #define NEW_RECEIVER_START_VALUE 0x4 |
| 83 | #define NEW_RECEIVER_STEP_1 4 |
| 84 | #define NEW_RECEIVER_STEP_2 7 |
| 85 | |
| 86 | #define NEW_RECEIVER_FINAL_OFFSETVALUE 5 |
| 87 | |
| 88 | #define MAX_POS_RX_EN_SEED_GROSS_RANGE 0x20 ///< Max Range RxEn Seed Gross |
| 89 | #define MAX_POS_RX_EN_SEED_GROSS_DIR 0x2 ///< Max RxEn Seed Gross Direction |
| 90 | |
| 91 | #define DBG_PRINT_STAGE 18 // "Stage" |
| 92 | #define DBG_PRINT_0_TO_64 23 // "0...64" |
| 93 | #define DBG_SPACES_4 21 // 4 spaces |
| 94 | #define DBG_POS_NEW_LINE 11 // New Line for POS training |
| 95 | #define DBG_WR_DLY 24 // "Write Delay: " |
| 96 | #define DBG_B_L_R_W_M 22 // " Bytelane Left Right Width Middle" |
| 97 | #define DBG_RX_EN_NEW_LINE 25 // New Line for Rx En |
| 98 | #define DBG_RX_EN_STAGE1 6 // "Receiver Enable Training Stage 1:" |
| 99 | #define DBG_RX_EN_STAGE2 7 // "Receiver Enable Training Stage 2:" |
| 100 | #define DBG_RX_EN_STAGE3 8 // "Receiver Enable Training Stage 3:" |
| 101 | #define DBG_DLY_PER_BL 9 // "Dly per BL -" |
| 102 | #define DBG_A_B_DLY 10 // "ALL BLs have Dly:" |
| 103 | #define DBG_RCVR_PRT_VALUE 0x0010Ful // PORT for RX EN training to print a value |
| 104 | #define DBG_RX_POS_PRT_VALUE 0x0011Ful // PORT for POS training to print a value |
| 105 | |
| 106 | #define DONE_FILTER 0 ///< optimized receiver enable training glitch search complete |
| 107 | #define START_FILTER 1 ///< optimized receiver enable training start glitch filter search |
| 108 | #define FILTER_FIRST_STAGE_COUNT 4 ///< optimized receiver enable training glitch filter first stage count |
| 109 | #define FILTER_SECOND_STAGE_COUNT 7 ///< optimized receiver enable training glitch second stage count |
| 110 | #define FILTER_OFFSET_VALUE 0x1C ///< optimized receiver enable training glitch filter offset value int preamble |
| 111 | #define FILTER_WINDOW_SIZE 0x28 ///< optimized receiver enable training glitch filter search window size |
| 112 | #define FILTER_MAX_REC_EN_DLY_VALUE 0x1FF ///< optimized receiver enable glitch filter max receiver value |
| 113 | #define FILTER_NEW_RECEIVER_START_VALUE 0x0 ///< optimized receiver enable glitch filter Start value |
| 114 | #define MAX_NUMBER_NIBBLES 18 ///< Maximum number of nibbles |
| 115 | #define MAX_NUMBER_LANES 18 ///< Maximum number of lanes (nibbles or bytes) |
| 116 | #define MAX_2D_VREF_ENTRIES 0x20 ///< Maximum number of vref entries |
| 117 | #define MAX_RD_DQS_ENTRIES 0x40 ///< Maximum number of RDDQS Entries |
| 118 | #define VREF_ADDITIONAL_STEP_SIZE 0x0 ///< Vref Additional Step size |
| 119 | #define RDDQS_ADDITIONAL_STEP_SIZE 0x0 ///< RdDqs Additional Step size |
| 120 | |
| 121 | /*---------------------------------------------------------------------------- |
| 122 | * TYPEDEFS, STRUCTURES, ENUMS |
| 123 | * |
| 124 | *---------------------------------------------------------------------------- |
| 125 | */ |
| 126 | /// List for Technology specific functions that are supported |
| 127 | typedef enum { |
| 128 | WlTrainingPrepareLrdimm, ///< Technology specific tasks to prepare LRDIMMs for Training |
| 129 | LrdimmControlRegInit, ///< Technology specific tasks to send control words to initialize an LRDIMM |
| 130 | LrdimmFreqChgCtrlWrd, ///< Technology specific tasks to send control words to reprogram LRDIMM's register |
| 131 | LrdimmSendAllMRCmds, ///< Technology specific tasks to send all MR commands |
| 132 | LrdimmRankMultiplication, ///< Determine Rank Multiplication to be used |
| 133 | LrdimmBuf2DramTrain, ///< Perform buffer to DRAM training for LRDIMMs |
| 134 | LrdimmSyncTrainedDlys, ///< Copy trained delay of the first rank of a QR LRDIMM to the third rank |
| 135 | LrdimmPresence, ///< Perform LRDIMM specific tasks at the time of Dimm Presence Detection |
| 136 | |
| 137 | NumberOfTechHooks ///< Size of list |
| 138 | } TECHNOLOGY_SPECIFIC_FUNC_INDEX; |
| 139 | |
| 140 | |
| 141 | /// Structure for Technology block. |
| 142 | typedef struct _MEM_TECH_BLOCK { |
| 143 | MEM_NB_BLOCK *NBPtr; ///< point to northbridge block. |
| 144 | MEM_PARAMETER_STRUCT *RefPtr; ///< point to parameter list. |
| 145 | |
| 146 | /* Temporary storage */ |
| 147 | UINT32 HwcrLo; ///< value of HWCR. |
| 148 | UINT32 CR4reg; ///< CR4 register value. |
| 149 | UINT8 DramEcc; ///< value of Dram ECC bit. |
| 150 | UINT8 *TestBufPtr; ///< point to buffer to store read-back data. |
| 151 | UINT8 *PatternBufPtr; ///< point to pattern buffer. |
| 152 | UINT16 PatternLength; ///< the length of pattern buffer in cache lines. |
| 153 | UINT8 Direction; ///< direction during training. |
| 154 | UINT8 ChipSel; ///< chip select number. |
| 155 | INT8 RestartChipSel; ///< is used to save the chipsel at which first RdDqsDly retrain is issued |
| 156 | UINT16 MaxDlyForMaxRdLat; ///< Largest possible value for Receiver enable delay. |
| 157 | UINT16 PrevSpeed; ///< Previous MemClk frequency |
| 158 | TRAINING_TYPE TrainingType; ///< Type of training currently being done |
| 159 | UINT8 TargetDIMM; ///< Target DIMM to being trained |
| 160 | INT16 WLCriticalDelay; ///< Minimum WL Dly of all byte lanes and all DIMMs |
| 161 | UINT8 Bytelane; ///< Bytelane being trained |
| 162 | UINT8 TrnNibble; ///< Nibble being trained |
| 163 | |
| 164 | |
| 165 | UINT8 Pass; ///< current pass of training. |
| 166 | UINT16 DqsRdWrPosSaved; ///< for position training byte lane saved flag |
| 167 | UINT16 DqsRcvEnSaved; ///< for TrainRcvrEn UINT8 lane saved flag |
| 168 | UINT16 DqsRcvEnSavedS1; ///< for TrainRcvrEn UINT8 lane saved flag |
| 169 | UINT16 DqsRcvEnFirstPassVal; ///< for TrainRcvrEn UINT8 lane saved flag |
| 170 | BOOLEAN GetFirstPassVal; ///< If the first passing value has been found. |
| 171 | BOOLEAN RevertPassVal; ///< Flag to restart training during training process when glitch is found. |
| 172 | UINT8 MaxFilterDly; ///< Maximum filter delay value for RcvrTraining. |
| 173 | UINT16 RcvrEnDlyOpt[MAX_BYTELANES_PER_CHANNEL]; ///< Receiver Enable delay for optimized filter |
| 174 | UINT16 MaxRcvrEnDlyBlOpt[MAX_BYTELANES_PER_CHANNEL]; ///< Max Receiver Enable delay for optimized filter |
| 175 | UINT16 RcvrEnDlyLimitOpt[MAX_BYTELANES_PER_CHANNEL]; ///< Receiver Enable delay Limit for optimized filter |
| 176 | UINT16 FilterStatusOpt[MAX_BYTELANES_PER_CHANNEL]; ///< Filter status to indicate if a ByteLane is "DONE", "SKIP" or "CONTINUE" |
| 177 | UINT16 FilterCountOpt; ///< Filter count to indicate the total number of ByteLanes completed |
| 178 | BOOLEAN DqsRcvEnSavedOpt[MAX_BYTELANES_PER_CHANNEL]; ///< for optimized TrainRcvrEn lane saved flag |
| 179 | UINT16 DqsRcvEnFirstPassValOpt[MAX_BYTELANES_PER_CHANNEL]; ///< for TrainRcvrEn UINT8 lane saved flag for optimized |
| 180 | BOOLEAN GetFirstPassValOpt[MAX_BYTELANES_PER_CHANNEL]; ///< If the first passing value has been found for optimized. |
| 181 | BOOLEAN RevertPassValOpt[MAX_BYTELANES_PER_CHANNEL]; ///< Flag to restart training during training process when glitch is found for optimized. |
| 182 | UINT8 MaxFilterDlyBlOpt[MAX_BYTELANES_PER_CHANNEL]; ///< Maximum filter delay value for RcvrTraining for optimized. |
| 183 | BOOLEAN IncBy1ForNextCountOpt[MAX_BYTELANES_PER_CHANNEL]; ///< Used to determine when to increment by 1 in second stage of opt. rec. en. training |
| 184 | UINT8 FilterSidePassCountOpt[MAX_BYTELANES_PER_CHANNEL]; ///< Indicates that previous side passed |
| 185 | UINT16 DiffSeedGrossSeedPreGross[MAX_BYTELANES_PER_CHANNEL]; ///< Gross difference between GrossSeed and SeedPreGross for HwRxEn Training. |
| 186 | UINT16 PrevPassRcvEnDly[MAX_BYTELANES_PER_CHANNEL]; ///< Receiver Enable Delay value from the previous pass |
| 187 | BOOLEAN SmallDqsPosWindow; ///< Status flag to record small DQS position window event |
| 188 | UINT8 WlNibbleDly[MAX_BYTELANES_PER_CHANNEL]; ///< Nibble based trainig results for Nibble 0 of Write Levelization |
| 189 | UINT16 WlNibble0Seed[MAX_BYTELANES_PER_CHANNEL]; ///< Nibble based trainig seed value for Nibble 0 Write Levelization |
| 190 | UINT16 RxEnNibbleDly[MAX_BYTELANES_PER_CHANNEL]; ///< Nibble based trainig results for Nibble 0 of Rx En training |
| 191 | BOOLEAN ByteLaneError[MAX_BYTELANES_PER_CHANNEL]; ///< Indicates that an error has occured on a bytelane |
| 192 | UINT16 RxOrig[MAX_BYTELANES_PER_CHANNEL]; ///< Original RxEn Delays for seedless training |
| 193 | |
| 194 | /* PUBLIC functions */ |
| 195 | VOID (*SendAllMRCmds) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 ChipSel); ///< Send MRS command. |
| 196 | VOID (*FreqChgCtrlWrd) (struct _MEM_TECH_BLOCK *TechPtr); ///< Frequency change control word. |
| 197 | BOOLEAN (*SetDramMode) (struct _MEM_TECH_BLOCK *TechPtr); ///< Set dram mode (DDR2 or DDR3). |
| 198 | BOOLEAN (*DimmPresence) (struct _MEM_TECH_BLOCK *TechPtr); ///< determines if DIMMs present. |
| 199 | BOOLEAN (*SpdCalcWidth) (struct _MEM_TECH_BLOCK *TechPtr); ///< check the symmetry of DIMM pairs. |
| 200 | BOOLEAN (*SpdGetTargetSpeed) (struct _MEM_TECH_BLOCK *TechPtr); ///< get supported frequency. |
| 201 | BOOLEAN (*AutoCycTiming) (struct _MEM_TECH_BLOCK *TechPtr); ///< configure timing based on spd data. |
| 202 | BOOLEAN (*SpdSetBanks) (struct _MEM_TECH_BLOCK *TechPtr); ///< set bank address. |
| 203 | BOOLEAN (*SetDqsEccTmgs) (struct _MEM_TECH_BLOCK *TechPtr); ///< DQS training. |
| 204 | VOID (*GetCSIntLvAddr) (UINT8 BankEnc, UINT8 *LowBit, UINT8 *HiBit); ///< Get Chip select interleave address. |
| 205 | VOID (*AdjustTwrwr) (struct _MEM_TECH_BLOCK *TechPtr); ///< Adjust Twrwr for certain dimm technology. |
| 206 | VOID (*AdjustTwrrd) (struct _MEM_TECH_BLOCK *TechPtr); ///< Adjust Twrrd for certain dimm technology. |
| 207 | INT8 (*GetLD) (struct _MEM_TECH_BLOCK *TechPtr); ///< Get LD value for certain dimm technology. |
| 208 | VOID (*DramInit) (struct _MEM_TECH_BLOCK *TechPtr); ///< dram initialization. |
| 209 | |
| 210 | /* PRIVATE functions */ |
| 211 | VOID (*InitDQSPos4RcvrEn) (struct _MEM_TECH_BLOCK *TechPtr); ///< Initialize training register before training. |
| 212 | VOID (*SetRcvrEnDly) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Receiver, UINT16 RcvEnDly); ///< Set receiver enable delay register value. |
| 213 | VOID (*LoadRcvrEnDly) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Receiver); ///< Load receiver enable delay register value. |
| 214 | BOOLEAN (*SaveRcvrEnDly) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Receiver, UINT16 RcvEnDly, UINT16 cmpResultRank0, UINT16 cmpResultRank1); ///< Save receiver enable delay register value. |
| 215 | BOOLEAN (*SaveRcvrEnDlyFilter) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Receiver, UINT16 RcvEnDly, UINT16 cmpResultRank0, UINT16 cmpResultRank1); ///< saves passing DqsRcvEnDly values to the stack. |
| 216 | VOID (*ResetDCTWrPtr) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Receiver); ///< resets the DCT input buffer write pointer. |
| 217 | UINT16 (*Compare1ClPattern) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Buffer[], UINT8 Pattern[]); ///< Compare training pattern of 1 cache line. |
| 218 | VOID (*SkipChipSelPass1) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 *ChipSel); ///< skips odd chip select if training at 800MT or above. |
| 219 | VOID (*SkipChipSelPass2) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 *ChipSel); ///< skips odd chip select if training at 800MT or above. |
| 220 | UINT16 (*CompareTestPatternFilter) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Buffer[], UINT8 Pattern[], UINT16 ByteCount); ///< compare training pattern with filter. |
| 221 | UINT8 (*MaxByteLanes) ( VOID ); ///< return maximum number of bytelanes. |
| 222 | VOID (*SetDQSDelayCSR) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 ByteLane, UINT8 Dly); ///< Set CSR. |
| 223 | VOID (*DQSWindowSave) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 ByteLane, UINT8 DlyMin, UINT8 DlyMax); ///< programs the trained DQS delay for the specified byte lane and stores its DQS window for reference. |
| 224 | BOOLEAN (*FindMaxDlyForMaxRdLat) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 *ChipSel); ///< Find maximum receiver enable delay value. |
| 225 | UINT8 (*DlyTableWidth) ( VOID ); ///< return the width of the delay tables (eg. RcvEnDlys, WrDqsDlys,...) in number of bytes. |
| 226 | UINT16 (*Compare1ClPatternOpt) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Buffer[], UINT8 Pattern[], UINT8 Side, UINT8 Receiver, BOOLEAN Side1En); ///< Compare training pattern of 1 cache line. |
| 227 | VOID (*LoadRcvrEnDlyOpt) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Receiver); ///< Load receiver enable delay register value. |
| 228 | VOID (*SetRcvrEnDlyOpt) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Receiver, UINT16 RcvEnDly); ///< Set receiver enable delay register value. |
| 229 | BOOLEAN (*CheckRcvrEnDlyLimitOpt) (struct _MEM_TECH_BLOCK *TechPtr); ///< Find limit for all bytelanes |
| 230 | UINT16 (*GetMaxValueOpt) (struct _MEM_TECH_BLOCK *TechPtr); ///< Returns the max value of all bytelanes |
| 231 | VOID (*InitializeVariablesOpt) (struct _MEM_TECH_BLOCK *TechPtr); ///< Initialized variables for optimized training |
| 232 | BOOLEAN (*SetSweepErrorOpt)(struct _MEM_TECH_BLOCK *TechPtr, UINT8 Receiver, UINT8 DCT, BOOLEAN ErrorCheck); ///< records any errors generated from optimized sweep |
| 233 | VOID (*LoadInitialRcvrEnDlyOpt) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 Receiver); ///< Load the starting value for receiver DQS training. |
| 234 | BOOLEAN (*GetDimmSpdBuffer) (struct _MEM_TECH_BLOCK *TechPtr, UINT8 **SpdBuffer, UINT8 Dimm); ///< Gets pointer to spd buffer for a dimm on the current channel, if present |
| 235 | UINT8 (*GetMinMaxGrossDly) (struct _MEM_TECH_BLOCK *TechPtr, TRN_DLY_TYPE TrnDlyType, BOOLEAN IfMax); ///< Gets the minimum or maximum gross dly value |
| 236 | |
| 237 | /* Technology Specific Hooks */ |
| 238 | BOOLEAN (*(TechnologySpecificHook[NumberOfTechHooks])) (struct _MEM_TECH_BLOCK *TechPtr, VOID *OptParam); ///< Technology specific functions |
| 239 | } MEM_TECH_BLOCK; |
| 240 | |
| 241 | /*---------------------------------------------------------------------------- |
| 242 | * FUNCTIONS PROTOTYPE |
| 243 | * |
| 244 | *---------------------------------------------------------------------------- |
| 245 | */ |
| 246 | |
| 247 | VOID |
| 248 | MemTDimmByteTrainInit ( |
| 249 | IN OUT MEM_TECH_BLOCK *TechPtr |
| 250 | ); |
| 251 | |
| 252 | BOOLEAN |
| 253 | MemTTrainMaxLatency ( |
| 254 | IN OUT MEM_TECH_BLOCK *TechPtr |
| 255 | ); |
| 256 | |
| 257 | BOOLEAN |
| 258 | MemTSetDQSEccTmgs ( |
| 259 | IN OUT MEM_TECH_BLOCK *TechPtr |
| 260 | ); |
| 261 | |
| 262 | BOOLEAN |
| 263 | MemTSetDQSEccTmgsRDdr3 ( |
| 264 | IN OUT MEM_TECH_BLOCK *TechPtr |
| 265 | ); |
| 266 | |
| 267 | BOOLEAN |
| 268 | MemTTrainRcvrEnSwPass1 ( |
| 269 | IN OUT MEM_TECH_BLOCK *TechPtr |
| 270 | ); |
| 271 | |
| 272 | BOOLEAN |
| 273 | MemTTrainDQSEdgeDetectSw ( |
| 274 | IN OUT MEM_TECH_BLOCK *TechPtr |
| 275 | ); |
| 276 | |
| 277 | BOOLEAN |
| 278 | MemTTrainDQSEdgeDetect ( |
| 279 | IN OUT MEM_TECH_BLOCK *TechPtr |
| 280 | ); |
| 281 | |
| 282 | BOOLEAN |
| 283 | MemTDramInitSw3 ( |
| 284 | IN OUT MEM_TECH_BLOCK *TechPtr |
| 285 | ); |
| 286 | VOID |
| 287 | MemTDramInitHw ( |
| 288 | IN OUT MEM_TECH_BLOCK *TechPtr |
| 289 | ); |
| 290 | BOOLEAN |
| 291 | MemTFeatDef ( |
| 292 | IN OUT MEM_TECH_BLOCK *TechPtr |
| 293 | ); |
| 294 | BOOLEAN |
| 295 | MemTSaveRcvrEnDlyByteFilter ( |
| 296 | IN OUT MEM_TECH_BLOCK *TechPtr, |
| 297 | IN UINT8 Receiver, |
| 298 | IN UINT16 RcvEnDly, |
| 299 | IN UINT16 CmpResultRank0, |
| 300 | IN UINT16 CmpResultRank1 |
| 301 | ); |
| 302 | |
| 303 | BOOLEAN |
| 304 | MemTSaveRcvrEnDlyByteFilterOpt ( |
| 305 | IN OUT MEM_TECH_BLOCK *TechPtr, |
| 306 | IN UINT8 Receiver, |
| 307 | IN UINT16 RcvEnDly, |
| 308 | IN UINT16 CmpResultRank0, |
| 309 | IN UINT16 CmpResultRank1 |
| 310 | ); |
| 311 | |
| 312 | BOOLEAN |
| 313 | MemTNewRevTrainingSupport ( |
| 314 | IN OUT MEM_TECH_BLOCK *TechPtr |
| 315 | ); |
| 316 | |
| 317 | BOOLEAN |
| 318 | MemTTrainOptRcvrEnSwPass1 ( |
| 319 | IN OUT MEM_TECH_BLOCK *TechPtr |
| 320 | ); |
| 321 | |
| 322 | BOOLEAN |
| 323 | MemTWriteLevelizationHw3Pass1 ( |
| 324 | IN OUT MEM_TECH_BLOCK *TechPtr |
| 325 | ); |
| 326 | |
| 327 | BOOLEAN |
| 328 | MemTWriteLevelizationHw3Pass2 ( |
| 329 | IN OUT MEM_TECH_BLOCK *TechPtr |
| 330 | ); |
| 331 | |
| 332 | BOOLEAN |
| 333 | MemTPreparePhyAssistedTraining ( |
| 334 | IN OUT MEM_TECH_BLOCK *TechPtr |
| 335 | ); |
| 336 | |
| 337 | BOOLEAN |
| 338 | MemTExitPhyAssistedTraining ( |
| 339 | IN OUT MEM_TECH_BLOCK *TechPtr |
| 340 | ); |
| 341 | |
| 342 | BOOLEAN |
| 343 | MemTDqsTrainRcvrEnHwPass1 ( |
| 344 | IN OUT MEM_TECH_BLOCK *TechPtr |
| 345 | ); |
| 346 | |
| 347 | BOOLEAN |
| 348 | MemTDqsTrainRcvrEnHwPass2 ( |
| 349 | IN OUT MEM_TECH_BLOCK *TechPtr |
| 350 | ); |
| 351 | |
| 352 | VOID |
| 353 | MemRecTSetWrDatRdDqs ( |
| 354 | IN OUT MEM_TECH_BLOCK *TechPtr, |
| 355 | IN UINT8 WrDatDly |
| 356 | ); |
| 357 | |
| 358 | VOID |
| 359 | MemRecTTrainDQSPosSw ( |
| 360 | IN OUT MEM_TECH_BLOCK *TechPtr |
| 361 | ); |
| 362 | |
| 363 | VOID |
| 364 | MemRecTTrainRcvrEnSw ( |
| 365 | IN OUT MEM_TECH_BLOCK *TechPtr |
| 366 | ); |
| 367 | |
| 368 | VOID |
| 369 | MemRecTTrainRcvrEnHw ( |
| 370 | IN OUT MEM_TECH_BLOCK *TechPtr |
| 371 | ); |
| 372 | |
| 373 | VOID |
| 374 | MemRecTTrainRcvrEnHwSeedless ( |
| 375 | IN OUT MEM_TECH_BLOCK *TechPtr |
| 376 | ); |
| 377 | |
| 378 | VOID |
| 379 | MemRecTBeginTraining ( |
| 380 | IN OUT MEM_TECH_BLOCK *TechPtr |
| 381 | ); |
| 382 | |
| 383 | VOID |
| 384 | MemRecTEndTraining ( |
| 385 | IN OUT MEM_TECH_BLOCK *TechPtr |
| 386 | ); |
| 387 | |
| 388 | BOOLEAN |
| 389 | MemTSetSweepErrorOptByte ( |
| 390 | IN OUT MEM_TECH_BLOCK *TechPtr, |
| 391 | IN UINT8 Receiver, |
| 392 | IN UINT8 Dct, |
| 393 | IN BOOLEAN ErrorCheck |
| 394 | ); |
| 395 | |
| 396 | VOID |
| 397 | MemTInitializeVariablesOptByte ( |
| 398 | IN OUT MEM_TECH_BLOCK *TechPtr |
| 399 | ); |
| 400 | |
| 401 | UINT16 |
| 402 | MemTGetMaxValueOptByte ( |
| 403 | IN OUT MEM_TECH_BLOCK *TechPtr |
| 404 | ); |
| 405 | |
| 406 | BOOLEAN |
| 407 | MemTCheckRcvrEnDlyLimitOptByte ( |
| 408 | IN OUT MEM_TECH_BLOCK *TechPtr |
| 409 | ); |
| 410 | |
| 411 | VOID |
| 412 | MemTMarkTrainFail ( |
| 413 | IN OUT MEM_TECH_BLOCK *TechPtr |
| 414 | ); |
| 415 | |
| 416 | VOID |
| 417 | MemTBeginTraining ( |
| 418 | IN OUT MEM_TECH_BLOCK *TechPtr |
| 419 | ); |
| 420 | |
| 421 | VOID |
| 422 | MemTEndTraining ( |
| 423 | IN OUT MEM_TECH_BLOCK *TechPtr |
| 424 | ); |
| 425 | |
| 426 | VOID |
| 427 | MemTSetDQSDelayAllCSR ( |
| 428 | IN OUT MEM_TECH_BLOCK *TechPtr, |
| 429 | IN UINT8 Dly |
| 430 | ); |
| 431 | |
| 432 | BOOLEAN |
| 433 | MemTExitPhyAssistedTrainingClient3 ( |
| 434 | IN OUT MEM_TECH_BLOCK *TechPtr |
| 435 | ); |
| 436 | |
| 437 | BOOLEAN |
| 438 | MemTFindMaxRcvrEnDlyRdDqsDlyByte ( |
| 439 | IN OUT MEM_TECH_BLOCK *TechPtr, |
| 440 | OUT UINT8 *ChipSel |
| 441 | ); |
| 442 | |
| 443 | BOOLEAN |
| 444 | MemTFindMaxRcvrEnDlyRdDqsDlyByteUnb ( |
| 445 | IN OUT MEM_TECH_BLOCK *TechPtr, |
| 446 | OUT UINT8 *ChipSel |
| 447 | ); |
| 448 | |
| 449 | VOID |
| 450 | MemTSendCtlWord3 ( |
| 451 | IN OUT MEM_TECH_BLOCK *TechPtr, |
| 452 | IN UINT8 CmdNum, |
| 453 | IN UINT8 Value |
| 454 | ); |
| 455 | |
| 456 | VOID |
| 457 | MemTCommonTechInit ( |
| 458 | IN OUT MEM_TECH_BLOCK *TechPtr |
| 459 | ); |
| 460 | |
| 461 | BOOLEAN |
| 462 | MemTLrdimmConstructor3 ( |
| 463 | IN OUT MEM_TECH_BLOCK *TechPtr |
| 464 | ); |
| 465 | |
| 466 | BOOLEAN |
| 467 | MemTRdPosWithRxEnDlySeeds3 ( |
| 468 | IN OUT MEM_TECH_BLOCK *TechPtr |
| 469 | ); |
| 470 | |
| 471 | BOOLEAN |
| 472 | MemTTrackRxEnSeedlessRdWrNoWindBLError ( |
| 473 | IN OUT MEM_TECH_BLOCK *TechPtr, |
| 474 | IN OUT VOID *OptParam |
| 475 | ); |
| 476 | |
| 477 | BOOLEAN |
| 478 | MemTTrackRxEnSeedlessRdWrSmallWindBLError ( |
| 479 | IN OUT MEM_TECH_BLOCK *TechPtr, |
| 480 | IN OUT VOID *OptParam |
| 481 | ); |
| 482 | |
| 483 | |
| 484 | |
| 485 | |
| 486 | #endif /* _MT_H_ */ |