zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * ma.h |
| 6 | * |
| 7 | * ARDK common header file |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: (Mem) |
| 12 | * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ |
| 13 | * |
| 14 | **/ |
| 15 | /***************************************************************************** |
| 16 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 17 | * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. |
| 18 | * All rights reserved. |
| 19 | * |
| 20 | * Redistribution and use in source and binary forms, with or without |
| 21 | * modification, are permitted provided that the following conditions are met: |
| 22 | * * Redistributions of source code must retain the above copyright |
| 23 | * notice, this list of conditions and the following disclaimer. |
| 24 | * * Redistributions in binary form must reproduce the above copyright |
| 25 | * notice, this list of conditions and the following disclaimer in the |
| 26 | * documentation and/or other materials provided with the distribution. |
| 27 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 28 | * its contributors may be used to endorse or promote products derived |
| 29 | * from this software without specific prior written permission. |
| 30 | * |
| 31 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 32 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 33 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 34 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 35 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 36 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 37 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 38 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 39 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 40 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 41 | * *************************************************************************** |
| 42 | * |
| 43 | */ |
| 44 | |
| 45 | #ifndef _MA_H_ |
| 46 | #define _MA_H_ |
| 47 | |
| 48 | /*---------------------------------------------------------------------------- |
| 49 | * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) |
| 50 | * |
| 51 | *---------------------------------------------------------------------------- |
| 52 | */ |
| 53 | |
| 54 | /*----------------------------------------------------------------------------- |
| 55 | * DEFINITIONS AND MACROS |
| 56 | * |
| 57 | *----------------------------------------------------------------------------- |
| 58 | */ |
| 59 | |
| 60 | |
| 61 | #define MAX_CS_PER_CHANNEL 8 ///< Max CS per channel |
| 62 | /*---------------------------------------------------------------------------- |
| 63 | * TYPEDEFS, STRUCTURES, ENUMS |
| 64 | * |
| 65 | *---------------------------------------------------------------------------- |
| 66 | */ |
| 67 | |
| 68 | /** MARDK Structure*/ |
| 69 | typedef struct { |
| 70 | UINT16 Speed; ///< Dram speed in MHz |
| 71 | UINT8 Loads; ///< Number of Data Loads |
| 72 | UINT32 AddrTmg; ///< Address Timing value |
| 73 | UINT32 Odc; ///< Output Driver Compensation Value |
| 74 | } PSCFG_ENTRY; |
| 75 | |
| 76 | /** MARDK Structure*/ |
| 77 | typedef struct { |
| 78 | UINT16 Speed; ///< Dram speed in MHz |
| 79 | UINT8 Loads; ///< Number of Data Loads |
| 80 | UINT32 AddrTmg; ///< Address Timing value |
| 81 | UINT32 Odc; ///< Output Driver Compensation Value |
| 82 | UINT8 Dimms; ///< Number of Dimms |
| 83 | } ADV_PSCFG_ENTRY; |
| 84 | |
| 85 | /** MARDK Structure for RDIMMs*/ |
| 86 | typedef struct { |
| 87 | UINT16 Speed; ///< Dram speed in MHz |
| 88 | UINT16 DIMMRankType; ///< Bitmap of Ranks //Bit0-3:DIMM0(1:SR, 2:DR, 4:QR, 0:No Dimm, 0xF:Any), Bit4-7:DIMM1, Bit8-11:DIMM2, Bit12-16:DIMM3 |
| 89 | UINT32 AddrTmg; ///< Address Timing value |
| 90 | UINT16 RC2RC8; ///< RC2 and RC8 value //High byte: 1st pair value, Low byte: 2nd pair value |
| 91 | UINT8 Dimms; ///< Number of Dimms |
| 92 | } ADV_R_PSCFG_ENTRY; |
| 93 | |
| 94 | /** MARDK Structure*/ |
| 95 | typedef struct { |
| 96 | UINT16 DIMMRankType; ///< Bitmap of Ranks //Bit0-3:DIMM0(1:SR, 2:DR, 4:QR, 0:No Dimm, 0xF:Any), Bit4-7:DIMM1, Bit8-11:DIMM2, Bit12-16:DIMM3 |
| 97 | UINT32 PhyRODTCSLow; ///< Fn2_9C 180 |
| 98 | UINT32 PhyRODTCSHigh; ///< Fn2_9C 181 |
| 99 | UINT32 PhyWODTCSLow; ///< Fn2_9C 182 |
| 100 | UINT32 PhyWODTCSHigh; ///< Fn2_9C 183 |
| 101 | UINT8 Dimms; ///< Number of Dimms |
| 102 | } ADV_PSCFG_ODT_ENTRY; |
| 103 | |
| 104 | /** MARDK Structure for Write Levelization ODT*/ |
| 105 | typedef struct { |
| 106 | UINT16 DIMMRankType; ///< Bitmap of Ranks //Bit0-3:DIMM0(1:SR, 2:DR, 4:QR, 0:No Dimm, 0xF:Any), Bit4-7:DIMM1, Bit8-11:DIMM2, Bit12-16:DIMM3 |
| 107 | UINT8 PhyWrLvOdt[MAX_CS_PER_CHANNEL / 2]; ///< WrLvOdt (Fn2_9C_0x08[11:8]) Value for each Dimm |
| 108 | UINT8 Dimms; ///< Number of Dimms |
| 109 | } ADV_R_PSCFG_WL_ODT_ENTRY; |
| 110 | |
| 111 | /*---------------------------------------------------------------------------- |
| 112 | * FUNCTIONS PROTOTYPE |
| 113 | * |
| 114 | *---------------------------------------------------------------------------- |
| 115 | */ |
| 116 | |
| 117 | AGESA_STATUS |
| 118 | MemAGetPsCfgDef ( |
| 119 | IN OUT MEM_DATA_STRUCT *MemData, |
| 120 | IN UINT8 SocketID, |
| 121 | IN OUT CH_DEF_STRUCT *CurrentChannel |
| 122 | ); |
| 123 | |
| 124 | AGESA_STATUS |
| 125 | MemAGetPsCfgRDr2 ( |
| 126 | IN OUT MEM_DATA_STRUCT *MemData, |
| 127 | IN UINT8 SocketID, |
| 128 | IN OUT CH_DEF_STRUCT *CurrentChannel |
| 129 | ); |
| 130 | |
| 131 | AGESA_STATUS |
| 132 | MemAGetPsCfgRDr3 ( |
| 133 | IN OUT MEM_DATA_STRUCT *MemData, |
| 134 | IN UINT8 SocketID, |
| 135 | IN OUT CH_DEF_STRUCT *CurrentChannel |
| 136 | ); |
| 137 | |
| 138 | AGESA_STATUS |
| 139 | MemAGetPsCfgUDr3 ( |
| 140 | IN OUT MEM_DATA_STRUCT *MemData, |
| 141 | IN UINT8 SocketID, |
| 142 | IN OUT CH_DEF_STRUCT *CurrentChannel |
| 143 | ); |
| 144 | |
| 145 | AGESA_STATUS |
| 146 | MemAGetPsCfgSDA2 ( |
| 147 | IN OUT MEM_DATA_STRUCT *MemData, |
| 148 | IN UINT8 SocketID, |
| 149 | IN OUT CH_DEF_STRUCT *CurrentChannel |
| 150 | ); |
| 151 | |
| 152 | AGESA_STATUS |
| 153 | MemAGetPsCfgSDA3 ( |
| 154 | IN OUT MEM_DATA_STRUCT *MemData, |
| 155 | IN UINT8 SocketID, |
| 156 | IN OUT CH_DEF_STRUCT *CurrentChannel |
| 157 | ); |
| 158 | |
| 159 | AGESA_STATUS |
| 160 | MemAGetPsCfgSNi3 ( |
| 161 | IN OUT MEM_DATA_STRUCT *MemData, |
| 162 | IN UINT8 SocketID, |
| 163 | IN OUT CH_DEF_STRUCT *CurrentChannel |
| 164 | ); |
| 165 | |
| 166 | AGESA_STATUS |
| 167 | MemAGetPsCfgUNi3 ( |
| 168 | IN OUT MEM_DATA_STRUCT *MemData, |
| 169 | IN UINT8 SocketID, |
| 170 | IN OUT CH_DEF_STRUCT *CurrentChannel |
| 171 | ); |
| 172 | |
| 173 | AGESA_STATUS |
| 174 | MemAGetPsCfgSRb3 ( |
| 175 | IN OUT MEM_DATA_STRUCT *MemData, |
| 176 | IN UINT8 SocketID, |
| 177 | IN OUT CH_DEF_STRUCT *CurrentChannel |
| 178 | ); |
| 179 | |
| 180 | AGESA_STATUS |
| 181 | MemAGetPsCfgURb3 ( |
| 182 | IN OUT MEM_DATA_STRUCT *MemData, |
| 183 | IN UINT8 SocketID, |
| 184 | IN OUT CH_DEF_STRUCT *CurrentChannel |
| 185 | ); |
| 186 | |
| 187 | AGESA_STATUS |
| 188 | MemAGetPsCfgSPh3 ( |
| 189 | IN OUT MEM_DATA_STRUCT *MemData, |
| 190 | IN UINT8 SocketID, |
| 191 | IN OUT CH_DEF_STRUCT *CurrentChannel |
| 192 | ); |
| 193 | |
| 194 | AGESA_STATUS |
| 195 | MemAGetPsCfgUPh3 ( |
| 196 | IN OUT MEM_DATA_STRUCT *MemData, |
| 197 | IN UINT8 SocketID, |
| 198 | IN OUT CH_DEF_STRUCT *CurrentChannel |
| 199 | ); |
| 200 | |
| 201 | AGESA_STATUS |
| 202 | MemAGetPsCfgUDA3 ( |
| 203 | IN OUT MEM_DATA_STRUCT *MemData, |
| 204 | IN UINT8 SocketID, |
| 205 | IN OUT CH_DEF_STRUCT *CurrentChannel |
| 206 | ); |
| 207 | |
| 208 | AGESA_STATUS |
| 209 | MemAGetPsCfgRHy3 ( |
| 210 | IN OUT MEM_DATA_STRUCT *MemData, |
| 211 | IN UINT8 SocketID, |
| 212 | IN OUT CH_DEF_STRUCT *CurrentChannel |
| 213 | ); |
| 214 | |
| 215 | AGESA_STATUS |
| 216 | MemAGetPsCfgUHy3 ( |
| 217 | IN OUT MEM_DATA_STRUCT *MemData, |
| 218 | IN UINT8 SocketID, |
| 219 | IN OUT CH_DEF_STRUCT *CurrentChannel |
| 220 | ); |
| 221 | |
| 222 | AGESA_STATUS |
| 223 | MemAGetPsCfgRC32_3 ( |
| 224 | IN OUT MEM_DATA_STRUCT *MemData, |
| 225 | IN UINT8 SocketID, |
| 226 | IN OUT CH_DEF_STRUCT *CurrentChannel |
| 227 | ); |
| 228 | |
| 229 | AGESA_STATUS |
| 230 | MemAGetPsCfgUC32_3 ( |
| 231 | IN OUT MEM_DATA_STRUCT *MemData, |
| 232 | IN UINT8 SocketID, |
| 233 | IN OUT CH_DEF_STRUCT *CurrentChannel |
| 234 | ); |
| 235 | |
| 236 | AGESA_STATUS |
| 237 | MemAGetPsCfgSLN3 ( |
| 238 | IN OUT MEM_DATA_STRUCT *MemData, |
| 239 | IN UINT8 SocketID, |
| 240 | IN OUT CH_DEF_STRUCT *CurrentChannel |
| 241 | ); |
| 242 | |
| 243 | AGESA_STATUS |
| 244 | MemAGetPsCfgULN3 ( |
| 245 | IN OUT MEM_DATA_STRUCT *MemData, |
| 246 | IN UINT8 SocketID, |
| 247 | IN OUT CH_DEF_STRUCT *CurrentChannel |
| 248 | ); |
| 249 | |
| 250 | AGESA_STATUS |
| 251 | MemAGetPsCfgSON3 ( |
| 252 | IN OUT MEM_DATA_STRUCT *MemData, |
| 253 | IN UINT8 SocketID, |
| 254 | IN OUT CH_DEF_STRUCT *CurrentChannel |
| 255 | ); |
| 256 | |
| 257 | AGESA_STATUS |
| 258 | MemAGetPsCfgUON3 ( |
| 259 | IN OUT MEM_DATA_STRUCT *MemData, |
| 260 | IN UINT8 SocketID, |
| 261 | IN OUT CH_DEF_STRUCT *CurrentChannel |
| 262 | ); |
| 263 | |
| 264 | AGESA_STATUS |
| 265 | MemAGetPsCfgROr3 ( |
| 266 | IN OUT MEM_DATA_STRUCT *MemData, |
| 267 | IN UINT8 SocketID, |
| 268 | IN OUT CH_DEF_STRUCT *CurrentChannel |
| 269 | ); |
| 270 | |
| 271 | AGESA_STATUS |
| 272 | MemAGetPsCfgUOr3 ( |
| 273 | IN OUT MEM_DATA_STRUCT *MemData, |
| 274 | IN UINT8 SocketID, |
| 275 | IN OUT CH_DEF_STRUCT *CurrentChannel |
| 276 | ); |
| 277 | |
| 278 | UINT16 |
| 279 | MemAGetPsRankType ( |
| 280 | IN CH_DEF_STRUCT *CurrentChannel |
| 281 | ); |
| 282 | |
| 283 | AGESA_STATUS |
| 284 | MemRecNGetPsCfgDef ( |
| 285 | IN OUT MEM_DATA_STRUCT *MemData, |
| 286 | IN UINT8 SocketID, |
| 287 | IN OUT CH_DEF_STRUCT *CurrentChannel |
| 288 | ); |
| 289 | |
| 290 | UINT16 |
| 291 | MemRecNGetPsRankType ( |
| 292 | IN CH_DEF_STRUCT *CurrentChannel |
| 293 | ); |
| 294 | |
| 295 | AGESA_STATUS |
| 296 | MemRecNGetPsCfgUDIMM3Nb ( |
| 297 | IN OUT MEM_DATA_STRUCT *MemData, |
| 298 | IN UINT8 SocketID, |
| 299 | IN OUT CH_DEF_STRUCT *CurrentChannel |
| 300 | ); |
| 301 | |
| 302 | AGESA_STATUS |
| 303 | MemRecNGetPsCfgSODIMM3Nb ( |
| 304 | IN OUT MEM_DATA_STRUCT *MemData, |
| 305 | IN UINT8 SocketID, |
| 306 | IN OUT CH_DEF_STRUCT *CurrentChannel |
| 307 | ); |
| 308 | |
| 309 | AGESA_STATUS |
| 310 | MemRecNGetPsCfgRDIMM3Nb ( |
| 311 | IN OUT MEM_DATA_STRUCT *MemData, |
| 312 | IN UINT8 SocketID, |
| 313 | IN OUT CH_DEF_STRUCT *CurrentChannel |
| 314 | ); |
| 315 | |
| 316 | #endif /* _MA_H_ */ |