zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * mttecc3.c |
| 6 | * |
| 7 | * Technology ECC byte support for registered DDR3 |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: (Mem/Tech/DDR3) |
| 12 | * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ |
| 13 | * |
| 14 | **/ |
| 15 | /***************************************************************************** |
| 16 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 17 | * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. |
| 18 | * All rights reserved. |
| 19 | * |
| 20 | * Redistribution and use in source and binary forms, with or without |
| 21 | * modification, are permitted provided that the following conditions are met: |
| 22 | * * Redistributions of source code must retain the above copyright |
| 23 | * notice, this list of conditions and the following disclaimer. |
| 24 | * * Redistributions in binary form must reproduce the above copyright |
| 25 | * notice, this list of conditions and the following disclaimer in the |
| 26 | * documentation and/or other materials provided with the distribution. |
| 27 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 28 | * its contributors may be used to endorse or promote products derived |
| 29 | * from this software without specific prior written permission. |
| 30 | * |
| 31 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 32 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 33 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 34 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 35 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 36 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 37 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 38 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 39 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 40 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 41 | * *************************************************************************** |
| 42 | * |
| 43 | */ |
| 44 | |
| 45 | /* |
| 46 | *---------------------------------------------------------------------------- |
| 47 | * MODULES USED |
| 48 | * |
| 49 | *---------------------------------------------------------------------------- |
| 50 | */ |
| 51 | |
| 52 | |
| 53 | #include "AGESA.h" |
| 54 | #include "mm.h" |
| 55 | #include "mn.h" |
| 56 | #include "mt.h" |
| 57 | #include "Filecode.h" |
| 58 | CODE_GROUP (G1_PEICC) |
| 59 | RDATA_GROUP (G1_PEICC) |
| 60 | |
| 61 | #define FILECODE PROC_MEM_TECH_DDR3_MTTECC3_FILECODE |
| 62 | /*---------------------------------------------------------------------------- |
| 63 | * DEFINITIONS AND MACROS |
| 64 | * |
| 65 | *---------------------------------------------------------------------------- |
| 66 | */ |
| 67 | |
| 68 | /*---------------------------------------------------------------------------- |
| 69 | * TYPEDEFS AND STRUCTURES |
| 70 | * |
| 71 | *---------------------------------------------------------------------------- |
| 72 | */ |
| 73 | |
| 74 | /*---------------------------------------------------------------------------- |
| 75 | * PROTOTYPES OF LOCAL FUNCTIONS |
| 76 | * |
| 77 | *---------------------------------------------------------------------------- |
| 78 | */ |
| 79 | |
| 80 | /*---------------------------------------------------------------------------- |
| 81 | * EXPORTED FUNCTIONS |
| 82 | * |
| 83 | *---------------------------------------------------------------------------- |
| 84 | */ |
| 85 | |
| 86 | /* -----------------------------------------------------------------------------*/ |
| 87 | /** |
| 88 | * |
| 89 | * This function sets the DQS ECC timings for registered DDR3 |
| 90 | * |
| 91 | * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK |
| 92 | * |
| 93 | * @return TRUE - No fatal error occurs. |
| 94 | * @return FALSE - Fatal error occurs. |
| 95 | */ |
| 96 | |
| 97 | BOOLEAN |
| 98 | MemTSetDQSEccTmgsRDdr3 ( |
| 99 | IN OUT MEM_TECH_BLOCK *TechPtr |
| 100 | ) |
| 101 | { |
| 102 | UINT8 Dct; |
| 103 | UINT8 Dimm; |
| 104 | UINT8 i; |
| 105 | UINT8 *WrDqsDly; |
| 106 | UINT16 *RcvEnDly; |
| 107 | UINT8 *RdDqsDly; |
| 108 | UINT8 *WrDatDly; |
| 109 | UINT8 EccByte; |
| 110 | INT16 TempValue; |
| 111 | |
| 112 | MEM_NB_BLOCK *NBPtr; |
| 113 | CH_DEF_STRUCT *ChannelPtr; |
| 114 | |
| 115 | EccByte = TechPtr->MaxByteLanes (); |
| 116 | NBPtr = TechPtr->NBPtr; |
| 117 | |
| 118 | if (NBPtr->MCTPtr->NodeMemSize) { |
| 119 | for (Dct = 0; Dct < NBPtr->DctCount; Dct++) { |
| 120 | NBPtr->SwitchDCT (NBPtr, Dct); |
| 121 | if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { |
| 122 | ChannelPtr = NBPtr->ChannelPtr; |
| 123 | for (Dimm = 0; Dimm < MAX_DIMMS_PER_CHANNEL; Dimm++) { |
| 124 | if (NBPtr->DCTPtr->Timings.CsEnabled & ((UINT16)3 << (Dimm * 2))) { |
| 125 | i = Dimm * TechPtr->DlyTableWidth (); |
| 126 | WrDqsDly = &ChannelPtr->WrDqsDlys[i]; |
| 127 | RcvEnDly = &ChannelPtr->RcvEnDlys[i]; |
| 128 | RdDqsDly = &ChannelPtr->RdDqsDlys[i]; |
| 129 | WrDatDly = &ChannelPtr->WrDatDlys[i]; |
| 130 | // Receiver DQS Enable: |
| 131 | // Receiver DQS enable for ECC bytelane = Receiver DQS enable for bytelane 3 - |
| 132 | // [write DQS for bytelane 3 - write DQS for ECC] |
| 133 | |
| 134 | TempValue = (INT16) RcvEnDly[3] - (INT16) (WrDqsDly[3] - WrDqsDly[EccByte]); |
| 135 | if (TempValue < 0) { |
| 136 | TempValue = 0; |
| 137 | } |
| 138 | RcvEnDly[EccByte] = (UINT16) TempValue; |
| 139 | |
| 140 | // Read DQS: |
| 141 | // Read DQS for ECC bytelane = read DQS of byte lane 3 |
| 142 | // |
| 143 | RdDqsDly[EccByte] = RdDqsDly[3]; |
| 144 | |
| 145 | // Write Data: |
| 146 | // Write Data for ECC bytelane = Write DQS for ECC + |
| 147 | // [write data for bytelane 3 - Write DQS for bytelane 3] |
| 148 | TempValue = (INT16) (WrDqsDly[EccByte] + (INT8) (WrDatDly[3] - WrDqsDly[3])); |
| 149 | if (TempValue < 0) { |
| 150 | TempValue = 0; |
| 151 | } |
| 152 | WrDatDly[EccByte] = (UINT8) TempValue; |
| 153 | |
| 154 | NBPtr->SetTrainDly (NBPtr, AccessRcvEnDly, DIMM_BYTE_ACCESS (Dimm, EccByte), RcvEnDly[EccByte]); |
| 155 | NBPtr->SetTrainDly (NBPtr, AccessRdDqsDly, DIMM_BYTE_ACCESS (Dimm, EccByte), RdDqsDly[EccByte]); |
| 156 | NBPtr->SetTrainDly (NBPtr, AccessWrDatDly, DIMM_BYTE_ACCESS (Dimm, EccByte), WrDatDly[EccByte]); |
| 157 | } |
| 158 | } |
| 159 | } |
| 160 | } |
| 161 | } |
| 162 | return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); |
| 163 | } |