zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * mtrci3.c |
| 6 | * |
| 7 | * Technology Control word initialization for DDR3 |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: (Mem/Tech/DDR3) |
| 12 | * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ |
| 13 | * |
| 14 | **/ |
| 15 | /***************************************************************************** |
| 16 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 17 | * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. |
| 18 | * All rights reserved. |
| 19 | * |
| 20 | * Redistribution and use in source and binary forms, with or without |
| 21 | * modification, are permitted provided that the following conditions are met: |
| 22 | * * Redistributions of source code must retain the above copyright |
| 23 | * notice, this list of conditions and the following disclaimer. |
| 24 | * * Redistributions in binary form must reproduce the above copyright |
| 25 | * notice, this list of conditions and the following disclaimer in the |
| 26 | * documentation and/or other materials provided with the distribution. |
| 27 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 28 | * its contributors may be used to endorse or promote products derived |
| 29 | * from this software without specific prior written permission. |
| 30 | * |
| 31 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 32 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 33 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 34 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 35 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 36 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 37 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 38 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 39 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 40 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 41 | * *************************************************************************** |
| 42 | * |
| 43 | */ |
| 44 | |
| 45 | /* |
| 46 | *---------------------------------------------------------------------------- |
| 47 | * MODULES USED |
| 48 | * |
| 49 | *---------------------------------------------------------------------------- |
| 50 | */ |
| 51 | |
| 52 | |
| 53 | |
| 54 | #include "AGESA.h" |
| 55 | #include "Ids.h" |
| 56 | #include "mm.h" |
| 57 | #include "mn.h" |
| 58 | #include "mu.h" |
| 59 | #include "mt.h" |
| 60 | #include "mt3.h" |
| 61 | #include "mtrci3.h" |
| 62 | #include "merrhdl.h" |
| 63 | #include "Filecode.h" |
| 64 | CODE_GROUP (G1_PEICC) |
| 65 | RDATA_GROUP (G1_PEICC) |
| 66 | |
| 67 | #define FILECODE PROC_MEM_TECH_DDR3_MTRCI3_FILECODE |
| 68 | /*---------------------------------------------------------------------------- |
| 69 | * DEFINITIONS AND MACROS |
| 70 | * |
| 71 | *---------------------------------------------------------------------------- |
| 72 | */ |
| 73 | |
| 74 | /*---------------------------------------------------------------------------- |
| 75 | * TYPEDEFS AND STRUCTURES |
| 76 | * |
| 77 | *---------------------------------------------------------------------------- |
| 78 | */ |
| 79 | |
| 80 | /*---------------------------------------------------------------------------- |
| 81 | * PROTOTYPES OF LOCAL FUNCTIONS |
| 82 | * |
| 83 | *---------------------------------------------------------------------------- |
| 84 | */ |
| 85 | |
| 86 | /*---------------------------------------------------------------------------- |
| 87 | * EXPORTED FUNCTIONS |
| 88 | * |
| 89 | *---------------------------------------------------------------------------- |
| 90 | */ |
| 91 | extern BUILD_OPT_CFG UserOptions; |
| 92 | |
| 93 | /* -----------------------------------------------------------------------------*/ |
| 94 | /** |
| 95 | * |
| 96 | * This function sends control words |
| 97 | * |
| 98 | * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK |
| 99 | * |
| 100 | */ |
| 101 | |
| 102 | VOID |
| 103 | MemTDramControlRegInit3 ( |
| 104 | IN OUT MEM_TECH_BLOCK *TechPtr |
| 105 | ) |
| 106 | { |
| 107 | UINT8 ChipSel; |
| 108 | UINT8 i; |
| 109 | UINT8 RawCard; |
| 110 | UINT8 Data; |
| 111 | UINT16 CsPresent; |
| 112 | |
| 113 | MEM_DATA_STRUCT *MemPtr; |
| 114 | MEM_NB_BLOCK *NBPtr; |
| 115 | |
| 116 | NBPtr = TechPtr->NBPtr; |
| 117 | MemPtr = NBPtr->MemPtr; |
| 118 | CsPresent = NBPtr->DCTPtr->Timings.CsPresent; |
| 119 | |
| 120 | MemUWait10ns (800, MemPtr); // wait 8us TACT must be changed to optimize to 8 MEM CLKs |
| 121 | |
| 122 | // Set EnDramInit to start DRAM initialization |
| 123 | |
| 124 | MemUWait10ns (600, MemPtr); // wait 6us for PLL LOCK |
| 125 | |
| 126 | for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel += 2) { |
| 127 | // |
| 128 | // If chip select present |
| 129 | // |
| 130 | if ((CsPresent & ((UINT16)3 << ChipSel)) != 0) { |
| 131 | NBPtr->SetBitField (NBPtr, BFMrsChipSel, ChipSel); |
| 132 | |
| 133 | // 2. Program F2x[1, 0]A8[CtrlWordCS]=bit mask for target chip selects. |
| 134 | NBPtr->SetBitField (NBPtr, BFCtrlWordCS, 3 << (ChipSel & 0xFE)); |
| 135 | |
| 136 | RawCard = NBPtr->ChannelPtr->RefRawCard[ChipSel >> 1]; |
| 137 | |
| 138 | for (i = 0; i <= 15; i++) { |
| 139 | // wait 8us for TMRD, must be changed to optimize to 8 MEM CLKs |
| 140 | MemUWait10ns (800, MemPtr); |
| 141 | if ((i != 6) && (i != 7)) { |
| 142 | Data = MemTGetCtlWord3 (TechPtr, i, RawCard, ChipSel); |
| 143 | MemTSendCtlWord3 (TechPtr, i, Data); |
| 144 | } |
| 145 | } |
| 146 | } |
| 147 | } |
| 148 | MemUWait10ns (600, MemPtr); // wait 6us for TSTAB |
| 149 | } |
| 150 | |
| 151 | /* -----------------------------------------------------------------------------*/ |
| 152 | /** |
| 153 | * |
| 154 | * This function calculates the ControlRC value |
| 155 | * |
| 156 | * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK |
| 157 | * @param[in] CtrlWordNum - control Word number. |
| 158 | * @param[in] RawCard - Raw Card |
| 159 | * @param[in] ChipSel - Target Chip Select |
| 160 | * @return Control Word value |
| 161 | */ |
| 162 | |
| 163 | UINT8 |
| 164 | MemTGetCtlWord3 ( |
| 165 | IN OUT MEM_TECH_BLOCK *TechPtr, |
| 166 | IN UINT8 CtrlWordNum, |
| 167 | IN UINT8 RawCard, |
| 168 | IN UINT8 ChipSel |
| 169 | ) |
| 170 | { |
| 171 | UINT8 Data; |
| 172 | UINT8 PowerDownMode; |
| 173 | DCT_STRUCT *DCTPtr; |
| 174 | CH_DEF_STRUCT *ChannelPtr; |
| 175 | |
| 176 | DCTPtr = TechPtr->NBPtr->DCTPtr; |
| 177 | ChannelPtr = TechPtr->NBPtr->ChannelPtr; |
| 178 | |
| 179 | Data = 0; //Default value for all control words is 0 |
| 180 | switch (CtrlWordNum) { |
| 181 | case 0: |
| 182 | Data = 0x02; // DA4=1 |
| 183 | break; |
| 184 | case 1: |
| 185 | if (DCTPtr->Timings.DimmSRPresent & ((UINT16) 1 << (ChipSel >> 1))) { |
| 186 | Data = 0x0C; // if single rank, set DBA1 and DBA0 |
| 187 | } |
| 188 | break; |
| 189 | case 2: |
| 190 | Data = ChannelPtr->CtrlWrd02[ChipSel >> 1]; |
| 191 | break; |
| 192 | case 3: |
| 193 | Data = ChannelPtr->CtrlWrd03[ChipSel >> 1]; |
| 194 | break; |
| 195 | case 4: |
| 196 | Data = ChannelPtr->CtrlWrd04[ChipSel >> 1]; |
| 197 | break; |
| 198 | case 5: |
| 199 | Data = ChannelPtr->CtrlWrd05[ChipSel >> 1]; |
| 200 | break; |
| 201 | case 8: |
| 202 | Data = ChannelPtr->CtrlWrd08[ChipSel >> 1]; |
| 203 | break; |
| 204 | case 9: |
| 205 | // RC9 = 0xD except when partial powerdown mode is enabled and mix SR/DR or SR/QR configurations, |
| 206 | // RC9 should be 0x9 for SR and and 0xD for DR or QR RDIMMs. |
| 207 | PowerDownMode = (UINT8) UserOptions.CfgPowerDownMode; |
| 208 | PowerDownMode = (!TechPtr->NBPtr->IsSupported[ChannelPDMode]) ? PowerDownMode : 0; |
| 209 | IDS_OPTION_HOOK (IDS_POWERDOWN_MODE, &PowerDownMode, &(TechPtr->NBPtr->MemPtr->StdHeader)); |
| 210 | if ((PowerDownMode == 1) && |
| 211 | (DCTPtr->Timings.DimmSRPresent & ((UINT16) 1 << (ChipSel >> 1))) && |
| 212 | ((DCTPtr->Timings.DimmDrPresent != 0) || (DCTPtr->Timings.DimmQrPresent != 0))) { |
| 213 | Data = 0x09; |
| 214 | } else { |
| 215 | Data = 0x0D; |
| 216 | } |
| 217 | break; |
| 218 | case 11: |
| 219 | Data = CONVERT_VDDIO_TO_ENCODED (TechPtr->RefPtr->DDR3Voltage); |
| 220 | break; |
| 221 | default:; |
| 222 | } |
| 223 | |
| 224 | return (Data & 0x0F); |
| 225 | } |
| 226 | /* -----------------------------------------------------------------------------*/ |
| 227 | /** |
| 228 | * |
| 229 | * This function sends control word command |
| 230 | * |
| 231 | * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK |
| 232 | * @param[in] CmdNum - control number. |
| 233 | * @param[in] Value - value to send |
| 234 | * |
| 235 | */ |
| 236 | |
| 237 | VOID |
| 238 | MemTSendCtlWord3 ( |
| 239 | IN OUT MEM_TECH_BLOCK *TechPtr, |
| 240 | IN UINT8 CmdNum, |
| 241 | IN UINT8 Value |
| 242 | ) |
| 243 | { |
| 244 | MEM_NB_BLOCK *NBPtr; |
| 245 | |
| 246 | NBPtr = TechPtr->NBPtr; |
| 247 | |
| 248 | // 1. Program MrsBank and MrsAddress. |
| 249 | // n = [BA2, A2, A1, A0]. |
| 250 | // data = [BA1, BA0, A4, A3]. |
| 251 | // Set all other bits in MrsAddress to zero. |
| 252 | // |
| 253 | NBPtr->SetBitField (NBPtr, BFMrsBank, ((CmdNum & 8) >> 1) | (Value >> 2)); |
| 254 | NBPtr->SetBitField (NBPtr, BFMrsAddress, ((Value & 3) << 3) | (CmdNum & 7)); |
| 255 | IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tCS%d RC%02d %04x\n", (MemNGetBitFieldNb (NBPtr, BFMrsChipSel) & 7), CmdNum, Value); |
| 256 | |
| 257 | // 2.Set SendCtrlWord=1 |
| 258 | NBPtr->SetBitField (NBPtr, BFSendCtrlWord, 1); |
| 259 | // 3.Wait for BFSendCtrlWord=0 |
| 260 | NBPtr->PollBitField (NBPtr, BFSendCtrlWord, 0, PCI_ACCESS_TIMEOUT, FALSE); |
| 261 | } |
| 262 | |
| 263 | /* -----------------------------------------------------------------------------*/ |
| 264 | /** |
| 265 | * |
| 266 | * This function sends specific control words commands before frequency change for certain DRAM buffers. |
| 267 | * |
| 268 | * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK |
| 269 | * |
| 270 | */ |
| 271 | |
| 272 | VOID |
| 273 | FreqChgCtrlWrd3 ( |
| 274 | IN OUT MEM_TECH_BLOCK *TechPtr |
| 275 | ) |
| 276 | { |
| 277 | UINT8 ChipSel; |
| 278 | UINT16 Speed; |
| 279 | UINT16 CsPresent; |
| 280 | |
| 281 | MEM_DATA_STRUCT *MemPtr; |
| 282 | MEM_NB_BLOCK *NBPtr; |
| 283 | |
| 284 | NBPtr = TechPtr->NBPtr; |
| 285 | MemPtr = NBPtr->MemPtr; |
| 286 | Speed = NBPtr->DCTPtr->Timings.Speed; |
| 287 | CsPresent = NBPtr->DCTPtr->Timings.CsPresent; |
| 288 | |
| 289 | |
| 290 | for (ChipSel = 0; ChipSel < MAX_CS_PER_CHANNEL; ChipSel += 2) { |
| 291 | // |
| 292 | // If chip select present. |
| 293 | // |
| 294 | if ((CsPresent & ((UINT16)3 << ChipSel)) != 0) { |
| 295 | |
| 296 | NBPtr->SetBitField (NBPtr, BFMrsChipSel, ChipSel); |
| 297 | // program F2x[1, 0]A8[CtrlWordCS]=bit mask for target chip selects. |
| 298 | NBPtr->SetBitField (NBPtr, BFCtrlWordCS, 3 << (ChipSel & 0xFE)); |
| 299 | |
| 300 | //wait 8us for TMRD, must be changed to optimize to 8 MEM CLKs |
| 301 | MemUWait10ns (800, MemPtr); |
| 302 | if (Speed == DDR800_FREQUENCY) { |
| 303 | MemTSendCtlWord3 (TechPtr, 0x0A, 0); |
| 304 | } else if (Speed == DDR1066_FREQUENCY) { |
| 305 | MemTSendCtlWord3 (TechPtr, 0x0A, 1); |
| 306 | } else if (Speed == DDR1333_FREQUENCY) { |
| 307 | MemTSendCtlWord3 (TechPtr, 0x0A, 2); |
| 308 | } else if (Speed == DDR1600_FREQUENCY) { |
| 309 | MemTSendCtlWord3 (TechPtr, 0x0A, 3); |
| 310 | } else if (Speed == DDR1866_FREQUENCY) { |
| 311 | MemTSendCtlWord3 (TechPtr, 0x0A, 4); |
| 312 | } else { |
| 313 | ASSERT (FALSE); |
| 314 | } |
| 315 | } |
| 316 | } |
| 317 | } |
| 318 | |