zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * mntrain3.c |
| 6 | * |
| 7 | * Common Northbridge function for training flow for DDR3 |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: (Mem/NB) |
| 12 | * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ |
| 13 | * |
| 14 | **/ |
| 15 | /***************************************************************************** |
| 16 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 17 | * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. |
| 18 | * All rights reserved. |
| 19 | * |
| 20 | * Redistribution and use in source and binary forms, with or without |
| 21 | * modification, are permitted provided that the following conditions are met: |
| 22 | * * Redistributions of source code must retain the above copyright |
| 23 | * notice, this list of conditions and the following disclaimer. |
| 24 | * * Redistributions in binary form must reproduce the above copyright |
| 25 | * notice, this list of conditions and the following disclaimer in the |
| 26 | * documentation and/or other materials provided with the distribution. |
| 27 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 28 | * its contributors may be used to endorse or promote products derived |
| 29 | * from this software without specific prior written permission. |
| 30 | * |
| 31 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 32 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 33 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 34 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 35 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 36 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 37 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 38 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 39 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 40 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 41 | * *************************************************************************** |
| 42 | * |
| 43 | */ |
| 44 | |
| 45 | /* |
| 46 | *---------------------------------------------------------------------------- |
| 47 | * MODULES USED |
| 48 | * |
| 49 | *---------------------------------------------------------------------------- |
| 50 | */ |
| 51 | |
| 52 | |
| 53 | |
| 54 | #include "AGESA.h" |
| 55 | #include "amdlib.h" |
| 56 | #include "Ids.h" |
| 57 | #include "OptionMemory.h" |
| 58 | #include "mm.h" |
| 59 | #include "mn.h" |
| 60 | #include "mt.h" |
| 61 | #include "Filecode.h" |
| 62 | CODE_GROUP (G1_PEICC) |
| 63 | RDATA_GROUP (G1_PEICC) |
| 64 | |
| 65 | #define FILECODE PROC_MEM_NB_MNTRAIN3_FILECODE |
| 66 | /* features */ |
| 67 | #include "mftds.h" |
| 68 | /*---------------------------------------------------------------------------- |
| 69 | * DEFINITIONS AND MACROS |
| 70 | * |
| 71 | *---------------------------------------------------------------------------- |
| 72 | */ |
| 73 | |
| 74 | /*---------------------------------------------------------------------------- |
| 75 | * TYPEDEFS AND STRUCTURES |
| 76 | * |
| 77 | *---------------------------------------------------------------------------- |
| 78 | */ |
| 79 | |
| 80 | /*---------------------------------------------------------------------------- |
| 81 | * PROTOTYPES OF LOCAL FUNCTIONS |
| 82 | * |
| 83 | *---------------------------------------------------------------------------- |
| 84 | */ |
| 85 | |
| 86 | BOOLEAN |
| 87 | STATIC |
| 88 | MemNHwWlPart2Nb ( |
| 89 | IN OUT MEM_TECH_BLOCK *TechPtr |
| 90 | ); |
| 91 | /*---------------------------------------------------------------------------- |
| 92 | * EXPORTED FUNCTIONS |
| 93 | * |
| 94 | *---------------------------------------------------------------------------- |
| 95 | */ |
| 96 | extern MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[]; |
| 97 | /* -----------------------------------------------------------------------------*/ |
| 98 | /** |
| 99 | * |
| 100 | * This function initiates DQS training |
| 101 | * |
| 102 | * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK |
| 103 | * |
| 104 | */ |
| 105 | |
| 106 | BOOLEAN |
| 107 | MemNDQSTiming3Nb ( |
| 108 | IN OUT MEM_NB_BLOCK *NBPtr |
| 109 | ) |
| 110 | { |
| 111 | MEM_TECH_BLOCK *TechPtr; |
| 112 | UINT8 i; |
| 113 | BOOLEAN Retval; |
| 114 | TechPtr = NBPtr->TechPtr; |
| 115 | Retval = TRUE; |
| 116 | if (TechPtr->NBPtr->MCTPtr->NodeMemSize) { |
| 117 | //Execute Technology specific training features |
| 118 | i = 0; |
| 119 | while (memTrainSequenceDDR3[i].TrainingSequenceEnabled != 0) { |
| 120 | if (memTrainSequenceDDR3[i].TrainingSequenceEnabled (NBPtr)) { |
| 121 | NBPtr->TrainingSequenceIndex = i; |
| 122 | Retval = memTrainSequenceDDR3[i].TrainingSequence (NBPtr); |
| 123 | break; |
| 124 | } |
| 125 | i++; |
| 126 | } |
| 127 | } |
| 128 | return Retval; |
| 129 | } |
| 130 | /* -----------------------------------------------------------------------------*/ |
| 131 | /** |
| 132 | * |
| 133 | * This function initiates DQS training for Server NB |
| 134 | * |
| 135 | * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK |
| 136 | * |
| 137 | */ |
| 138 | |
| 139 | BOOLEAN |
| 140 | memNSequenceDDR3Nb ( |
| 141 | IN OUT MEM_NB_BLOCK *NBPtr |
| 142 | ) |
| 143 | { |
| 144 | MEM_TECH_BLOCK *TechPtr; |
| 145 | UINT8 i; |
| 146 | TechPtr = NBPtr->TechPtr; |
| 147 | i = NBPtr->TrainingSequenceIndex; |
| 148 | if (TechPtr->NBPtr->MCTPtr->NodeMemSize != 0) { |
| 149 | AGESA_TESTPOINT (TpProcMemBeforeAgesaHookBeforeDQSTraining, &NBPtr->MemPtr->StdHeader); |
| 150 | IDS_HDT_CONSOLE (MEM_FLOW, "\nCalling out to Platform BIOS...\n"); |
| 151 | if (AgesaHookBeforeDQSTraining (NBPtr->MCTPtr->SocketId, TechPtr->NBPtr->MemPtr) == AGESA_SUCCESS) { |
| 152 | // Right now we do not have anything to do if the callout is implemented |
| 153 | } |
| 154 | AGESA_TESTPOINT (TpProcMemAfterAgesaHookBeforeDQSTraining, &NBPtr->MemPtr->StdHeader); |
| 155 | //Execute Technology specific training features |
| 156 | if (memTrainSequenceDDR3[i].MemTechFeatBlock->EnterHardwareTraining (TechPtr)) { |
| 157 | TechPtr->TechnologySpecificHook[LrdimmBuf2DramTrain] (TechPtr, NULL); |
| 158 | if (memTrainSequenceDDR3[i].MemTechFeatBlock->SwWLTraining (TechPtr)) { |
| 159 | MemFInitTableDrive (NBPtr, MTAfterSwWLTrn); |
| 160 | if (memTrainSequenceDDR3[i].MemTechFeatBlock->HwBasedWLTrainingPart1 (TechPtr)) { |
| 161 | MemFInitTableDrive (NBPtr, MTAfterHwWLTrnP1); |
| 162 | if (memTrainSequenceDDR3[i].MemTechFeatBlock->HwBasedDQSReceiverEnableTrainingPart1 (TechPtr)) { |
| 163 | MemFInitTableDrive (NBPtr, MTAfterHwRxEnTrnP1); |
| 164 | // If target speed is higher than start-up speed, do frequency change and second pass of WL |
| 165 | do { |
| 166 | if (MemNHwWlPart2Nb (TechPtr)) { |
| 167 | if (memTrainSequenceDDR3[i].MemTechFeatBlock->TrainExitHwTrn (TechPtr)) { |
| 168 | IDS_OPTION_HOOK (IDS_PHY_DLL_STANDBY_CTRL, NBPtr, &(NBPtr->MemPtr->StdHeader)); |
| 169 | if (memTrainSequenceDDR3[i].MemTechFeatBlock->NonOptimizedSWDQSRecEnTrainingPart1 (TechPtr)) { |
| 170 | if (memTrainSequenceDDR3[i].MemTechFeatBlock->OptimizedSwDqsRecEnTrainingPart1 (TechPtr)) { |
| 171 | MemFInitTableDrive (NBPtr, MTAfterSwRxEnTrn); |
| 172 | if (memTrainSequenceDDR3[i].MemTechFeatBlock->NonOptimizedSRdWrPosTraining (TechPtr)) { |
| 173 | if (memTrainSequenceDDR3[i].MemTechFeatBlock->OptimizedSRdWrPosTraining (TechPtr)) { |
| 174 | MemFInitTableDrive (NBPtr, MTAfterDqsRwPosTrn); |
| 175 | if (!NBPtr->FamilySpecificHook[MemPstateStageChange] (NBPtr, NULL)) { |
| 176 | continue; |
| 177 | } |
| 178 | if (NBPtr->Execute1dMaxRdLatTraining) { |
| 179 | do { |
| 180 | if (memTrainSequenceDDR3[i].MemTechFeatBlock->MaxRdLatencyTraining (TechPtr)) { |
| 181 | MemFInitTableDrive (NBPtr, MTAfterMaxRdLatTrn); |
| 182 | } |
| 183 | } while (NBPtr->ChangeNbFrequency (NBPtr)); |
| 184 | } else { |
| 185 | memTrainSequenceDDR3[i].MemTechFeatBlock->TrainExitHwTrn (TechPtr); |
| 186 | } |
| 187 | } |
| 188 | } |
| 189 | } |
| 190 | } |
| 191 | } |
| 192 | } |
| 193 | } while (NBPtr->MemPstateStage == MEMORY_PSTATE_2ND_STAGE); |
| 194 | } |
| 195 | } |
| 196 | } |
| 197 | } |
| 198 | MemTMarkTrainFail (TechPtr); |
| 199 | } |
| 200 | return TRUE; |
| 201 | } |
| 202 | /* -----------------------------------------------------------------------------*/ |
| 203 | /** |
| 204 | * |
| 205 | * This function executes HW WL at multiple speeds |
| 206 | * |
| 207 | * @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK |
| 208 | * @return TRUE - No errors occurred |
| 209 | * FALSE - errors occurred |
| 210 | */ |
| 211 | |
| 212 | BOOLEAN |
| 213 | STATIC |
| 214 | MemNHwWlPart2Nb ( |
| 215 | IN OUT MEM_TECH_BLOCK *TechPtr |
| 216 | ) |
| 217 | { |
| 218 | BOOLEAN retVal; |
| 219 | UINT8 i; |
| 220 | retVal = TRUE; |
| 221 | i = TechPtr->NBPtr->TrainingSequenceIndex; |
| 222 | while ((TechPtr->NBPtr->DCTPtr->Timings.TargetSpeed > TechPtr->NBPtr->DCTPtr->Timings.Speed) && (TechPtr->NBPtr->MemPstateStage != MEMORY_PSTATE_1ST_STAGE)) { |
| 223 | TechPtr->PrevSpeed = TechPtr->NBPtr->DCTPtr->Timings.Speed; |
| 224 | if (TechPtr->NBPtr->RampUpFrequency (TechPtr->NBPtr)) { |
| 225 | TechPtr->TechnologySpecificHook[LrdimmBuf2DramTrain] (TechPtr, NULL); |
| 226 | if (!memTrainSequenceDDR3[i].MemTechFeatBlock->HwBasedWLTrainingPart2 (TechPtr)) { |
| 227 | retVal = FALSE; |
| 228 | break; |
| 229 | } |
| 230 | MemFInitTableDrive (TechPtr->NBPtr, MTAfterHwWLTrnP2); |
| 231 | if (!memTrainSequenceDDR3[i].MemTechFeatBlock->HwBasedDQSReceiverEnableTrainingPart2 (TechPtr)) { |
| 232 | retVal = FALSE; |
| 233 | break; |
| 234 | } |
| 235 | MemFInitTableDrive (TechPtr->NBPtr, MTAfterHwRxEnTrnP2); |
| 236 | } else { |
| 237 | retVal = FALSE; |
| 238 | break; |
| 239 | } |
| 240 | } |
| 241 | return retVal; |
| 242 | } |