zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * mnottn.c |
| 6 | * |
| 7 | * Northbridge Non-SPD timings for TN |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: (Mem/NB/TN) |
| 12 | * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ |
| 13 | * |
| 14 | **/ |
| 15 | /***************************************************************************** |
| 16 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 17 | * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. |
| 18 | * All rights reserved. |
| 19 | * |
| 20 | * Redistribution and use in source and binary forms, with or without |
| 21 | * modification, are permitted provided that the following conditions are met: |
| 22 | * * Redistributions of source code must retain the above copyright |
| 23 | * notice, this list of conditions and the following disclaimer. |
| 24 | * * Redistributions in binary form must reproduce the above copyright |
| 25 | * notice, this list of conditions and the following disclaimer in the |
| 26 | * documentation and/or other materials provided with the distribution. |
| 27 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 28 | * its contributors may be used to endorse or promote products derived |
| 29 | * from this software without specific prior written permission. |
| 30 | * |
| 31 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 32 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 33 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 34 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 35 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 36 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 37 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 38 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 39 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 40 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 41 | * *************************************************************************** |
| 42 | * |
| 43 | */ |
| 44 | |
| 45 | /* |
| 46 | *---------------------------------------------------------------------------- |
| 47 | * MODULES USED |
| 48 | * |
| 49 | *---------------------------------------------------------------------------- |
| 50 | */ |
| 51 | |
| 52 | |
| 53 | |
| 54 | #include "AGESA.h" |
| 55 | #include "Ids.h" |
| 56 | #include "mm.h" |
| 57 | #include "mn.h" |
| 58 | #include "OptionMemory.h" |
| 59 | #include "mntn.h" |
| 60 | #include "mu.h" |
| 61 | #include "Filecode.h" |
| 62 | CODE_GROUP (G3_DXE) |
| 63 | RDATA_GROUP (G3_DXE) |
| 64 | |
| 65 | #define FILECODE PROC_MEM_NB_TN_MNOTTN_FILECODE |
| 66 | /*---------------------------------------------------------------------------- |
| 67 | * DEFINITIONS AND MACROS |
| 68 | * |
| 69 | *---------------------------------------------------------------------------- |
| 70 | */ |
| 71 | |
| 72 | /*---------------------------------------------------------------------------- |
| 73 | * TYPEDEFS AND STRUCTURES |
| 74 | * |
| 75 | *---------------------------------------------------------------------------- |
| 76 | */ |
| 77 | |
| 78 | /*---------------------------------------------------------------------------- |
| 79 | * PROTOTYPES OF LOCAL FUNCTIONS |
| 80 | * |
| 81 | *---------------------------------------------------------------------------- |
| 82 | */ |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 83 | |
| 84 | /*---------------------------------------------------------------------------- |
| 85 | * EXPORTED FUNCTIONS |
| 86 | * |
| 87 | *---------------------------------------------------------------------------- |
| 88 | */ |
| 89 | |
| 90 | extern BUILD_OPT_CFG UserOptions; |
| 91 | |
| 92 | /* -----------------------------------------------------------------------------*/ |
| 93 | /** |
| 94 | * |
| 95 | * |
| 96 | * This function sets the non-SPD timings |
| 97 | * |
| 98 | * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK |
| 99 | * |
| 100 | * @return TRUE - No fatal error occurs. |
| 101 | * @return FALSE - Fatal error occurs. |
| 102 | */ |
| 103 | |
| 104 | BOOLEAN |
| 105 | MemNOtherTimingTN ( |
| 106 | IN OUT MEM_NB_BLOCK *NBPtr |
| 107 | ) |
| 108 | { |
| 109 | UINT8 Dct; |
| 110 | IDS_HDT_CONSOLE (MEM_STATUS, "\nStart Programming of Non-SPD Timings.\n"); |
| 111 | for (Dct = 0; Dct < MAX_DCTS_PER_NODE_TN; Dct++) { |
| 112 | IDS_HDT_CONSOLE (MEM_STATUS, "\tDct %d\n", Dct); |
| 113 | MemNSwitchDCTNb (NBPtr, Dct); |
| 114 | if (NBPtr->DCTPtr->Timings.DctDimmValid > 0) { |
| 115 | MemNSetOtherTimingTN (NBPtr); |
| 116 | } |
| 117 | } |
| 118 | return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); |
| 119 | } |
| 120 | |
| 121 | /*---------------------------------------------------------------------------- |
| 122 | * LOCAL FUNCTIONS |
| 123 | * |
| 124 | *---------------------------------------------------------------------------- |
| 125 | */ |
| 126 | |
| 127 | /* -----------------------------------------------------------------------------*/ |
| 128 | /** |
| 129 | * |
| 130 | * |
| 131 | * This function sets the non-SPD timings in PCI registers |
| 132 | * |
| 133 | * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK |
| 134 | * |
| 135 | */ |
| 136 | |
| 137 | VOID |
| 138 | MemNSetOtherTimingTN ( |
| 139 | IN OUT MEM_NB_BLOCK *NBPtr |
| 140 | ) |
| 141 | { |
| 142 | INT8 ROD; |
| 143 | INT8 WOD; |
| 144 | INT8 LD; |
| 145 | INT8 WrEarlyx2; |
| 146 | INT8 CDDTrdrdSdDc; |
| 147 | INT8 CDDTrdrdDd; |
| 148 | INT8 CDDTwrwrDd; |
| 149 | INT8 CDDTwrwrSdDc; |
| 150 | INT8 CDDTrwtTO; |
| 151 | INT8 CDDTwrrd; |
| 152 | UINT8 TrdrdSdDc; |
| 153 | UINT8 TrdrdDd; |
| 154 | UINT8 TwrwrSdDc; |
| 155 | UINT8 TwrwrDd; |
| 156 | UINT8 TrdrdSdSc; |
| 157 | UINT8 TwrwrSdSc; |
| 158 | UINT8 Twrrd; |
| 159 | UINT8 TrwtTO; |
| 160 | BOOLEAN PerRankTimingEn; |
| 161 | |
| 162 | CH_DEF_STRUCT *ChannelPtr; |
| 163 | ChannelPtr = NBPtr->ChannelPtr; |
| 164 | |
| 165 | PerRankTimingEn = (BOOLEAN) (MemNGetBitFieldNb (NBPtr, BFPerRankTimingEn)); |
| 166 | // |
| 167 | // Latency Difference (LD) = Tcl - Tcwl |
| 168 | // |
| 169 | LD = (INT8) (MemNGetBitFieldNb (NBPtr, BFTcl)) - (INT8) (MemNGetBitFieldNb (NBPtr, BFTcwl)); |
| 170 | |
| 171 | // |
| 172 | // Read ODT Delay (ROD) = MAX ( 0, (RdOdtOnDuration - 6)) + MAX ( 0, (RdOdtTrnOnDly - LD)) |
| 173 | // |
| 174 | ROD = MAX (0, (INT8) (MemNGetBitFieldNb (NBPtr, BFRdOdtOnDuration) - 6)) + |
| 175 | MAX ( 0, (INT8) (MemNGetBitFieldNb (NBPtr, BFRdOdtTrnOnDly) - LD)); |
| 176 | // |
| 177 | // Write ODT Delay (WOD) = MAX (0, (WrOdtOnDuration - 6)) |
| 178 | // |
| 179 | WOD = MAX (0, (INT8) (MemNGetBitFieldNb (NBPtr, BFWrOdtOnDuration) - 6)); |
| 180 | // |
| 181 | // WrEarly = ABS (WrDqDqsEarly) / 2 |
| 182 | // |
| 183 | WrEarlyx2 = (INT8) MemNGetBitFieldNb (NBPtr, BFWrDqDqsEarly); |
| 184 | |
| 185 | IDS_HDT_CONSOLE (MEM_FLOW, "\t\tLD: %d ROD: %d WOD: %d WrEarlyx2: %d\n\n", LD, ROD, WOD, WrEarlyx2); |
| 186 | // |
| 187 | // Read to Read Timing (TrdrdSdSc, TrdrdScDc, TrdrdDd) |
| 188 | // |
| 189 | // TrdrdSdSc = 1. |
| 190 | // TrdrdSdDc (in MEMCLKs) = MAX(TrdrdSdSc, 3 + (IF (D18F2xA8_dct[1:0][PerRankTimingEn]) |
| 191 | // THEN CEIL(CDDTrdrdSdDc / 2 ) ELSE 0 ENDIF)). |
| 192 | // TrdrdDd = MAX(TrdrdSdDc, CEIL(MAX(ROD + 3, CDDTrdrdDd/2 + 3.5))) |
| 193 | // |
| 194 | TrdrdSdSc = 1; |
| 195 | |
| 196 | CDDTrdrdSdDc = (INT8) MemNCalcCDDNb (NBPtr, AccessRcvEnDly, AccessRcvEnDly, TRUE, FALSE); |
| 197 | TrdrdSdDc = MAX (0, PerRankTimingEn ? (3 + (CDDTrdrdSdDc + 1) / 2) : 3); |
| 198 | TrdrdSdDc = MAX (TrdrdSdSc, TrdrdSdDc); |
| 199 | |
| 200 | CDDTrdrdDd = (INT8) MemNCalcCDDNb (NBPtr, AccessRcvEnDly, AccessRcvEnDly, FALSE, TRUE); |
| 201 | TrdrdDd = MAX (ROD + 3, (CDDTrdrdDd + 7 + 1) / 2); |
| 202 | TrdrdDd = MAX (TrdrdSdDc, TrdrdDd); |
| 203 | |
| 204 | MemNSetBitFieldNb (NBPtr, BFTrdrdDd, (UINT32) TrdrdDd); |
| 205 | MemNSetBitFieldNb (NBPtr, BFTrdrdSdDc, (UINT32) TrdrdSdDc); |
| 206 | MemNSetBitFieldNb (NBPtr, BFTrdrdSdSc, (UINT32) TrdrdSdSc); |
| 207 | // |
| 208 | // Write to Write Timing (TwrwrSdSc, TwrwrScDc, TwrwrDd) |
| 209 | // |
| 210 | // TwrwrSdSc = 1. |
| 211 | // TwrwrSdDc = CEIL(MAX(WOD + 3, CDDTwrwrSdDc / 2 + |
| 212 | // (IF (D18F2xA8_dct[1:0][PerRankTimingEn]) THEN 3.5 ELSE 3 ENDIF))). |
| 213 | // |
| 214 | // TwrwrDd = CEIL (MAX (WOD + 3, CDDTwrwrDd / 2 + 3.5)) |
| 215 | // TwrwrSdSc <= TwrwrSdDc <= TwrwrDd |
| 216 | // |
| 217 | TwrwrSdSc = 1; |
| 218 | |
| 219 | CDDTwrwrSdDc = (INT8) MemNCalcCDDNb (NBPtr, AccessWrDqsDly, AccessWrDqsDly, TRUE, FALSE); |
| 220 | TwrwrSdDc = (UINT8) MAX (WOD + 3, (CDDTwrwrSdDc + (PerRankTimingEn ? 7 : 6) + 1 ) / 2); |
| 221 | |
| 222 | CDDTwrwrDd = (INT8) MemNCalcCDDNb (NBPtr, AccessWrDqsDly, AccessWrDqsDly, FALSE, TRUE); |
| 223 | TwrwrDd = (UINT8) MAX ((UINT8) (WOD + 3), (CDDTwrwrDd + 7 + 1) / 2); |
| 224 | |
| 225 | TwrwrSdDc = (TwrwrSdSc <= TwrwrSdDc) ? TwrwrSdDc : TwrwrSdSc; |
| 226 | TwrwrDd = (TwrwrSdDc <= TwrwrDd) ? TwrwrDd : TwrwrSdDc; |
| 227 | |
| 228 | MemNSetBitFieldNb (NBPtr, BFTwrwrDd, (UINT32) TwrwrDd); |
| 229 | MemNSetBitFieldNb (NBPtr, BFTwrwrSdDc, (UINT32) TwrwrSdDc); |
| 230 | MemNSetBitFieldNb (NBPtr, BFTwrwrSdSc, (UINT32) TwrwrSdSc); |
| 231 | // |
| 232 | // Write to Read DIMM Termination Turn-around |
| 233 | // |
| 234 | // Twrrd = MAX ( 1, CEIL (MAX (WOD, (CDDTwrrd / 2) + 0.5 - WrEarly) - LD + 3)) |
| 235 | // |
| 236 | CDDTwrrd = (INT8) MemNCalcCDDNb (NBPtr, AccessWrDqsDly, AccessRcvEnDly, TRUE, TRUE); |
| 237 | Twrrd = MAX (1, MAX (WOD, (CDDTwrrd + 1 - WrEarlyx2 + 1) / 2) - LD + 3); |
| 238 | |
| 239 | MemNSetBitFieldNb (NBPtr, BFTwrrd, (UINT32) Twrrd); |
| 240 | // |
| 241 | // Read to Write Turnaround for Data, DQS Contention |
| 242 | // |
| 243 | // TrwtTO = CEIL (MAX (ROD, (CDDTrwtTO / 2) - 0.5 + WrEarly) + LD + 3) |
| 244 | // |
| 245 | CDDTrwtTO = (INT8) MemNCalcCDDNb (NBPtr, AccessRcvEnDly, AccessWrDqsDly, TRUE, TRUE); |
| 246 | |
| 247 | TrwtTO = MAX ((ChannelPtr->Dimms == 1 ? 0 : ROD) , (CDDTrwtTO - 1 + WrEarlyx2 + 1) / 2) + LD + 3; |
| 248 | |
| 249 | MemNSetBitFieldNb (NBPtr, BFTrwtTO, (UINT32) TrwtTO); |
| 250 | // |
| 251 | // Read to Write Turnaround for opportunistic Write Bursting |
| 252 | // |
| 253 | // TrwtWB = TrwtTO + 1 |
| 254 | // |
| 255 | MemNSetBitFieldNb (NBPtr, BFTrwtWB, (UINT32) TrwtTO + 1); |
| 256 | |
| 257 | IDS_HDT_CONSOLE (MEM_FLOW, "\t\t TrdrdSdSc : %02x\n", TrdrdSdSc); |
| 258 | IDS_HDT_CONSOLE (MEM_FLOW, "\t\tCDDTrdrdSdDc : %02x TrdrdSdDc : %02x\n", CDDTrdrdSdDc, TrdrdSdDc); |
| 259 | IDS_HDT_CONSOLE (MEM_FLOW, "\t\tCDDTrdrdDd : %02x TrdrdDd : %02x\n\n", CDDTrdrdDd, TrdrdDd); |
| 260 | |
| 261 | IDS_HDT_CONSOLE (MEM_FLOW, "\t\t TwrwrSdSc : %02x\n", TwrwrSdSc); |
| 262 | IDS_HDT_CONSOLE (MEM_FLOW, "\t\tCDDTwrwrSdDc : %02x TwrwrSdDc : %02x\n", CDDTwrwrSdDc, TwrwrSdDc ); |
| 263 | IDS_HDT_CONSOLE (MEM_FLOW, "\t\tCDDTwrwrDd : %02x TwrwrDd : %02x\n\n", CDDTwrwrDd, TwrwrDd); |
| 264 | |
| 265 | IDS_HDT_CONSOLE (MEM_FLOW, "\t\t TrwtWB : %02x\n", TrwtTO + 1); |
| 266 | IDS_HDT_CONSOLE (MEM_FLOW, "\t\tCDDTwrrd : %02x Twrrd : %02x\n", (UINT8) CDDTwrrd, (UINT8) Twrrd ); |
| 267 | IDS_HDT_CONSOLE (MEM_FLOW, "\t\tCDDTrwtTO : %02x TrwtTO : %02x\n\n", (UINT8) CDDTrwtTO, (UINT8) TrwtTO ); |
| 268 | } |