zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * mnmcttn.c |
| 6 | * |
| 7 | * Northbridge TN MCT supporting functions |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: (Mem/NB/TN) |
| 12 | * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ |
| 13 | * |
| 14 | **/ |
| 15 | /***************************************************************************** |
| 16 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 17 | * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. |
| 18 | * All rights reserved. |
| 19 | * |
| 20 | * Redistribution and use in source and binary forms, with or without |
| 21 | * modification, are permitted provided that the following conditions are met: |
| 22 | * * Redistributions of source code must retain the above copyright |
| 23 | * notice, this list of conditions and the following disclaimer. |
| 24 | * * Redistributions in binary form must reproduce the above copyright |
| 25 | * notice, this list of conditions and the following disclaimer in the |
| 26 | * documentation and/or other materials provided with the distribution. |
| 27 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 28 | * its contributors may be used to endorse or promote products derived |
| 29 | * from this software without specific prior written permission. |
| 30 | * |
| 31 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 32 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 33 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 34 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 35 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 36 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 37 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 38 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 39 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 40 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 41 | * *************************************************************************** |
| 42 | * |
| 43 | */ |
| 44 | |
| 45 | /* |
| 46 | *---------------------------------------------------------------------------- |
| 47 | * MODULES USED |
| 48 | * |
| 49 | *---------------------------------------------------------------------------- |
| 50 | */ |
| 51 | |
| 52 | #include "AGESA.h" |
| 53 | #include "amdlib.h" |
| 54 | #include "Ids.h" |
| 55 | #include "mport.h" |
| 56 | #include "GnbRegistersTN.h" |
| 57 | #include "GnbRegisterAccTN.h" |
| 58 | #include "mm.h" |
| 59 | #include "mn.h" |
| 60 | #include "OptionMemory.h" |
| 61 | #include "mntn.h" |
| 62 | #include "cpuFeatures.h" |
| 63 | #include "Filecode.h" |
| 64 | #include "mftds.h" |
| 65 | #include "mu.h" |
| 66 | CODE_GROUP (G3_DXE) |
| 67 | RDATA_GROUP (G3_DXE) |
| 68 | |
| 69 | |
| 70 | #define FILECODE PROC_MEM_NB_TN_MNMCTTN_FILECODE |
| 71 | /*---------------------------------------------------------------------------- |
| 72 | * DEFINITIONS AND MACROS |
| 73 | * |
| 74 | *---------------------------------------------------------------------------- |
| 75 | */ |
| 76 | #define _16MB_RJ16 0x0100 |
| 77 | /*---------------------------------------------------------------------------- |
| 78 | * TYPEDEFS AND STRUCTURES |
| 79 | * |
| 80 | *---------------------------------------------------------------------------- |
| 81 | */ |
| 82 | |
| 83 | /*---------------------------------------------------------------------------- |
| 84 | * PROTOTYPES OF LOCAL FUNCTIONS |
| 85 | * |
| 86 | *---------------------------------------------------------------------------- |
| 87 | */ |
| 88 | |
| 89 | |
| 90 | /*---------------------------------------------------------------------------- |
| 91 | * EXPORTED FUNCTIONS |
| 92 | * |
| 93 | *---------------------------------------------------------------------------- |
| 94 | */ |
| 95 | extern BUILD_OPT_CFG UserOptions; |
| 96 | |
| 97 | /* -----------------------------------------------------------------------------*/ |
| 98 | /** |
| 99 | * |
| 100 | * |
| 101 | * This function force memory Pstate to M0 |
| 102 | * |
| 103 | * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK |
| 104 | * |
| 105 | * @return TRUE - No fatal error occurs. |
| 106 | * @return FALSE - Fatal error occurs. |
| 107 | */ |
| 108 | |
| 109 | BOOLEAN |
| 110 | MemNInitializeMctTN ( |
| 111 | IN OUT MEM_NB_BLOCK *NBPtr |
| 112 | ) |
| 113 | { |
| 114 | MemNSetBitFieldNb (NBPtr, BFMemPsSel, 0); |
| 115 | MemNSetBitFieldNb (NBPtr, BFEnSplitMctDatBuffers, 1); |
| 116 | |
| 117 | MemUMFenceInstr (); |
| 118 | MemNSetBitFieldNb (NBPtr, BFMctEccDisLatOptEn, 1); |
| 119 | MemUMFenceInstr (); |
| 120 | |
| 121 | MemNBrdcstSetUnConditionalNb (NBPtr, BFPStateToAccess, 0); |
| 122 | |
| 123 | MemNForcePhyToM0Unb (NBPtr); |
| 124 | |
| 125 | return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); |
| 126 | } |
| 127 | |
| 128 | /* -----------------------------------------------------------------------------*/ |
| 129 | /** |
| 130 | * |
| 131 | * |
| 132 | * This function sets final values for specific registers. |
| 133 | * |
| 134 | * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK |
| 135 | * |
| 136 | * @return TRUE - No fatal error occurs. |
| 137 | * @return FALSE - Fatal error occurs. |
| 138 | */ |
| 139 | |
| 140 | BOOLEAN |
| 141 | MemNFinalizeMctTN ( |
| 142 | IN OUT MEM_NB_BLOCK *NBPtr |
| 143 | ) |
| 144 | { |
| 145 | MEM_DATA_STRUCT *MemPtr; |
| 146 | MEM_PARAMETER_STRUCT *RefPtr; |
| 147 | DRAM_PREFETCH_MODE DramPrefetchMode; |
| 148 | UINT16 Speed; |
| 149 | UINT32 Value32; |
| 150 | UINT8 DcqBwThrotWm1; |
| 151 | UINT8 DcqBwThrotWm2; |
| 152 | UINT8 Dct; |
| 153 | |
| 154 | MemPtr = NBPtr->MemPtr; |
| 155 | RefPtr = MemPtr->ParameterListPtr; |
| 156 | DramPrefetchMode = MemPtr->PlatFormConfig->PlatformProfile.AdvancedPerformanceProfile.DramPrefetchMode; |
| 157 | Speed = NBPtr->DCTPtr->Timings.Speed; |
| 158 | |
| 159 | // |
| 160 | // F2x11C |
| 161 | // |
| 162 | MemNSetBitFieldNb (NBPtr, BFMctCfgHiReg, 0x0CE00F31); |
| 163 | if (DramPrefetchMode == DISABLE_DRAM_PREFETCH_FOR_IO || DramPrefetchMode == DISABLE_DRAM_PREFETCHER) { |
| 164 | MemNSetBitFieldNb (NBPtr, BFPrefIoDis, 1); |
| 165 | } |
| 166 | |
| 167 | if (DramPrefetchMode == DISABLE_DRAM_PREFETCH_FOR_CPU || DramPrefetchMode == DISABLE_DRAM_PREFETCHER) { |
| 168 | MemNSetBitFieldNb (NBPtr, BFPrefCpuDis, 1); |
| 169 | } |
| 170 | |
| 171 | |
| 172 | if (Speed == DDR667_FREQUENCY) { |
| 173 | DcqBwThrotWm1 = 3; |
| 174 | DcqBwThrotWm2 = 4; |
| 175 | } else if (Speed == DDR800_FREQUENCY) { |
| 176 | DcqBwThrotWm1 = 3; |
| 177 | DcqBwThrotWm2 = 5; |
| 178 | } else if (Speed == DDR1066_FREQUENCY) { |
| 179 | DcqBwThrotWm1 = 4; |
| 180 | DcqBwThrotWm2 = 6; |
| 181 | } else if (Speed == DDR1333_FREQUENCY) { |
| 182 | DcqBwThrotWm1 = 5; |
| 183 | DcqBwThrotWm2 = 8; |
| 184 | } else if (Speed == DDR1600_FREQUENCY) { |
| 185 | DcqBwThrotWm1 = 6; |
| 186 | DcqBwThrotWm2 = 9; |
| 187 | } else if (Speed == DDR1866_FREQUENCY) { |
| 188 | DcqBwThrotWm1 = 7; |
| 189 | DcqBwThrotWm2 = 10; |
| 190 | } else { |
| 191 | DcqBwThrotWm1 = 8; |
| 192 | DcqBwThrotWm2 = 12; |
| 193 | } |
| 194 | // |
| 195 | // F2x1B0 |
| 196 | // |
| 197 | Value32 = MemNGetBitFieldNb (NBPtr, BFExtMctCfgLoReg); |
| 198 | Value32 &= 0x003FE8C0; |
| 199 | Value32 |= 0x0FC01001; |
| 200 | MemNSetBitFieldNb (NBPtr, BFExtMctCfgLoReg, Value32); |
| 201 | |
| 202 | // |
| 203 | // F2x1B4 |
| 204 | // |
| 205 | Value32 = MemNGetBitFieldNb (NBPtr, BFExtMctCfgHiReg); |
| 206 | Value32 &= 0xFFFFFC00; |
| 207 | Value32 |= (((UINT32) DcqBwThrotWm2 << 5) | (UINT32) DcqBwThrotWm1); |
| 208 | MemNSetBitFieldNb (NBPtr, BFExtMctCfgHiReg, Value32); |
| 209 | |
| 210 | for (Dct = 0; Dct < MAX_DCTS_PER_NODE_TN; Dct++) { |
| 211 | MemNSwitchDCTNb (NBPtr, Dct); |
| 212 | |
| 213 | if (NBPtr->DCTPtr->Timings.DctMemSize != 0) { |
| 214 | // |
| 215 | // Phy Power Saving |
| 216 | // |
| 217 | MemNPhyPowerSavingMPstateUnb (NBPtr); |
| 218 | if (NBPtr->MemPstateStage == MEMORY_PSTATE_3RD_STAGE) { |
| 219 | MemNChangeMemPStateContextNb (NBPtr, 1); |
| 220 | MemNPhyPowerSavingMPstateUnb (NBPtr); |
| 221 | MemFInitTableDrive (NBPtr, MTAfterSettingMemoryPstate1); |
| 222 | MemNChangeMemPStateContextNb (NBPtr, 0); |
| 223 | } |
| 224 | // |
| 225 | // Power Down Enable |
| 226 | // |
| 227 | if (NBPtr->RefPtr->EnablePowerDown) { |
| 228 | MemNSetBitFieldNb (NBPtr, BFPowerDownEn, 1); |
| 229 | } |
| 230 | } |
| 231 | } |
| 232 | |
| 233 | // Set LockDramCfg |
| 234 | if (IsFeatureEnabled (C6Cstate, NBPtr->MemPtr->PlatFormConfig, &(NBPtr->MemPtr->StdHeader))) { |
| 235 | IDS_SKIP_HOOK (IDS_LOCK_DRAM_CFG, NBPtr, &NBPtr->MemPtr->StdHeader) { |
| 236 | MemNSetBitFieldNb (NBPtr, BFLockDramCfg, 1); |
| 237 | } |
| 238 | } |
| 239 | |
| 240 | return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); |
| 241 | } |
| 242 | |
| 243 | /* -----------------------------------------------------------------------------*/ |
| 244 | /** |
| 245 | * |
| 246 | * This function create the HT memory map for TN |
| 247 | * |
| 248 | * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK |
| 249 | * |
| 250 | * @return TRUE - No fatal error occurs. |
| 251 | * @return FALSE - Fatal error occurs. |
| 252 | */ |
| 253 | |
| 254 | BOOLEAN |
| 255 | MemNHtMemMapInitTN ( |
| 256 | IN OUT MEM_NB_BLOCK *NBPtr |
| 257 | ) |
| 258 | { |
| 259 | UINT8 WeReMask; |
| 260 | UINT32 BottomIo; |
| 261 | UINT32 HoleOffset; |
| 262 | UINT32 DctSelBaseAddr; |
| 263 | UINT32 NodeSysBase; |
| 264 | UINT32 NodeSysLimit; |
| 265 | MEM_PARAMETER_STRUCT *RefPtr; |
| 266 | DIE_STRUCT *MCTPtr; |
| 267 | |
| 268 | RefPtr = NBPtr->RefPtr; |
| 269 | MCTPtr = NBPtr->MCTPtr; |
| 270 | // |
| 271 | // Physical addresses in this function are right adjusted by 16 bits ([47:16]) |
| 272 | // They are BottomIO, HoleOffset, DctSelBaseAddr, NodeSysBase, NodeSysLimit. |
| 273 | // |
| 274 | |
| 275 | // Enforce bottom of IO be be 128MB aligned |
| 276 | BottomIo = (RefPtr->BottomIo & 0xF8) << 8; |
| 277 | |
| 278 | if (MCTPtr->NodeMemSize != 0) { |
| 279 | NodeSysBase = 0; |
| 280 | NodeSysLimit = MCTPtr->NodeMemSize - 1; |
| 281 | DctSelBaseAddr = MCTPtr->DctData[0].Timings.DctMemSize; |
| 282 | |
| 283 | if (NodeSysLimit >= BottomIo) { |
| 284 | // HW Dram Remap |
| 285 | MCTPtr->Status[SbHWHole] = TRUE; |
| 286 | RefPtr->GStatus[GsbHWHole] = TRUE; |
| 287 | MCTPtr->NodeHoleBase = BottomIo; |
| 288 | RefPtr->HoleBase = BottomIo; |
| 289 | |
| 290 | HoleOffset = _4GB_RJ16 - BottomIo; |
| 291 | |
| 292 | NodeSysLimit += HoleOffset; |
| 293 | |
| 294 | if ((DctSelBaseAddr > 0) && (DctSelBaseAddr < BottomIo)) { |
| 295 | HoleOffset += DctSelBaseAddr; |
| 296 | } else { |
| 297 | if (DctSelBaseAddr >= BottomIo) { |
| 298 | DctSelBaseAddr += HoleOffset; |
| 299 | } |
| 300 | HoleOffset += NodeSysBase; |
| 301 | } |
| 302 | |
| 303 | MemNSetBitFieldNb (NBPtr, BFDramHoleBase, BottomIo >> 8); |
| 304 | MemNSetBitFieldNb (NBPtr, BFDramHoleOffset, HoleOffset >> 7); |
| 305 | MemNSetBitFieldNb (NBPtr, BFDramHoleValid, 1); |
| 306 | MemNSetBitFieldNb (NBPtr, BFDramMemHoistValid, 1); |
| 307 | } else { |
| 308 | // No Remapping. Normal Contiguous mapping |
| 309 | } |
| 310 | MCTPtr->NodeSysBase = NodeSysBase; |
| 311 | MCTPtr->NodeSysLimit = NodeSysLimit; |
| 312 | RefPtr->SysLimit = MCTPtr->NodeSysLimit; |
| 313 | |
| 314 | WeReMask = 3; |
| 315 | // Set the Dram base and set the WE and RE flags in the base. |
| 316 | MemNSetBitFieldNb (NBPtr, BFDramBaseReg0, (NodeSysBase << 8) | WeReMask); |
| 317 | MemNSetBitFieldNb (NBPtr, BFDramBaseHiReg0, NodeSysBase >> 24); |
| 318 | // Set the Dram limit and set DstNode. |
| 319 | MemNSetBitFieldNb (NBPtr, BFDramLimitReg0, ((NodeSysLimit << 8) & 0xFFFF0000)); |
| 320 | MemNSetBitFieldNb (NBPtr, BFDramLimitHiReg0, NodeSysLimit >> 24); |
| 321 | |
| 322 | MemNSetBitFieldNb (NBPtr, BFDramBaseAddr, NodeSysBase >> (27 - 16)); |
| 323 | MemNSetBitFieldNb (NBPtr, BFDramLimitAddr, NodeSysLimit >> (27 - 16)); |
| 324 | |
| 325 | if ((MCTPtr->DctData[1].Timings.DctMemSize != 0) && (!NBPtr->Ganged)) { |
| 326 | MemNSetBitFieldNb (NBPtr, BFDctSelBaseAddr, DctSelBaseAddr >> 11); |
| 327 | MemNSetBitFieldNb (NBPtr, BFDctSelHiRngEn, 1); |
| 328 | MemNSetBitFieldNb (NBPtr, BFDctSelHi, 1); |
| 329 | MemNSetBitFieldNb (NBPtr, BFDctSelBaseOffset, DctSelBaseAddr >> 10); |
| 330 | } |
| 331 | } |
| 332 | return (BOOLEAN) (NBPtr->MCTPtr->ErrCode < AGESA_FATAL); |
| 333 | } |
| 334 | |
| 335 | /* -----------------------------------------------------------------------------*/ |
| 336 | /** |
| 337 | * |
| 338 | * |
| 339 | * Report the Uma size that is going to be allocated. |
| 340 | * Total system memory UMASize |
| 341 | * >= 2G 512M |
| 342 | * >=1G 256M |
| 343 | * <1G 64M |
| 344 | * |
| 345 | * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK |
| 346 | * |
| 347 | * @return Uma size [31:0] = Addr [47:16] |
| 348 | */ |
| 349 | UINT32 |
| 350 | MemNGetUmaSizeTN ( |
| 351 | IN OUT MEM_NB_BLOCK *NBPtr |
| 352 | ) |
| 353 | { |
| 354 | UINT32 SysMemSize; |
| 355 | UINT32 SizeOfUma; |
| 356 | |
| 357 | SysMemSize = NBPtr->RefPtr->SysLimit + 1; |
| 358 | SysMemSize = (SysMemSize + 0x100) & 0xFFFFF000; // Ignore 16MB allocated for C6 when finding UMA size |
| 359 | if (SysMemSize >= 0x8000) { |
| 360 | SizeOfUma = 512 << (20 - 16); |
| 361 | } else if (SysMemSize >= 0x4000) { |
| 362 | SizeOfUma = 256 << (20 - 16); |
| 363 | } else { |
| 364 | SizeOfUma = 64 << (20 - 16); |
| 365 | } |
| 366 | |
| 367 | return SizeOfUma; |
| 368 | } |
| 369 | |
| 370 | /* -----------------------------------------------------------------------------*/ |
| 371 | /** |
| 372 | * |
| 373 | * This function allocates 16MB of memory for C6 storage when it is requested to be enabled |
| 374 | * |
| 375 | * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK |
| 376 | * |
| 377 | */ |
| 378 | VOID |
| 379 | MemNAllocateC6StorageTN ( |
| 380 | IN OUT MEM_NB_BLOCK *NBPtr |
| 381 | ) |
| 382 | { |
| 383 | UINT32 SysLimit; |
| 384 | UINT32 DramLimitReg; |
| 385 | |
| 386 | if (NBPtr->SharedPtr->C6Enabled || IsFeatureEnabled (C6Cstate, NBPtr->MemPtr->PlatFormConfig, &(NBPtr->MemPtr->StdHeader))) { |
| 387 | |
| 388 | SysLimit = NBPtr->RefPtr->SysLimit; |
| 389 | |
| 390 | // Calculate new SysLimit |
| 391 | if (!NBPtr->SharedPtr->C6Enabled) { |
| 392 | // System memory available is reduced by 16MB |
| 393 | SysLimit -= _16MB_RJ16; |
| 394 | |
| 395 | NBPtr->MCTPtr->NodeSysLimit = SysLimit; |
| 396 | NBPtr->RefPtr->SysLimit = SysLimit; |
| 397 | NBPtr->SharedPtr->C6Enabled = TRUE; |
| 398 | |
| 399 | // Set TOPMEM and MTRRs (only need to be done once for BSC) |
| 400 | MemNC6AdjustMSRs (NBPtr); |
| 401 | } |
| 402 | |
| 403 | // Set Dram Limit |
| 404 | DramLimitReg = MemNGetBitFieldNb (NBPtr, BFDramLimitReg0) & 0x0000FFFF; |
| 405 | MemNSetBitFieldNb (NBPtr, BFDramLimitReg0, ((SysLimit << 8) & 0xFFFF0000) | DramLimitReg); |
| 406 | MemNSetBitFieldNb (NBPtr, BFDramLimitHiReg0, SysLimit >> 24); |
| 407 | |
| 408 | MemNSetBitFieldNb (NBPtr, BFCoreStateSaveDestNode, 0); |
| 409 | |
| 410 | // Set BFCC6SaveEn |
| 411 | MemNSetBitFieldNb (NBPtr, BFCC6SaveEn, 1); |
| 412 | // LockDramCfg will be set in FinalizeMCT |
| 413 | } |
| 414 | } |
| 415 | |
| 416 | /* -----------------------------------------------------------------------------*/ |
| 417 | /** |
| 418 | * |
| 419 | * This function adjusts NB pstate norbridge voltage for TN |
| 420 | * |
| 421 | * @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK |
| 422 | * |
| 423 | */ |
| 424 | VOID |
| 425 | MemNAdjustNBPstateVolTN ( |
| 426 | IN OUT MEM_NB_BLOCK *NBPtr |
| 427 | ) |
| 428 | { |
| 429 | |
| 430 | D0F0xBC_xE0104168_STRUCT D0F0xBC_xE0104168; |
| 431 | D0F0xBC_xE010416C_STRUCT D0F0xBC_xE010416C; |
| 432 | D0F0xBC_xE0104170_STRUCT D0F0xBC_xE0104170; |
| 433 | UINT8 MemClkVidHi; |
| 434 | UINT8 MemClkVidLo; |
| 435 | UINT8 MemPstate; |
| 436 | UINT8 NbVid; |
| 437 | UINT8 NbPs; |
| 438 | UINT8 NbPstateMaxVal; |
| 439 | |
| 440 | IDS_HDT_CONSOLE (MEM_FLOW, "\nStart NB Pstate voltage adjustment.\n"); |
| 441 | |
| 442 | GnbRegisterReadTN (TYPE_D0F0xBC, D0F0xBC_xE0104168_ADDRESS, &D0F0xBC_xE0104168.Value, 0, &(NBPtr->MemPtr->StdHeader)); |
| 443 | GnbRegisterReadTN (TYPE_D0F0xBC, D0F0xBC_xE010416C_ADDRESS, &D0F0xBC_xE010416C.Value, 0, &(NBPtr->MemPtr->StdHeader)); |
| 444 | GnbRegisterReadTN (TYPE_D0F0xBC, D0F0xBC_xE0104170_ADDRESS, &D0F0xBC_xE0104170.Value, 0, &(NBPtr->MemPtr->StdHeader)); |
| 445 | |
| 446 | IDS_HDT_CONSOLE (MEM_FLOW, "\t\tD0F0xBC_xE0104168: %08x\n", D0F0xBC_xE0104168.Value); |
| 447 | IDS_HDT_CONSOLE (MEM_FLOW, "\t\tD0F0xBC_xE010416C: %08x\n", D0F0xBC_xE010416C.Value); |
| 448 | IDS_HDT_CONSOLE (MEM_FLOW, "\t\tD0F0xBC_xE0104170: %08x\n", D0F0xBC_xE0104170.Value); |
| 449 | |
| 450 | // MemClkVidHi = read D0F0xBC_xE0104168 through D0F0xBC_xE0104170 to find the VID code corresponding |
| 451 | // to the M0 MEMCLK. If the M0 MEMCLK is not found, use the next higher defined MEMCLK as the target. |
| 452 | switch (NBPtr->DCTPtr->Timings.TargetSpeed) { |
| 453 | case DDR667_FREQUENCY: |
| 454 | MemClkVidHi = (UINT8) D0F0xBC_xE0104168.Field.MemClkVid0_7_0; |
| 455 | break; |
| 456 | case DDR800_FREQUENCY: |
| 457 | MemClkVidHi = (UINT8) D0F0xBC_xE0104168.Field.MemClkVid1_7_0; |
| 458 | break; |
| 459 | case DDR1066_FREQUENCY: |
| 460 | MemClkVidHi = (UINT8) D0F0xBC_xE0104168.Field.MemClkVid2_7_0; |
| 461 | break; |
| 462 | case DDR1333_FREQUENCY: |
| 463 | MemClkVidHi = (UINT8) D0F0xBC_xE0104168.Field.MemClkVid3_1_0 | ((UINT8) D0F0xBC_xE010416C.Field.MemClkVid3_7_2 << 2); |
| 464 | break; |
| 465 | case DDR1600_FREQUENCY: |
| 466 | MemClkVidHi = (UINT8) D0F0xBC_xE010416C.Field.MemClkVid4_7_0; |
| 467 | break; |
| 468 | case DDR1866_FREQUENCY: |
| 469 | MemClkVidHi = (UINT8) D0F0xBC_xE010416C.Field.MemClkVid5_7_0; |
| 470 | break; |
| 471 | case DDR2100_FREQUENCY: |
| 472 | MemClkVidHi = (UINT8) D0F0xBC_xE010416C.Field.MemClkVid6_7_0; |
| 473 | break; |
| 474 | case DDR2133_FREQUENCY: |
| 475 | MemClkVidHi = (UINT8) D0F0xBC_xE010416C.Field.MemClkVid7_1_0 | ((UINT8) D0F0xBC_xE0104170.Field.MemClkVid7_7_2 << 2); |
| 476 | break; |
| 477 | case DDR2400_FREQUENCY: |
| 478 | MemClkVidHi = (UINT8) D0F0xBC_xE0104170.Field.MemClkVid8_7_0; |
| 479 | break; |
| 480 | default: |
| 481 | // If the M0 MEMCLK is greater than MemClkVid8, use the MemClkVid8 VID as the target |
| 482 | MemClkVidHi = (UINT8) D0F0xBC_xE0104170.Field.MemClkVid8_7_0; |
| 483 | } |
| 484 | |
| 485 | // MemClkVidLo = read D0F0xBC_xE0104168 through D0F0xBC_xE0104170 to find the VID code corresponding |
| 486 | // to the M1 MEMCLK. If the M1 MEMCLK is not found, use the next higher defined MEMCLK as the target. |
| 487 | MemClkVidLo = (UINT8) D0F0xBC_xE0104168.Field.MemClkVid0_7_0; |
| 488 | |
| 489 | IDS_HDT_CONSOLE (MEM_FLOW, "\t\tOriginal MemClkVidLo: %02x\n", MemClkVidLo); |
| 490 | IDS_HDT_CONSOLE (MEM_FLOW, "\t\tOriginal MemClkVidHi: %02x\n", MemClkVidHi); |
| 491 | |
| 492 | // If D18F5x188[NbOffsetTrim] == 01b, MemClkVid = Fuse[MemClkVid] - 4 (-25mV offset so add 25mV to VID) |
| 493 | // Else if D18F5x188[NbOffsetTrim] == 11b, MemClkVid = Fuse[MemClkVid] + 4 (+25mV offset so decrease 25mV from VID) |
| 494 | // Else MemClkVid = Fuse[MemClkVid] |
| 495 | if (MemNGetBitFieldNb (NBPtr, BFNbOffsetTrim) == 1) { |
| 496 | MemClkVidLo -= 4; |
| 497 | MemClkVidHi -= 4; |
| 498 | IDS_HDT_CONSOLE (MEM_FLOW, "\t\tAdd 25mV\n"); |
| 499 | } else if (MemNGetBitFieldNb (NBPtr, BFNbOffsetTrim) == 3) { |
| 500 | MemClkVidLo += 4; |
| 501 | MemClkVidHi += 4; |
| 502 | IDS_HDT_CONSOLE (MEM_FLOW, "\t\tDecrease 25mV\n"); |
| 503 | } |
| 504 | IDS_HDT_CONSOLE (MEM_FLOW, "\t\tAdjusted MemClkVidLo: %02x\n", MemClkVidLo); |
| 505 | IDS_HDT_CONSOLE (MEM_FLOW, "\t\tAdjusted MemClkVidHi: %02x\n", MemClkVidHi); |
| 506 | |
| 507 | // For each NB P-state from NBP0 through D18F5x170[NbPstateMaxVal]: |
| 508 | // If ((D18F5x1[6C:60][MemPstate] == 0) && (MemClkVidHi voltage > D18F5x1[6C:60][NbVid] voltage)): |
| 509 | // Program D18F5x1[6C:60][NbVid] == MemClkVidHi. |
| 510 | // If ((D18F5x1[6C:60][MemPstate] == 1) && (MemClkVidLo voltage > D18F5x1[6C:60][NbVid] voltage)): |
| 511 | // Program D18F5x1[6C:60][NbVid] == MemClkVidLo. |
| 512 | IDS_HDT_CONSOLE (MEM_FLOW, "\t\tNBPs\tNbVid\tMemPstate\tOverride\n"); |
| 513 | NbPstateMaxVal = (UINT8) MemNGetBitFieldNb (NBPtr, BFNbPstateMaxVal); |
| 514 | for (NbPs = 0; NbPs <= NbPstateMaxVal; NbPs ++) { |
| 515 | NbVid = (UINT8) MemNGetBitFieldNb (NBPtr, BFNbVid0 + (NbPs << 1)); |
| 516 | MemPstate = (UINT8) MemNGetBitFieldNb (NBPtr, BFMemPstate0 + NbPs); |
| 517 | IDS_HDT_CONSOLE (MEM_FLOW, "\t\t %01d \t %02x \t %01d \t", NbPs, NbVid, MemPstate); |
| 518 | // higher voltage correspond to smaller VID |
| 519 | if ((MemPstate == 0) && (MemClkVidHi < NbVid)) { |
| 520 | MemNSetBitFieldNb (NBPtr, BFNbVid0 + (NbPs << 1), MemClkVidHi); |
| 521 | IDS_HDT_CONSOLE (MEM_FLOW, "MemClkVidHi\n"); |
| 522 | } else if ((MemPstate == 1) && (MemClkVidLo < NbVid)) { |
| 523 | MemNSetBitFieldNb (NBPtr, BFNbVid0 + (NbPs << 1), MemClkVidLo); |
| 524 | IDS_HDT_CONSOLE (MEM_FLOW, "MemClkVidLo\n"); |
| 525 | } else { |
| 526 | IDS_HDT_CONSOLE (MEM_FLOW, "No change\n"); |
| 527 | } |
| 528 | } |
| 529 | } |
| 530 | |
| 531 | /*---------------------------------------------------------------------------- |
| 532 | * LOCAL FUNCTIONS |
| 533 | * |
| 534 | *---------------------------------------------------------------------------- |
| 535 | */ |