zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * AMD Integrated Debug Routines for performance analysis |
| 6 | * |
| 7 | * Contains AMD AGESA debug macros and functions for performance analysis |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: IDS |
| 12 | * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ |
| 13 | */ |
| 14 | /***************************************************************************** |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 15 | * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. |
| 16 | * All rights reserved. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 17 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 18 | * Redistribution and use in source and binary forms, with or without |
| 19 | * modification, are permitted provided that the following conditions are met: |
| 20 | * * Redistributions of source code must retain the above copyright |
| 21 | * notice, this list of conditions and the following disclaimer. |
| 22 | * * Redistributions in binary form must reproduce the above copyright |
| 23 | * notice, this list of conditions and the following disclaimer in the |
| 24 | * documentation and/or other materials provided with the distribution. |
| 25 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 26 | * its contributors may be used to endorse or promote products derived |
| 27 | * from this software without specific prior written permission. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 28 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 29 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 30 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 31 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 32 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 33 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 34 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 35 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 36 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 37 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 38 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 39 | ****************************************************************************** |
| 40 | */ |
| 41 | /*---------------------------------------------------------------------------------------- |
| 42 | * M O D U L E S U S E D |
| 43 | *---------------------------------------------------------------------------------------- |
| 44 | */ |
| 45 | |
| 46 | #include "AGESA.h" |
| 47 | #include "Ids.h" |
| 48 | #include "IdsLib.h" |
| 49 | #include "IdsDpHdtout.h" |
| 50 | #include "heapManager.h" |
| 51 | #include "cpuFamilyTranslation.h" |
| 52 | #include "amdlib.h" |
| 53 | |
| 54 | #define FILECODE PROC_IDS_PERF_IDSPERF_FILECODE |
| 55 | /** |
| 56 | * |
| 57 | * IDS Performance function for Output to HDT. |
| 58 | * |
| 59 | * Invoke communications with the HDT environment to allow the user to issue |
| 60 | * debug commands. If the sign = 0x0, HDT Control Register will be initialized to |
| 61 | * catch the special I/O for HDT_OUT. Otherwise, it will inform HDT script |
| 62 | * function what is meaning for the value to output to HDT. |
| 63 | * |
| 64 | * @param[in] Command HDT_OUT Command. |
| 65 | * @param[in] Data The Data to output to HDT. |
| 66 | * @param[in,out] StdHeader The Pointer of AGESA Header |
| 67 | * |
| 68 | **/ |
| 69 | #define HDTOUT_COMMAND 0x99cc |
| 70 | #define HDTOUT_TIME_ANALYSE (0xD0BF0000ul | HDTOUT_COMMAND) |
| 71 | |
| 72 | VOID |
| 73 | IdsPerfHdtOut ( |
| 74 | IN UINT16 Command, |
| 75 | IN UINT32 Data, |
| 76 | IN OUT AMD_CONFIG_PARAMS *StdHeader |
| 77 | ) |
| 78 | { |
| 79 | IdsOutPort (HDTOUT_TIME_ANALYSE, Data, 0); |
| 80 | } |
| 81 | |
| 82 | /** |
| 83 | * |
| 84 | * Get Ids Performance analysis table pointer in the AGESA Heap. |
| 85 | * |
| 86 | * @param[in] LineInFile ((FILECODE) shift 16)+ Line number |
| 87 | * @param[in,out] StdHeader The Pointer of AGESA Header |
| 88 | * |
| 89 | * @retval AGESA_SUCCESS Success to get the pointer of Performance analysis Table. |
| 90 | * @retval AGESA_ERROR Fail to get the pointer of Performance analysis Table. |
| 91 | * @retval AGESA_UNSUPPORTED Get an exclude testpoint |
| 92 | * |
| 93 | **/ |
| 94 | AGESA_STATUS |
| 95 | IdsPerfTimestamp ( |
| 96 | IN UINT32 LineInFile, |
| 97 | IN OUT AMD_CONFIG_PARAMS *StdHeader |
| 98 | ) |
| 99 | { |
| 100 | AGESA_STATUS status; |
| 101 | UINT32 Index; |
| 102 | TP_Perf_STRUCT *PerfTableEntry; |
| 103 | ALLOCATE_HEAP_PARAMS AllocHeapParams; |
| 104 | LOCATE_HEAP_PTR LocateHeapStructPtr; |
| 105 | UINT64 CurrentTsc; |
| 106 | |
| 107 | //if heap is not ready yet, don't invoke locate buffer, or else will cause event log & locate heap dead loop |
| 108 | if (StdHeader->HeapStatus != HEAP_DO_NOT_EXIST_YET ) { |
| 109 | LibAmdMsrRead (TSC, &CurrentTsc, StdHeader); |
| 110 | |
| 111 | LocateHeapStructPtr.BufferHandle = IDS_CHECK_POINT_PERF_HANDLE; |
| 112 | LocateHeapStructPtr.BufferPtr = NULL; |
| 113 | status = HeapLocateBuffer (&LocateHeapStructPtr, StdHeader); |
| 114 | if (status == AGESA_SUCCESS) { |
| 115 | PerfTableEntry = (TP_Perf_STRUCT *) (LocateHeapStructPtr.BufferPtr); |
| 116 | } else { |
| 117 | AllocHeapParams.RequestedBufferSize = sizeof (TP_Perf_STRUCT); |
| 118 | AllocHeapParams.BufferHandle = IDS_CHECK_POINT_PERF_HANDLE; |
| 119 | AllocHeapParams.Persist = HEAP_SYSTEM_MEM; |
| 120 | status = HeapAllocateBuffer (&AllocHeapParams, StdHeader); |
| 121 | if (status != AGESA_SUCCESS) { |
| 122 | return status; |
| 123 | } |
| 124 | PerfTableEntry = (TP_Perf_STRUCT *) (AllocHeapParams.BufferPtr); |
| 125 | LibAmdMemFill (PerfTableEntry, 0, sizeof (TP_Perf_STRUCT), StdHeader); |
| 126 | PerfTableEntry->Signature = 'EMIT'; |
| 127 | } |
| 128 | |
| 129 | Index = PerfTableEntry ->Index; |
| 130 | |
| 131 | PerfTableEntry ->TP[Index].LineInFile = LineInFile; |
| 132 | PerfTableEntry ->TP[Index].StartTsc = CurrentTsc; |
| 133 | PerfTableEntry ->Index = ++Index; |
| 134 | } |
| 135 | return AGESA_SUCCESS; |
| 136 | } |
| 137 | |
| 138 | typedef struct _PERFREGBACKUP { |
| 139 | UINT64 SMsr; |
| 140 | UINT32 Dr0Reg; |
| 141 | UINT32 Dr7Reg; |
| 142 | UINT32 Cr4Reg; |
| 143 | } PERFREGBACKUP; |
| 144 | |
| 145 | VOID |
| 146 | IdsPerfSaveReg ( |
| 147 | IN OUT PERFREGBACKUP * perfreg, |
| 148 | IN OUT AMD_CONFIG_PARAMS *StdHeader |
| 149 | ) |
| 150 | { |
| 151 | |
| 152 | LibAmdReadCpuReg (DR0_REG, &perfreg->Dr0Reg); |
| 153 | |
| 154 | LibAmdReadCpuReg (DR7_REG, &perfreg->Dr7Reg); |
| 155 | |
| 156 | LibAmdReadCpuReg (CR4_REG, &perfreg->Cr4Reg); |
| 157 | } |
| 158 | |
| 159 | VOID |
| 160 | IdsPerfRestoreReg ( |
| 161 | IN PERFREGBACKUP * perfreg, |
| 162 | IN OUT AMD_CONFIG_PARAMS *StdHeader |
| 163 | ) |
| 164 | { |
| 165 | |
| 166 | LibAmdWriteCpuReg (DR0_REG, perfreg->Dr0Reg); |
| 167 | |
| 168 | LibAmdWriteCpuReg (DR7_REG, perfreg->Dr7Reg); |
| 169 | |
| 170 | LibAmdWriteCpuReg (CR4_REG, perfreg->Cr4Reg); |
| 171 | } |
| 172 | /** |
| 173 | * Output Test Point function . |
| 174 | * |
| 175 | * @param[in,out] StdHeader The Pointer of Standard Header. |
| 176 | * |
| 177 | * @retval AGESA_SUCCESS Success to get the pointer of IDS_CHECK_POINT_PERF_HANDLE. |
| 178 | * @retval AGESA_ERROR Fail to get the pointer of IDS_CHECK_POINT_PERF_HANDLE. |
| 179 | * |
| 180 | **/ |
| 181 | AGESA_STATUS |
| 182 | IdsPerfAnalyseTimestamp ( |
| 183 | IN OUT AMD_CONFIG_PARAMS *StdHeader |
| 184 | ) |
| 185 | { |
| 186 | AGESA_STATUS status; |
| 187 | LOCATE_HEAP_PTR LocateHeapStructPtr; |
| 188 | UINT32 TscRateInMhz; |
| 189 | CPU_SPECIFIC_SERVICES *FamilySpecificServices; |
| 190 | PERFREGBACKUP PerfReg; |
| 191 | UINT32 CR4reg; |
| 192 | UINT64 SMsr; |
| 193 | |
| 194 | LocateHeapStructPtr.BufferHandle = IDS_CHECK_POINT_PERF_HANDLE; |
| 195 | LocateHeapStructPtr.BufferPtr = NULL; |
| 196 | status = HeapLocateBuffer (&LocateHeapStructPtr, StdHeader); |
| 197 | if (status != AGESA_SUCCESS) { |
| 198 | return status; |
| 199 | } |
| 200 | GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader); |
| 201 | FamilySpecificServices->GetTscRate (FamilySpecificServices, &TscRateInMhz, StdHeader); |
| 202 | ((TP_Perf_STRUCT *) (LocateHeapStructPtr.BufferPtr)) ->TscInMhz = TscRateInMhz; |
| 203 | if (AmdIdsHdtOutSupport () == FALSE) { |
| 204 | //Init break point |
| 205 | IdsPerfSaveReg (&PerfReg, StdHeader); |
| 206 | |
| 207 | SMsr |= 1; |
| 208 | |
| 209 | LibAmdWriteCpuReg (DR2_REG, 0x99cc); |
| 210 | LibAmdWriteCpuReg (DR7_REG, 0x02000420); |
| 211 | |
| 212 | LibAmdReadCpuReg (CR4_REG, &CR4reg); |
| 213 | LibAmdWriteCpuReg (CR4_REG, CR4reg | ((UINT32)1 << 3)); |
| 214 | |
| 215 | IdsPerfHdtOut (1, (UINT32) (UINT64) LocateHeapStructPtr.BufferPtr, StdHeader); |
| 216 | IdsPerfRestoreReg (&PerfReg, StdHeader); |
| 217 | } |
| 218 | return status; |
| 219 | } |
| 220 | |
| 221 | |