zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * AMD Integrated Debug library Routines |
| 6 | * |
| 7 | * Contains AMD AGESA debug macros and library functions |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: IDS |
| 12 | * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ |
| 13 | */ |
| 14 | /***************************************************************************** |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 15 | * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. |
| 16 | * All rights reserved. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 17 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 18 | * Redistribution and use in source and binary forms, with or without |
| 19 | * modification, are permitted provided that the following conditions are met: |
| 20 | * * Redistributions of source code must retain the above copyright |
| 21 | * notice, this list of conditions and the following disclaimer. |
| 22 | * * Redistributions in binary form must reproduce the above copyright |
| 23 | * notice, this list of conditions and the following disclaimer in the |
| 24 | * documentation and/or other materials provided with the distribution. |
| 25 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 26 | * its contributors may be used to endorse or promote products derived |
| 27 | * from this software without specific prior written permission. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 28 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 29 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 30 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 31 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 32 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 33 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 34 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 35 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 36 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 37 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 38 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 39 | ****************************************************************************** |
| 40 | */ |
| 41 | /*---------------------------------------------------------------------------------------- |
| 42 | * M O D U L E S U S E D |
| 43 | *---------------------------------------------------------------------------------------- |
| 44 | */ |
| 45 | |
| 46 | #include "AGESA.h" |
| 47 | #include "Ids.h" |
| 48 | #include "amdlib.h" |
| 49 | #include "GeneralServices.h" |
| 50 | #include "cpuServices.h" |
| 51 | #include "cpuFamilyTranslation.h" |
| 52 | #include "cpuPstateTables.h" |
| 53 | #include "IdsLib.h" |
| 54 | #include "heapManager.h" |
| 55 | |
| 56 | #include "mm.h" |
| 57 | #include "mn.h" |
| 58 | #include "cpuLateInit.h" |
| 59 | #include "Filecode.h" |
| 60 | CODE_GROUP (G1_PEICC) |
| 61 | RDATA_GROUP (G1_PEICC) |
| 62 | |
| 63 | #define FILECODE PROC_IDS_LIBRARY_IDSLIB_FILECODE |
| 64 | |
| 65 | /*---------------------------------------------------------------------------- |
| 66 | * DEFINITIONS AND MACROS |
| 67 | * |
| 68 | *---------------------------------------------------------------------------- |
| 69 | */ |
| 70 | extern CPU_FAMILY_SUPPORT_TABLE PstateFamilyServiceTable; |
| 71 | |
| 72 | /*---------------------------------------------------------------------------- |
| 73 | * EXPORTED FUNCTIONS |
| 74 | * |
| 75 | *---------------------------------------------------------------------------- |
| 76 | */ |
| 77 | |
| 78 | /** |
| 79 | * |
| 80 | * Get IDS NV table pointer in the AGESA Heap. |
| 81 | * |
| 82 | * @param[in,out] IdsNvTable The Pointer of IDS NV Table. |
| 83 | * @param[in,out] StdHeader The Pointer of Standard Header. |
| 84 | * |
| 85 | * @retval AGESA_SUCCESS Success to get the pointer of NV Table. |
| 86 | * @retval AGESA_ERROR Fail to get the pointer of NV Table. |
| 87 | **/ |
| 88 | AGESA_STATUS |
| 89 | AmdGetIdsNvTable ( |
| 90 | IN OUT VOID **IdsNvTable, |
| 91 | IN OUT AMD_CONFIG_PARAMS *StdHeader |
| 92 | ) |
| 93 | { |
| 94 | AGESA_STATUS status; |
| 95 | LOCATE_HEAP_PTR LocateHeapStructPtr; |
| 96 | IDS_CONTROL_STRUCT *IdsCtrlPtr; |
| 97 | |
| 98 | LocateHeapStructPtr.BufferHandle = IDS_CONTROL_HANDLE; |
| 99 | LocateHeapStructPtr.BufferPtr = NULL; |
| 100 | status = HeapLocateBuffer (&LocateHeapStructPtr, StdHeader); |
| 101 | if (status == AGESA_SUCCESS) { |
| 102 | IdsCtrlPtr = (IDS_CONTROL_STRUCT *) LocateHeapStructPtr.BufferPtr; |
| 103 | *IdsNvTable = LocateHeapStructPtr.BufferPtr + IdsCtrlPtr->IdsNvTableOffset; |
| 104 | } |
| 105 | return status; |
| 106 | } |
| 107 | |
| 108 | /** |
| 109 | * |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 110 | * Read IDS NV value in NV table. |
| 111 | * |
| 112 | * It searches the table until the Nv Id is found and return the NV value |
| 113 | * in the table. Otherwise, return IDS_UNSUPPORTED. |
| 114 | * |
| 115 | * @param[in] IdsNvId IDS NV ID |
| 116 | * @param[in] NvTablePtr NV Table pointer. |
| 117 | * @param[in,out] StdHeader The Pointer of Standard Header. |
| 118 | * |
| 119 | * @retval IDS_UNSUPPORTED NV ID is not found in the table |
| 120 | * Other Value The NV value |
| 121 | * |
| 122 | **/ |
| 123 | IDS_STATUS |
| 124 | AmdIdsNvReader ( |
| 125 | IN UINT16 IdsNvId, |
| 126 | IN IDS_NV_ITEM *NvTablePtr, |
| 127 | IN OUT AMD_CONFIG_PARAMS *StdHeader |
| 128 | ) |
| 129 | { |
| 130 | IDS_STATUS Status; |
| 131 | IDS_NV_ITEM *NvPtr; |
| 132 | BOOLEAN IgnoreIdsDefault; |
| 133 | AGESA_STATUS status; |
| 134 | LOCATE_HEAP_PTR LocateHeapStructPtr; |
| 135 | IDS_CONTROL_STRUCT *IdsCtrlPtr; |
| 136 | |
| 137 | IgnoreIdsDefault = FALSE; |
| 138 | Status = IDS_UNSUPPORTED; |
| 139 | NvPtr = NvTablePtr; |
| 140 | |
| 141 | if (NvPtr != NULL) { |
| 142 | while (NvPtr->IdsNvId != AGESA_IDS_NV_END) { |
| 143 | if (NvPtr->IdsNvId == IdsNvId) { |
| 144 | break; |
| 145 | } else { |
| 146 | NvPtr ++; |
| 147 | } |
| 148 | } |
| 149 | if ((NvPtr->IdsNvId != AGESA_IDS_NV_END)) { |
| 150 | //Get IgnoreIdsDefault from heap |
| 151 | LocateHeapStructPtr.BufferHandle = IDS_CONTROL_HANDLE; |
| 152 | LocateHeapStructPtr.BufferPtr = NULL; |
| 153 | status = HeapLocateBuffer (&LocateHeapStructPtr, StdHeader); |
| 154 | if (status == AGESA_SUCCESS) { |
| 155 | IdsCtrlPtr = (IDS_CONTROL_STRUCT *) LocateHeapStructPtr.BufferPtr; |
| 156 | IgnoreIdsDefault = IdsCtrlPtr->IgnoreIdsDefault; |
| 157 | } |
| 158 | |
| 159 | if (IgnoreIdsDefault || (NvPtr->IdsNvValue != AGESA_IDS_DFT_VAL)) { |
| 160 | Status = NvPtr->IdsNvValue; |
| 161 | } |
| 162 | } |
| 163 | } |
| 164 | return Status; |
| 165 | } |
| 166 | |
| 167 | /** |
| 168 | * IDS function for only return IDS_SUCCESS |
| 169 | * |
| 170 | * |
| 171 | * @param[in,out] DataPtr meaningless data pointer |
| 172 | * @param[in,out] StdHeader The Pointer of AMD_CONFIG_PARAMS. |
| 173 | * @param[in] IdsNvPtr The Pointer of NV Table. |
| 174 | * |
| 175 | * @retval IDS_SUCCESS Always succeeds. |
| 176 | * |
| 177 | **/ |
| 178 | IDS_STATUS |
| 179 | IdsCommonReturn ( |
| 180 | IN OUT VOID *DataPtr, |
| 181 | IN OUT AMD_CONFIG_PARAMS *StdHeader, |
| 182 | IN IDS_NV_ITEM *IdsNvPtr |
| 183 | ) |
| 184 | { |
| 185 | return IDS_SUCCESS; |
| 186 | } |
| 187 | |
| 188 | |
| 189 | /** |
| 190 | * IDS function for ap run specific task after amdinitpost |
| 191 | * |
| 192 | * |
| 193 | * @param[in] ApicIdOfCore apic id of specific AP |
| 194 | * @param[in] ApLateTaskPtr The Pointer of IDSAPLATETASK. |
| 195 | * @param[in,out] StdHeader The Pointer of AMD_CONFIG_PARAMS. |
| 196 | * |
| 197 | * @retval AGESA_SUCCESS Success |
| 198 | * @retval AGESA_ERROR meet some error |
| 199 | * |
| 200 | **/ |
| 201 | AGESA_STATUS |
| 202 | IdsAgesaRunFcnOnApLate ( |
| 203 | IN UINTN ApicIdOfCore, |
| 204 | IN IDSAPLATETASK *ApLateTaskPtr, |
| 205 | IN OUT AMD_CONFIG_PARAMS *StdHeader |
| 206 | ) |
| 207 | { |
| 208 | AGESA_STATUS Status; |
| 209 | AP_EXE_PARAMS LaunchApParams; |
| 210 | |
| 211 | //init AgesaRunFcnOnAp parameters |
| 212 | LaunchApParams.FunctionNumber = IDS_LATE_RUN_AP_TASK_ID; |
| 213 | LaunchApParams.RelatedBlockLength = SIZE_IN_DWORDS (IDSAPLATETASK); |
| 214 | LaunchApParams.RelatedDataBlock = ApLateTaskPtr; |
| 215 | LaunchApParams.StdHeader = *StdHeader; |
| 216 | |
| 217 | AGESA_TESTPOINT (TpIfBeforeRunApFromIds, StdHeader); |
| 218 | Status = AgesaRunFcnOnAp ((UINTN) ApicIdOfCore, &LaunchApParams); |
| 219 | AGESA_TESTPOINT (TpIfAfterRunApFromIds, StdHeader); |
| 220 | |
| 221 | return Status; |
| 222 | } |
| 223 | |
| 224 | /** |
| 225 | * IDS function force all cores run specific task after amdinitpost |
| 226 | * |
| 227 | * |
| 228 | * @param[in] ApLateTaskPtr The Pointer of IDSAPLATETASK. |
| 229 | * @param[in,out] StdHeader The Pointer of AMD_CONFIG_PARAMS. |
| 230 | * |
| 231 | * @retval AGESA_SUCCESS Success |
| 232 | * @retval AGESA_ERROR meet some error |
| 233 | * |
| 234 | **/ |
| 235 | AGESA_STATUS |
| 236 | IdsAgesaRunFcnOnAllCoresLate ( |
| 237 | IN IDSAPLATETASK *ApLateTaskPtr, |
| 238 | IN OUT AMD_CONFIG_PARAMS *StdHeader |
| 239 | ) |
| 240 | { |
| 241 | AP_EXE_PARAMS LaunchApParams; |
| 242 | AGESA_STATUS Status; |
| 243 | |
| 244 | //init AgesaRunFcnOnAp parameters |
| 245 | Status = AGESA_SUCCESS; |
| 246 | LaunchApParams.FunctionNumber = IDS_LATE_RUN_AP_TASK_ID; |
| 247 | LaunchApParams.RelatedBlockLength = SIZE_IN_DWORDS (IDSAPLATETASK); |
| 248 | LaunchApParams.RelatedDataBlock = ApLateTaskPtr; |
| 249 | LaunchApParams.StdHeader = *StdHeader; |
| 250 | |
| 251 | Status = RunLateApTaskOnAllAPs (&LaunchApParams, StdHeader); |
| 252 | |
| 253 | //do it on Bsp |
| 254 | Status = ApLateTaskPtr->ApTask (ApLateTaskPtr->ApTaskPara, StdHeader); |
| 255 | return Status; |
| 256 | } |
| 257 | |
| 258 | /** |
| 259 | * IDS call-back function for ApDispatchTable |
| 260 | * |
| 261 | * @param[in] AmdApExeParams AP_EXE_PARAMS. |
| 262 | * |
| 263 | * @retval AGESA_SUCCESS Success |
| 264 | * @retval AGESA_ERROR meet some error |
| 265 | * |
| 266 | **/ |
| 267 | AGESA_STATUS |
| 268 | AmdIdsRunApTaskLate ( |
| 269 | IN AP_EXE_PARAMS *AmdApExeParams |
| 270 | ) |
| 271 | { |
| 272 | IDSAPLATETASK *ApLateTaskPtr; |
| 273 | AGESA_STATUS Status; |
| 274 | |
| 275 | ApLateTaskPtr = (IDSAPLATETASK *)AmdApExeParams->RelatedDataBlock; |
| 276 | Status = ApLateTaskPtr->ApTask (ApLateTaskPtr->ApTaskPara, &AmdApExeParams->StdHeader); |
| 277 | return Status; |
| 278 | } |
| 279 | |
| 280 | /** |
| 281 | * Get the number of P-State to support |
| 282 | * |
| 283 | * @param[in,out] StdHeader The Pointer of AMD_CONFIG_PARAMS. |
| 284 | * |
| 285 | * @retval num The number of P-State to support. |
| 286 | * |
| 287 | **/ |
| 288 | UINT8 |
| 289 | IdsGetNumPstatesFamCommon ( |
| 290 | IN OUT AMD_CONFIG_PARAMS *StdHeader |
| 291 | ) |
| 292 | { |
| 293 | UINT8 pstatesnum; |
| 294 | UINT8 i; |
| 295 | UINT8 IgnoredByte; |
| 296 | UINT32 Ignored; |
| 297 | BOOLEAN PStateEnabled; |
| 298 | UINT32 TempVar_c; |
| 299 | PSTATE_CPU_FAMILY_SERVICES *FamilyServices; |
| 300 | |
| 301 | pstatesnum = 0; |
| 302 | GetFeatureServicesOfCurrentCore (&PstateFamilyServiceTable, (CONST VOID **)&FamilyServices, StdHeader); |
| 303 | ASSERT (FamilyServices != NULL); |
| 304 | |
| 305 | FamilyServices->GetPstateMaxState (FamilyServices, &TempVar_c, &IgnoredByte, StdHeader); |
| 306 | for (i = 0; i <= TempVar_c; i++) { |
| 307 | // Check if PState is enabled |
| 308 | FamilyServices->GetPstateRegisterInfo ( FamilyServices, |
| 309 | (UINT32) i, |
| 310 | &PStateEnabled, |
| 311 | &Ignored, |
| 312 | &Ignored, |
| 313 | &Ignored, |
| 314 | StdHeader); |
| 315 | if (PStateEnabled) { |
| 316 | pstatesnum++; |
| 317 | } |
| 318 | } |
| 319 | return pstatesnum; |
| 320 | } |
| 321 | |
| 322 | /*---------------------------------------------------------------------------------------*/ |
| 323 | /** |
| 324 | * Runs the given task on all cores (including self) on the socket of the executing |
| 325 | * core 0. |
| 326 | * |
| 327 | * This function is used to invoke all APs on the socket of the executing core 0 to |
| 328 | * run a specified AGESA procedure. |
| 329 | * |
| 330 | * @param[in] TaskPtr Function descriptor |
| 331 | * @param[in] StdHeader Config handle for library and services |
| 332 | * |
| 333 | */ |
| 334 | VOID |
| 335 | IdsApRunCodeOnAllLocalCores ( |
| 336 | IN AP_TASK *TaskPtr, |
| 337 | IN OUT AMD_CONFIG_PARAMS *StdHeader |
| 338 | ) |
| 339 | { |
| 340 | UINT32 Core; |
| 341 | UINT32 BscCoreNum; |
| 342 | UINT32 Socket; |
| 343 | UINT32 BscSocket; |
| 344 | UINT32 IgnoredModule; |
| 345 | UINT32 NumberOfCores; |
| 346 | UINT32 NumberOfSockets; |
| 347 | AGESA_STATUS IgnoredSts; |
| 348 | |
| 349 | IdentifyCore (StdHeader, &BscSocket, &IgnoredModule, &BscCoreNum, &IgnoredSts); |
| 350 | NumberOfSockets = GetPlatformNumberOfSockets (); |
| 351 | |
| 352 | |
| 353 | for (Socket = 0; Socket < NumberOfSockets; Socket++) { |
| 354 | if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) { |
| 355 | for (Core = 0; Core < NumberOfCores; Core++) { |
| 356 | if ((Socket != (UINT32) BscSocket) || (Core != (UINT32) BscCoreNum)) { |
| 357 | ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) Core, TaskPtr, StdHeader); |
| 358 | } |
| 359 | } |
| 360 | } |
| 361 | } |
| 362 | // BSP codes |
| 363 | ApUtilTaskOnExecutingCore (TaskPtr, StdHeader, NULL); |
| 364 | } |
| 365 | |
| 366 | /** |
| 367 | * IdsMakePciRegEntry |
| 368 | * |
| 369 | * |
| 370 | * @param[in,out] TableEntry The Pointer of TableEntry |
| 371 | * @param[in] Family Family |
| 372 | * @param[in] Revision Revision |
| 373 | * @param[in] PciAddr PCI address |
| 374 | * @param[in] Data Or Mask |
| 375 | * @param[in] Mask And Mask |
| 376 | * |
| 377 | * |
| 378 | */ |
| 379 | VOID |
| 380 | IdsMakePciRegEntry ( |
| 381 | IN OUT TABLE_ENTRY_FIELDS **TableEntry, |
| 382 | IN UINT64 Family, |
| 383 | IN UINT64 Revision, |
| 384 | IN UINT32 PciAddr, |
| 385 | IN UINT32 Data, |
| 386 | IN UINT32 Mask |
| 387 | ) |
| 388 | { |
| 389 | (*TableEntry)->EntryType = PciRegister; |
| 390 | (*TableEntry)->CpuRevision.Family = Family; |
| 391 | (*TableEntry)->CpuRevision.Revision = Revision; |
| 392 | (*TableEntry)->Features.PlatformValue = AMD_PF_ALL; |
| 393 | (*TableEntry)->Entry.PciEntry.Address.AddressValue = PciAddr; |
| 394 | (*TableEntry)->Entry.PciEntry.Data = Data; |
| 395 | (*TableEntry)->Entry.PciEntry.Mask = Mask; |
| 396 | (*TableEntry)++; |
| 397 | } |
| 398 | |
| 399 | /** |
| 400 | * IdsMakeHtLinkPciRegEntry |
| 401 | * |
| 402 | * |
| 403 | * @param[in,out] TableEntry The Pointer of TableEntry |
| 404 | * @param[in] Family Family |
| 405 | * @param[in] Revision Revision |
| 406 | * @param[in] HtHostFeat HtHostFeat |
| 407 | * @param[in] PciAddr PCI address |
| 408 | * @param[in] Data Or Mask |
| 409 | * @param[in] Mask And Mask |
| 410 | * |
| 411 | * |
| 412 | */ |
| 413 | VOID |
| 414 | IdsMakeHtLinkPciRegEntry ( |
| 415 | IN OUT TABLE_ENTRY_FIELDS **TableEntry, |
| 416 | IN UINT64 Family, |
| 417 | IN UINT64 Revision, |
| 418 | IN UINT32 HtHostFeat, |
| 419 | IN UINT32 PciAddr, |
| 420 | IN UINT32 Data, |
| 421 | IN UINT32 Mask |
| 422 | ) |
| 423 | { |
| 424 | (*TableEntry)->EntryType = HtLinkPciRegister; |
| 425 | (*TableEntry)->CpuRevision.Family = Family; |
| 426 | (*TableEntry)->CpuRevision.Revision = Revision; |
| 427 | (*TableEntry)->Features.PlatformValue = AMD_PF_ALL; |
| 428 | (*TableEntry)->Entry.HtLinkPciEntry.LinkFeats.HtHostValue = HtHostFeat; |
| 429 | (*TableEntry)->Entry.HtLinkPciEntry.PciEntry.Address.AddressValue = PciAddr; |
| 430 | (*TableEntry)->Entry.HtLinkPciEntry.PciEntry.Data = Data; |
| 431 | (*TableEntry)->Entry.HtLinkPciEntry.PciEntry.Mask = Mask; |
| 432 | (*TableEntry)++; |
| 433 | } |
| 434 | /** |
| 435 | * IdsMakeHtFeatPciRegEntry |
| 436 | * |
| 437 | * |
| 438 | * @param[in,out] TableEntry The Pointer of TableEntry |
| 439 | * @param[in] Family Family |
| 440 | * @param[in] Revision Revision |
| 441 | * @param[in] HtHostFeat HtHostFeat |
| 442 | * @param[in] PackageType PackageType |
| 443 | * @param[in] PciAddr PCI address |
| 444 | * @param[in] Data Or Mask |
| 445 | * @param[in] Mask And Mask |
| 446 | * |
| 447 | * |
| 448 | */ |
| 449 | VOID |
| 450 | IdsMakeHtFeatPciRegEntry ( |
| 451 | IN OUT TABLE_ENTRY_FIELDS **TableEntry, |
| 452 | IN UINT64 Family, |
| 453 | IN UINT64 Revision, |
| 454 | IN UINT32 HtHostFeat, |
| 455 | IN UINT32 PackageType, |
| 456 | IN UINT32 PciAddr, |
| 457 | IN UINT32 Data, |
| 458 | IN UINT32 Mask |
| 459 | ) |
| 460 | { |
| 461 | (*TableEntry)->EntryType = HtFeatPciRegister; |
| 462 | (*TableEntry)->CpuRevision.Family = Family; |
| 463 | (*TableEntry)->CpuRevision.Revision = Revision; |
| 464 | (*TableEntry)->Features.PlatformValue = AMD_PF_ALL; |
| 465 | (*TableEntry)->Entry.HtFeatPciEntry.LinkFeats.HtHostValue = HtHostFeat; |
| 466 | (*TableEntry)->Entry.HtFeatPciEntry.PackageType.PackageTypeValue = PackageType; |
| 467 | (*TableEntry)->Entry.HtFeatPciEntry.PciEntry.Address.AddressValue = PciAddr; |
| 468 | (*TableEntry)->Entry.HtFeatPciEntry.PciEntry.Data = Data; |
| 469 | (*TableEntry)->Entry.HtFeatPciEntry.PciEntry.Mask = Mask; |
| 470 | (*TableEntry)++; |
| 471 | } |
| 472 | /** |
| 473 | * IdsMakeHostPciRegEntry |
| 474 | * |
| 475 | * |
| 476 | * @param[in,out] TableEntry The Pointer of TableEntry |
| 477 | * @param[in] Family Family |
| 478 | * @param[in] Revision Revision |
| 479 | * @param[in] HtHostFeat HtHostFeat |
| 480 | * @param[in] PciAddr PCI address |
| 481 | * @param[in] Data Or Mask |
| 482 | * @param[in] Mask And Mask |
| 483 | * |
| 484 | * |
| 485 | */ |
| 486 | VOID |
| 487 | IdsMakeHtHostPciRegEntry ( |
| 488 | IN OUT TABLE_ENTRY_FIELDS **TableEntry, |
| 489 | IN UINT64 Family, |
| 490 | IN UINT64 Revision, |
| 491 | IN UINT32 HtHostFeat, |
| 492 | IN UINT32 PciAddr, |
| 493 | IN UINT32 Data, |
| 494 | IN UINT32 Mask |
| 495 | ) |
| 496 | { |
| 497 | (*TableEntry)->EntryType = HtHostPciRegister; |
| 498 | (*TableEntry)->CpuRevision.Family = Family; |
| 499 | (*TableEntry)->CpuRevision.Revision = Revision; |
| 500 | (*TableEntry)->Features.PlatformValue = AMD_PF_ALL; |
| 501 | (*TableEntry)->Entry.HtHostEntry.TypeFeats.HtHostValue = HtHostFeat; |
| 502 | (*TableEntry)->Entry.HtHostEntry.Address.AddressValue = PciAddr; |
| 503 | (*TableEntry)->Entry.HtHostEntry.Data = Data; |
| 504 | (*TableEntry)->Entry.HtHostEntry.Mask = Mask; |
| 505 | (*TableEntry)++; |
| 506 | } |
| 507 | /** |
| 508 | * IdsMakeHtPhyRegEntry |
| 509 | * |
| 510 | * |
| 511 | * @param[in,out] TableEntry The Pointer of TableEntry |
| 512 | * @param[in] Family Family |
| 513 | * @param[in] Revision Revision |
| 514 | * @param[in] HtPhyLinkFeat HtPhyLinkFeat |
| 515 | * @param[in] Address PCI address |
| 516 | * @param[in] Data Or Mask |
| 517 | * @param[in] Mask And Mask |
| 518 | * |
| 519 | * |
| 520 | */ |
| 521 | VOID |
| 522 | IdsMakeHtPhyRegEntry ( |
| 523 | IN OUT TABLE_ENTRY_FIELDS **TableEntry, |
| 524 | IN UINT64 Family, |
| 525 | IN UINT64 Revision, |
| 526 | IN UINT32 HtPhyLinkFeat, |
| 527 | IN UINT32 Address, |
| 528 | IN UINT32 Data, |
| 529 | IN UINT32 Mask |
| 530 | ) |
| 531 | { |
| 532 | (*TableEntry)->EntryType = HtPhyRegister; |
| 533 | (*TableEntry)->CpuRevision.Family = Family; |
| 534 | (*TableEntry)->CpuRevision.Revision = Revision; |
| 535 | (*TableEntry)->Features.PlatformValue = AMD_PF_ALL; |
| 536 | (*TableEntry)->Entry.HtPhyEntry.TypeFeats.HtPhyLinkValue = HtPhyLinkFeat; |
| 537 | (*TableEntry)->Entry.HtPhyEntry.Address = Address; |
| 538 | (*TableEntry)->Entry.HtPhyEntry.Data = Data; |
| 539 | (*TableEntry)->Entry.HtPhyEntry.Mask = Mask; |
| 540 | (*TableEntry)++; |
| 541 | } |
| 542 | |
| 543 | /** |
| 544 | * IdsOptionCallout |
| 545 | * |
| 546 | * Description |
| 547 | * Call the host environment interface to provide a user hook opportunity. |
| 548 | * |
| 549 | * @param[in] CallOutId This parameter indicates the IDS Call-Out-function desired. |
| 550 | * @param[in,out] DataPtr The pointer for callout function use |
| 551 | * @param[in,out] StdHeader Config handle for library and services |
| 552 | * |
| 553 | * @retval AGESA_SUCCESS Success |
| 554 | * @retval AGESA_ERROR meet some error |
| 555 | * |
| 556 | */ |
| 557 | AGESA_STATUS |
| 558 | IdsOptionCallout ( |
| 559 | IN UINTN CallOutId, |
| 560 | IN OUT VOID *DataPtr, |
| 561 | IN OUT AMD_CONFIG_PARAMS *StdHeader |
| 562 | ) |
| 563 | { |
| 564 | IDS_CALLOUT_STRUCT IdsCalloutData; |
| 565 | IDS_NV_ITEM NullEntry; |
| 566 | |
| 567 | NullEntry.IdsNvId = 0xFFFF; |
| 568 | NullEntry.IdsNvValue = 0xFFFF; |
| 569 | IdsCalloutData.StdHeader = *StdHeader; |
| 570 | IdsCalloutData.IdsNvPtr = &NullEntry; |
| 571 | IdsCalloutData.Reserved = (UINTN) DataPtr; |
| 572 | |
| 573 | return AgesaGetIdsData (CallOutId, &IdsCalloutData); |
| 574 | |
| 575 | } |
| 576 | |
| 577 | /** |
| 578 | * Ids Write PCI register to All node |
| 579 | * |
| 580 | * |
| 581 | * @param[in] PciAddress Pci address |
| 582 | * @param[in] Highbit High bit position of the field in DWORD |
| 583 | * @param[in] Lowbit Low bit position of the field in DWORD |
| 584 | * @param[in] Value Pointer to input value |
| 585 | * @param[in] StdHeader Standard configuration header |
| 586 | * |
| 587 | */ |
| 588 | VOID |
| 589 | IdsLibPciWriteBitsToAllNode ( |
| 590 | IN PCI_ADDR PciAddress, |
| 591 | IN UINT8 Highbit, |
| 592 | IN UINT8 Lowbit, |
| 593 | IN UINT32 *Value, |
| 594 | IN OUT AMD_CONFIG_PARAMS *StdHeader |
| 595 | ) |
| 596 | { |
| 597 | UINT32 Socket; |
| 598 | UINT32 Module; |
| 599 | AGESA_STATUS IgnoreStatus; |
| 600 | PCI_ADDR PciAddr; |
| 601 | |
| 602 | |
| 603 | for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { |
| 604 | for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { |
| 605 | if (GetPciAddress (StdHeader, Socket, Module, &PciAddr, &IgnoreStatus)) { |
| 606 | PciAddr.Address.Function = PciAddress.Address.Function; |
| 607 | PciAddr.Address.Register = PciAddress.Address.Register; |
| 608 | LibAmdPciWriteBits (PciAddr, Highbit, Lowbit, Value, StdHeader); |
| 609 | } |
| 610 | } |
| 611 | } |
| 612 | } |
| 613 | |
| 614 | /** |
| 615 | * |
| 616 | * |
| 617 | * Core 0 task to run local ap task at early |
| 618 | * |
| 619 | * @param[in] PEarlyApTask - point to IDS_EARLY_AP_TASK structure |
| 620 | * @param[in,out] StdHeader - The Pointer of AGESA Header |
| 621 | * |
| 622 | */ |
| 623 | |
| 624 | STATIC VOID |
| 625 | IdsCmnTaskCore0Early ( |
| 626 | IN IDS_EARLY_AP_TASK *PEarlyApTask, |
| 627 | IN OUT AMD_CONFIG_PARAMS *StdHeader |
| 628 | ) |
| 629 | { |
| 630 | UINT32 Socket; |
| 631 | UINT32 IgnoredModule; |
| 632 | UINT32 IgnoredCore; |
| 633 | AGESA_STATUS IgnoredSts; |
| 634 | |
| 635 | ASSERT (PEarlyApTask->Ap_Task0.Core != 0); |
| 636 | |
| 637 | PEarlyApTask->Ap_Task0.ApTask.DataTransfer.DataPtr = &PEarlyApTask->Parameters[0]; |
| 638 | IdentifyCore (StdHeader, &Socket, &IgnoredModule, &IgnoredCore, &IgnoredSts); |
| 639 | ApUtilRunCodeOnSocketCore ((UINT8)Socket, PEarlyApTask->Ap_Task0.Core, &PEarlyApTask->Ap_Task0.ApTask, StdHeader); |
| 640 | } |
| 641 | |
| 642 | /** |
| 643 | * |
| 644 | * |
| 645 | * BSC task to run Core0 task at early, must only run on BSC |
| 646 | * |
| 647 | * @param[in] Socket - Socket which run the task |
| 648 | * @param[in] Core - Core which run the task |
| 649 | * @param[in] ApTask - Task for AP |
| 650 | * @param[in,out] StdHeader - The Pointer of AGESA Header |
| 651 | * |
| 652 | */ |
| 653 | VOID |
| 654 | IdsRunCodeOnCoreEarly ( |
| 655 | IN UINT8 Socket, |
| 656 | IN UINT8 Core, |
| 657 | IN AP_TASK* ApTask, |
| 658 | IN OUT AMD_CONFIG_PARAMS *StdHeader |
| 659 | ) |
| 660 | { |
| 661 | UINT32 BscSocket; |
| 662 | UINT32 BscCoreNum; |
| 663 | UINT32 IgnoredModule; |
| 664 | AGESA_STATUS IgnoredSts; |
| 665 | AP_TASK Core0Task; |
| 666 | IDS_EARLY_AP_TASK IdsEarlyTask; |
| 667 | |
| 668 | IdentifyCore (StdHeader, &BscSocket, &IgnoredModule, &BscCoreNum, &IgnoredSts); |
Martin Roth | 7d96565 | 2017-07-22 17:46:07 -0600 | [diff] [blame] | 669 | ASSERT (!((Socket == BscSocket) && (Core == BscCoreNum))); |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 670 | if ((Socket == BscSocket) || (Core == 0)) { |
| 671 | ApUtilRunCodeOnSocketCore (Socket, Core, ApTask, StdHeader); |
| 672 | } else { |
| 673 | //Init IDS_EARLY_AP_TASK for Core 0 |
| 674 | IdsEarlyTask.Ap_Task0.ApTask = *ApTask; |
| 675 | IdsEarlyTask.Ap_Task0.Core = Core; |
| 676 | //Init Parameter buffer, Target core can't get the parameter from pointer, which point to Host Core memory space |
| 677 | ASSERT ((ApTask->DataTransfer.DataSizeInDwords * sizeof (UINT32)) <= IDS_EARLY_AP_TASK_PARA_NUM); |
| 678 | LibAmdMemCopy (&IdsEarlyTask.Parameters[0], ApTask->DataTransfer.DataPtr, sizeof (UINT32) * ApTask->DataTransfer.DataSizeInDwords, StdHeader); |
| 679 | if ((ApTask->DataTransfer.DataSizeInDwords * sizeof (UINT32)) <= IDS_EARLY_AP_TASK_PARA_NUM) { |
| 680 | //Lauch Core0 1st |
| 681 | Core0Task.FuncAddress.PfApTaskI = (PF_AP_TASK_I)IdsCmnTaskCore0Early; |
| 682 | Core0Task.ExeFlags = WAIT_FOR_CORE; |
| 683 | Core0Task.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (IDS_EARLY_AP_TASK0) + ApTask->DataTransfer.DataSizeInDwords; |
| 684 | Core0Task.DataTransfer.DataPtr = &IdsEarlyTask; |
| 685 | Core0Task.DataTransfer.DataTransferFlags = 0; |
| 686 | ApUtilRunCodeOnSocketCore (Socket, 0, &Core0Task, StdHeader); |
| 687 | } |
| 688 | } |
| 689 | } |
| 690 | |
| 691 | /** |
| 692 | * |
| 693 | * |
| 694 | * This function get start end Module according to input ModuleId |
| 695 | * |
| 696 | * @param[in] ModuleId - 0xFF means all nodes, other value Specifies real NodeId |
| 697 | * @param[in,out] StartModule - Point to start Node |
| 698 | * @param[in,out] EndModule - Point to end Node |
| 699 | * |
| 700 | */ |
| 701 | VOID |
| 702 | IdsGetStartEndModule ( |
| 703 | IN UINT8 ModuleId, |
| 704 | IN OUT UINT8 *StartModule, |
| 705 | IN OUT UINT8 *EndModule |
| 706 | ) |
| 707 | { |
| 708 | if (ModuleId == 0xFF) { |
| 709 | *StartModule = 0; |
| 710 | *EndModule = (UINT8) (GetPlatformNumberOfSockets () * GetPlatformNumberOfModules () - 1); |
| 711 | if (*EndModule > 7) { |
| 712 | *EndModule = 7; |
| 713 | } |
| 714 | } else { |
| 715 | *StartModule = ModuleId; |
| 716 | *EndModule = ModuleId; |
| 717 | } |
| 718 | } |
| 719 | |
| 720 | /** |
| 721 | * |
| 722 | * |
| 723 | * This function get start end socket according to input SocketId |
| 724 | * |
| 725 | * @param[in] SocketId - 0xFF means all sockets, other value Specifies real SokcetId |
| 726 | * @param[in,out] StartSocket - Point to start Socket |
| 727 | * @param[in,out] EndSocket - Point to end Socket |
| 728 | * |
| 729 | */ |
| 730 | VOID |
| 731 | IdsGetStartEndSocket ( |
| 732 | IN UINT8 SocketId, |
| 733 | IN OUT UINT8 *StartSocket, |
| 734 | IN OUT UINT8 *EndSocket |
| 735 | ) |
| 736 | { |
| 737 | if (SocketId == 0xFF) { |
| 738 | *StartSocket = 0; |
| 739 | *EndSocket = (UINT8) (GetPlatformNumberOfSockets () - 1); |
| 740 | } else { |
| 741 | *StartSocket = SocketId; |
| 742 | *EndSocket = SocketId; |
| 743 | } |
| 744 | } |
| 745 | |
| 746 | /** |
| 747 | * |
| 748 | * |
| 749 | * This function transfer input High low bit to Mask |
| 750 | * |
| 751 | * @param[in] RegVal - Regval want to set |
| 752 | * @param[in] Highbit - (0~63) |
| 753 | * @param[in] Lowbit - (0~63) |
| 754 | * @param[in,out] AndMask - point value contain output AndMask |
| 755 | * @param[in,out] OrMask - point value contain output OrMask |
| 756 | * |
| 757 | */ |
| 758 | VOID |
| 759 | IdsGetMask64bits ( |
| 760 | IN UINT64 RegVal, |
| 761 | IN UINT8 Highbit, |
| 762 | IN UINT8 Lowbit, |
| 763 | IN OUT UINT64 *AndMask, |
| 764 | IN OUT UINT64 *OrMask |
| 765 | ) |
| 766 | { |
| 767 | UINT64 Mask; |
| 768 | |
| 769 | if ((Highbit - Lowbit) != 63) { |
| 770 | Mask = (((UINT64) 1 << (Highbit - Lowbit + 1)) - 1); |
| 771 | } else { |
| 772 | Mask = (UINT64) 0xFFFFFFFFFFFFFFFF; |
| 773 | } |
| 774 | *AndMask = ~(Mask << Lowbit); |
| 775 | *OrMask = (RegVal & Mask) << Lowbit; |
| 776 | } |
| 777 | /** |
| 778 | * |
| 779 | * |
| 780 | * This function transfer input High low bit to Mask |
| 781 | * |
| 782 | * @param[in] RegVal - Regval want to set |
| 783 | * @param[in] Highbit - (0~31) |
| 784 | * @param[in] Lowbit - (0~31) |
| 785 | * @param[in,out] AndMask - point value contain output AndMask |
| 786 | * @param[in,out] OrMask - point value contain output OrMask |
| 787 | * |
| 788 | */ |
| 789 | |
| 790 | VOID |
| 791 | IdsGetMask32bits ( |
| 792 | IN UINT32 RegVal, |
| 793 | IN UINT8 Highbit, |
| 794 | IN UINT8 Lowbit, |
| 795 | IN OUT UINT32 *AndMask, |
| 796 | IN OUT UINT32 *OrMask |
| 797 | ) |
| 798 | { |
| 799 | UINT32 Mask; |
| 800 | |
| 801 | if ((Highbit - Lowbit) != 31) { |
| 802 | Mask = (((UINT32) 1 << (Highbit - Lowbit + 1)) - 1); |
| 803 | } else { |
| 804 | Mask = (UINT32) 0xFFFFFFFF; |
| 805 | } |
| 806 | *AndMask = ~(Mask << Lowbit); |
| 807 | *OrMask = (RegVal & Mask) << Lowbit; |
| 808 | |
| 809 | } |
| 810 | /** |
| 811 | * |
| 812 | * |
| 813 | * This function transfer input High low bit to Mask |
| 814 | * |
| 815 | * @param[in] RegVal - Regval want to set |
| 816 | * @param[in] Highbit - (0~15) |
| 817 | * @param[in] Lowbit - (0~15) |
| 818 | * @param[in,out] AndMask - point value contain output AndMask |
| 819 | * @param[in,out] OrMask - point value contain output OrMask |
| 820 | * |
| 821 | */ |
| 822 | |
| 823 | VOID |
| 824 | IdsGetMask16bits ( |
| 825 | IN UINT16 RegVal, |
| 826 | IN UINT8 Highbit, |
| 827 | IN UINT8 Lowbit, |
| 828 | IN OUT UINT32 *AndMask, |
| 829 | IN OUT UINT32 *OrMask |
| 830 | ) |
| 831 | { |
| 832 | UINT16 Mask; |
| 833 | |
| 834 | if ((Highbit - Lowbit) != 15) { |
| 835 | Mask = (((UINT16) 1 << (Highbit - Lowbit + 1)) - 1); |
| 836 | } else { |
| 837 | Mask = (UINT16) 0xFFFF; |
| 838 | } |
| 839 | *AndMask = ~(Mask << Lowbit); |
| 840 | *OrMask = (RegVal & Mask) << Lowbit; |
| 841 | } |
| 842 | |
| 843 | /** |
| 844 | * |
| 845 | * |
| 846 | * IdsCheckPciExisit |
| 847 | * Use to check is the PCI device exisit of given address |
| 848 | * |
| 849 | * @param[in] PciAddr - Given PCI address |
| 850 | * @param[in,out] StdHeader - The Pointer of AGESA Header |
| 851 | * |
| 852 | * @retval TRUE The PCI device exisit |
| 853 | * @retval FALSE The PCI device doesn't exisit |
| 854 | * |
| 855 | * |
| 856 | */ |
| 857 | BOOLEAN |
| 858 | IdsCheckPciExisit ( |
| 859 | IN PCI_ADDR PciAddr, |
| 860 | IN OUT AMD_CONFIG_PARAMS *StdHeader |
| 861 | ) |
| 862 | { |
| 863 | PCI_ADDR _pciaddr; |
| 864 | UINT32 _pcidata; |
| 865 | BOOLEAN status; |
| 866 | |
| 867 | status = FALSE; |
| 868 | _pciaddr = PciAddr; |
| 869 | _pciaddr.Address.Register = 0; |
| 870 | LibAmdPciRead (AccessWidth32, _pciaddr, &_pcidata, StdHeader); |
Elyes HAOUAS | a360d9a | 2019-06-11 13:18:04 +0200 | [diff] [blame] | 871 | if (_pcidata != 0xFFFFFFFF && _pcidata != 0) { |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 872 | status = TRUE; |
| 873 | } |
| 874 | return status; |
| 875 | } |
| 876 | |
| 877 | /** |
| 878 | * |
| 879 | * |
| 880 | * This function transfer input High low bit to Mask |
| 881 | * |
| 882 | * @param[in,out] Value - Regval want to And Or with Mask |
| 883 | * @param[in] AndMask - AndMask |
| 884 | * @param[in] OrMask - OrMask |
| 885 | * |
| 886 | */ |
| 887 | |
| 888 | VOID |
| 889 | IdsLibDataMaskSet32 ( |
| 890 | IN OUT UINT32 *Value, |
| 891 | IN UINT32 AndMask, |
| 892 | IN UINT32 OrMask |
| 893 | ) |
| 894 | { |
| 895 | *Value &= AndMask; |
| 896 | *Value |= OrMask; |
| 897 | } |
| 898 | |
| 899 | |
| 900 | |
Kyösti Mälkki | 08311f5 | 2016-04-19 07:17:59 +0300 | [diff] [blame] | 901 | VOID |
| 902 | IdsOutPort ( |
| 903 | IN UINT32 Addr, |
| 904 | IN UINT32 Value, |
| 905 | IN UINT32 Flag |
| 906 | ) |
| 907 | { |
| 908 | __outdword ((UINT16) Addr, Value); |
| 909 | } |