zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * PCIe wrapper services |
| 6 | * |
| 7 | * |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: GNB |
| 12 | * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ |
| 13 | * |
| 14 | */ |
| 15 | /* |
| 16 | ***************************************************************************** |
| 17 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 18 | * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. |
| 19 | * All rights reserved. |
| 20 | * |
| 21 | * Redistribution and use in source and binary forms, with or without |
| 22 | * modification, are permitted provided that the following conditions are met: |
| 23 | * * Redistributions of source code must retain the above copyright |
| 24 | * notice, this list of conditions and the following disclaimer. |
| 25 | * * Redistributions in binary form must reproduce the above copyright |
| 26 | * notice, this list of conditions and the following disclaimer in the |
| 27 | * documentation and/or other materials provided with the distribution. |
| 28 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 29 | * its contributors may be used to endorse or promote products derived |
| 30 | * from this software without specific prior written permission. |
| 31 | * |
| 32 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 33 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 34 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 35 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 36 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 37 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 38 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 39 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 40 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 41 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 42 | * *************************************************************************** |
| 43 | * |
| 44 | */ |
| 45 | |
| 46 | /*---------------------------------------------------------------------------------------- |
| 47 | * M O D U L E S U S E D |
| 48 | *---------------------------------------------------------------------------------------- |
| 49 | */ |
| 50 | #include "AGESA.h" |
| 51 | #include "Ids.h" |
| 52 | #include "amdlib.h" |
| 53 | #include "Gnb.h" |
| 54 | #include "GnbPcie.h" |
| 55 | #include "GnbPcieFamServices.h" |
| 56 | #include "GnbCommonLib.h" |
| 57 | #include "GnbPcieConfig.h" |
| 58 | #include "GnbPcieInitLibV1.h" |
| 59 | #include "GnbNbInitLibV4.h" |
| 60 | #include "PcieWrapperServicesV4.h" |
| 61 | #include "GnbRegistersTN.h" |
| 62 | #include "Filecode.h" |
| 63 | #define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV4_PCIEWRAPPERSERVICESV4_FILECODE |
| 64 | /*---------------------------------------------------------------------------------------- |
| 65 | * D E F I N I T I O N S A N D M A C R O S |
| 66 | *---------------------------------------------------------------------------------------- |
| 67 | */ |
| 68 | |
| 69 | |
| 70 | /*---------------------------------------------------------------------------------------- |
| 71 | * T Y P E D E F S A N D S T R U C T U R E S |
| 72 | *---------------------------------------------------------------------------------------- |
| 73 | */ |
| 74 | |
| 75 | |
| 76 | /*---------------------------------------------------------------------------------------- |
| 77 | * P R O T O T Y P E S O F L O C A L F U N C T I O N S |
| 78 | *---------------------------------------------------------------------------------------- |
| 79 | */ |
| 80 | |
| 81 | |
| 82 | |
| 83 | /*----------------------------------------------------------------------------------------*/ |
| 84 | /** |
| 85 | * Relinquish control to DDI for specific lanes |
| 86 | * |
| 87 | * |
| 88 | * @param[in] Wrapper Pointer to wrapper configuration descriptor |
| 89 | * @param[in] Pcie Pointer to global PCIe configuration |
| 90 | */ |
| 91 | VOID |
| 92 | PcieSetDdiOwnPhyV4 ( |
| 93 | IN PCIe_WRAPPER_CONFIG *Wrapper, |
| 94 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 95 | ) |
| 96 | { |
| 97 | |
| 98 | UINT32 LaneBitmap; |
| 99 | UINT8 Slice; |
| 100 | if (PcieLibIsDdiWrapper (Wrapper)) { |
| 101 | IDS_HDT_CONSOLE (GNB_TRACE, "PcieSetDdiOwnPhyV4 Enter\n"); |
| 102 | LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_DDI_PHY_NATIVE, 0, Wrapper); |
| 103 | for (Slice = 0; Slice < 4; Slice++) { |
| 104 | if ((LaneBitmap & (1 << (Slice * 4))) != 0) { |
| 105 | PcieRegisterRMW ( |
| 106 | Wrapper, |
| 107 | WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8040_ADDRESS + Slice), |
| 108 | D0F0xE4_WRAP_8040_OwnSlice_MASK, |
| 109 | 1 << D0F0xE4_WRAP_8040_OwnSlice_OFFSET, |
| 110 | FALSE, |
| 111 | Pcie |
| 112 | ); |
| 113 | } |
| 114 | } |
| 115 | IDS_HDT_CONSOLE (GNB_TRACE, "PcieSetDdiOwnPhyV4 Exit\n"); |
| 116 | } |
| 117 | } |
| 118 | |
| 119 | /*----------------------------------------------------------------------------------------*/ |
| 120 | /** |
| 121 | * Execute/clean up reconfiguration |
| 122 | * |
| 123 | * |
| 124 | * @param[in] Wrapper Pointer to wrapper config descriptor |
| 125 | * @param[in] Pcie Pointer to global PCIe configuration |
| 126 | */ |
| 127 | VOID |
| 128 | PcieTopologyExecuteReconfigV4 ( |
| 129 | IN PCIe_WRAPPER_CONFIG *Wrapper, |
| 130 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 131 | ) |
| 132 | { |
| 133 | D0F0xE4_WRAP_8062_STRUCT D0F0xE4_WRAP_8062; |
| 134 | PCIe_SILICON_CONFIG *Silicon; |
| 135 | |
| 136 | if (PcieLibIsPcieWrapper (Wrapper)) { |
| 137 | IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyExecuteReconfigV4 Enter\n"); |
| 138 | |
| 139 | PcieTopologyInitSrbmReset (FALSE, Wrapper, Pcie); |
| 140 | |
| 141 | D0F0xE4_WRAP_8062.Value = PcieRegisterRead ( |
| 142 | Wrapper, |
| 143 | WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS), |
| 144 | Pcie |
| 145 | ); |
| 146 | D0F0xE4_WRAP_8062.Field.ReconfigureEn = 0x1; |
| 147 | PcieRegisterWrite ( |
| 148 | Wrapper, |
| 149 | WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS), |
| 150 | D0F0xE4_WRAP_8062.Value, |
| 151 | FALSE, |
| 152 | Pcie |
| 153 | ); |
| 154 | |
| 155 | Silicon = PcieConfigGetParentSilicon (Wrapper); |
| 156 | |
| 157 | GnbLibPciIndirectRMW ( |
| 158 | Silicon->Address.AddressValue | D0F0xB8_ADDRESS, |
| 159 | D0F0xBC_x1F630_ADDRESS, |
| 160 | AccessWidth32, |
| 161 | (UINT32) ~D0F0xBC_x1F630_RECONF_WRAPPER_MASK, |
| 162 | Wrapper->WrapId << D0F0xBC_x1F630_RECONF_WRAPPER_OFFSET, |
| 163 | GnbLibGetHeader (Pcie) |
| 164 | ); |
| 165 | |
| 166 | GnbSmuServiceRequestV4 ( |
| 167 | Silicon->Address, |
| 168 | SMC_MSG_RECONFIGURE, |
| 169 | 0, |
| 170 | GnbLibGetHeader (Pcie) |
| 171 | ); |
| 172 | |
| 173 | D0F0xE4_WRAP_8062.Field.ConfigXferMode = 0x1; |
| 174 | D0F0xE4_WRAP_8062.Field.ReconfigureEn = 0x0; |
| 175 | PcieRegisterWrite ( |
| 176 | Wrapper, |
| 177 | WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS), |
| 178 | D0F0xE4_WRAP_8062.Value, |
| 179 | FALSE, |
| 180 | Pcie |
| 181 | ); |
| 182 | PcieTopologyInitSrbmReset (TRUE, Wrapper, Pcie); |
| 183 | IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyExecuteReconfigV4 Exit\n"); |
| 184 | } |
| 185 | } |
| 186 | |
| 187 | /*----------------------------------------------------------------------------------------*/ |
| 188 | /** |
| 189 | * Set SSID |
| 190 | * |
| 191 | * |
| 192 | * @param[in] Ssid SSID |
| 193 | * @param[in] Wrapper Pointer to wrapper configuration descriptor |
| 194 | * @param[in] Pcie Pointer to global PCIe configuration |
| 195 | */ |
| 196 | VOID |
| 197 | PcieSetSsidV4 ( |
| 198 | IN UINT32 Ssid, |
| 199 | IN PCIe_WRAPPER_CONFIG *Wrapper, |
| 200 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 201 | ) |
| 202 | { |
| 203 | if (PcieLibIsPcieWrapper (Wrapper)) { |
| 204 | PcieRegisterWrite ( |
| 205 | Wrapper, |
| 206 | WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_0046_ADDRESS), |
| 207 | Ssid, |
| 208 | FALSE, |
| 209 | Pcie |
| 210 | ); |
| 211 | } |
| 212 | } |
| 213 | |
| 214 | /*----------------------------------------------------------------------------------------*/ |
| 215 | /** |
| 216 | * Enable lane reversal |
| 217 | * |
| 218 | * |
| 219 | * @param[in] Wrapper Pointer to wrapper config descriptor |
| 220 | * @param[in] Pcie Pointer to global PCIe configuration |
| 221 | */ |
| 222 | VOID |
| 223 | PcieTopologySetLinkReversalV4 ( |
| 224 | IN PCIe_WRAPPER_CONFIG *Wrapper, |
| 225 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 226 | ) |
| 227 | { |
| 228 | PCIe_ENGINE_CONFIG *EngineList; |
| 229 | IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySetLinkReversal Enter\n"); |
| 230 | EngineList = PcieConfigGetChildEngine (Wrapper); |
| 231 | while (EngineList != NULL) { |
| 232 | if (PcieLibIsEngineAllocated (EngineList)) { |
| 233 | if (PcieLibIsPcieEngine (EngineList)) { |
| 234 | if (EngineList->EngineData.StartLane > EngineList->EngineData.EndLane) { |
| 235 | PciePortRegisterWriteField ( |
| 236 | EngineList, |
| 237 | DxF0xE4_xC1_ADDRESS, |
| 238 | DxF0xE4_xC1_StrapReverseLanes_OFFSET, |
| 239 | DxF0xE4_xC1_StrapReverseLanes_WIDTH, |
| 240 | 0x1, |
| 241 | FALSE, |
| 242 | Pcie |
| 243 | ); |
| 244 | } |
| 245 | } |
| 246 | } |
| 247 | EngineList = PcieLibGetNextDescriptor (EngineList); |
| 248 | } |
| 249 | IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySetLinkReversal Exit\n"); |
| 250 | } |