zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * PCIe port initialization service procedure |
| 6 | * |
| 7 | * |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: GNB |
| 12 | * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ |
| 13 | * |
| 14 | */ |
| 15 | /* |
| 16 | ***************************************************************************** |
| 17 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 18 | * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. |
| 19 | * All rights reserved. |
| 20 | * |
| 21 | * Redistribution and use in source and binary forms, with or without |
| 22 | * modification, are permitted provided that the following conditions are met: |
| 23 | * * Redistributions of source code must retain the above copyright |
| 24 | * notice, this list of conditions and the following disclaimer. |
| 25 | * * Redistributions in binary form must reproduce the above copyright |
| 26 | * notice, this list of conditions and the following disclaimer in the |
| 27 | * documentation and/or other materials provided with the distribution. |
| 28 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 29 | * its contributors may be used to endorse or promote products derived |
| 30 | * from this software without specific prior written permission. |
| 31 | * |
| 32 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 33 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 34 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 35 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 36 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 37 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 38 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 39 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 40 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 41 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 42 | * *************************************************************************** |
| 43 | * |
| 44 | */ |
| 45 | |
| 46 | /*---------------------------------------------------------------------------------------- |
| 47 | * M O D U L E S U S E D |
| 48 | *---------------------------------------------------------------------------------------- |
| 49 | */ |
| 50 | #include "AGESA.h" |
| 51 | #include "Ids.h" |
| 52 | #include "amdlib.h" |
| 53 | #include "Gnb.h" |
| 54 | #include "GnbPcieConfig.h" |
| 55 | #include "GnbCommonLib.h" |
| 56 | #include "GnbPcieInitLibV1.h" |
| 57 | #include "PciePortServicesV4.h" |
| 58 | #include "GnbRegistersTN.h" |
| 59 | #include "Filecode.h" |
| 60 | #define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV4_PCIEPORTSERVICESV4_FILECODE |
| 61 | /*---------------------------------------------------------------------------------------- |
| 62 | * D E F I N I T I O N S A N D M A C R O S |
| 63 | *---------------------------------------------------------------------------------------- |
| 64 | */ |
| 65 | |
| 66 | |
| 67 | /*---------------------------------------------------------------------------------------- |
| 68 | * T Y P E D E F S A N D S T R U C T U R E S |
| 69 | *---------------------------------------------------------------------------------------- |
| 70 | */ |
| 71 | |
| 72 | |
| 73 | /*---------------------------------------------------------------------------------------- |
| 74 | * P R O T O T Y P E S O F L O C A L F U N C T I O N S |
| 75 | *---------------------------------------------------------------------------------------- |
| 76 | */ |
| 77 | |
| 78 | |
| 79 | /*----------------------------------------------------------------------------------------*/ |
| 80 | /** |
| 81 | * Set current link speed |
| 82 | * |
| 83 | * |
| 84 | * @param[in] LinkSpeedCapability Link Speed Capability |
| 85 | * @param[in] Engine Pointer to engine configuration descriptor |
| 86 | * @param[in] Pcie Pointer to global PCIe configuration |
| 87 | * |
| 88 | */ |
| 89 | VOID |
| 90 | PcieSetLinkSpeedCapV4 ( |
| 91 | IN PCIE_LINK_SPEED_CAP LinkSpeedCapability, |
| 92 | IN PCIe_ENGINE_CONFIG *Engine, |
| 93 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 94 | ) |
| 95 | { |
| 96 | DxF0xE4_xA4_STRUCT DxF0xE4_xA4; |
| 97 | DxF0xE4_xC0_STRUCT DxF0xE4_xC0; |
| 98 | DxF0x88_STRUCT DxF0x88; |
| 99 | GnbLibPciRead ( |
| 100 | Engine->Type.Port.Address.AddressValue | DxF0x88_ADDRESS, |
| 101 | AccessWidth32, |
| 102 | &DxF0x88.Value, |
| 103 | GnbLibGetHeader (Pcie) |
| 104 | ); |
| 105 | DxF0xE4_xA4.Value = PciePortRegisterRead ( |
| 106 | Engine, |
| 107 | DxF0xE4_xA4_ADDRESS, |
| 108 | Pcie |
| 109 | ); |
| 110 | DxF0xE4_xC0.Value = PciePortRegisterRead ( |
| 111 | Engine, |
| 112 | DxF0xE4_xC0_ADDRESS, |
| 113 | Pcie |
| 114 | ); |
| 115 | |
| 116 | switch (LinkSpeedCapability) { |
| 117 | case PcieGen2: |
| 118 | DxF0xE4_xA4.Field.LcGen2EnStrap = 0x1; |
| 119 | DxF0xE4_xA4.Field.LcMultUpstreamAutoSpdChngEn = 0x1; |
| 120 | DxF0xE4_xC0.Field.StrapAutoRcSpeedNegotiationDis = 0x0; |
| 121 | DxF0x88.Field.TargetLinkSpeed = 0x2; |
| 122 | DxF0x88.Field.HwAutonomousSpeedDisable = 0x0; |
| 123 | break; |
| 124 | case PcieGen1: |
| 125 | DxF0xE4_xA4.Field.LcGen2EnStrap = 0x0; |
| 126 | DxF0xE4_xA4.Field.LcMultUpstreamAutoSpdChngEn = 0x0; |
| 127 | DxF0xE4_xC0.Field.StrapAutoRcSpeedNegotiationDis = 0x1; |
| 128 | DxF0x88.Field.TargetLinkSpeed = 0x1; |
| 129 | DxF0x88.Field.HwAutonomousSpeedDisable = 0x1; |
| 130 | PcieRegisterWriteField ( |
| 131 | PcieConfigGetParentWrapper (Engine), |
| 132 | WRAP_SPACE (PcieConfigGetParentWrapper (Engine)->WrapId, D0F0xE4_WRAP_0803_ADDRESS + 0x100 * Engine->Type.Port.PortId), |
| 133 | D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_OFFSET, |
| 134 | D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_WIDTH, |
| 135 | 0, |
| 136 | FALSE, |
| 137 | Pcie |
| 138 | ); |
| 139 | break; |
| 140 | default: |
| 141 | ASSERT (FALSE); |
| 142 | break; |
| 143 | } |
| 144 | PciePortRegisterWrite ( |
| 145 | Engine, |
| 146 | DxF0xE4_xA4_ADDRESS, |
| 147 | DxF0xE4_xA4.Value, |
| 148 | FALSE, |
| 149 | Pcie |
| 150 | ); |
| 151 | PciePortRegisterWrite ( |
| 152 | Engine, |
| 153 | DxF0xE4_xC0_ADDRESS, |
| 154 | DxF0xE4_xC0.Value, |
| 155 | FALSE, |
| 156 | Pcie |
| 157 | ); |
| 158 | GnbLibPciWrite ( |
| 159 | Engine->Type.Port.Address.AddressValue | DxF0x88_ADDRESS, |
| 160 | AccessWidth32, |
| 161 | &DxF0x88.Value, |
| 162 | GnbLibGetHeader (Pcie) |
| 163 | ); |
| 164 | } |
| 165 | /*----------------------------------------------------------------------------------------*/ |
| 166 | /** |
| 167 | * Enable passing TLP prefix to IOMMU if IOMMU enabled |
| 168 | * |
| 169 | * |
| 170 | * @param[in] Engine Pointer to engine configuration descriptor |
| 171 | * @param[in] Pcie Pointer to global PCIe configuration |
| 172 | * |
| 173 | */ |
| 174 | VOID |
| 175 | PcieInitPortForIommuV4 ( |
| 176 | IN PCIe_ENGINE_CONFIG *Engine, |
| 177 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 178 | ) |
| 179 | { |
| 180 | PciePortRegisterRMW ( |
| 181 | Engine, |
| 182 | DxF0xE4_xC1_ADDRESS, |
| 183 | DxF0xE4_xC1_StrapE2EPrefixEn_MASK | DxF0xE4_xC1_StrapExtendedFmtSupported_MASK, |
| 184 | (1 << DxF0xE4_xC1_StrapE2EPrefixEn_OFFSET) | (1 << DxF0xE4_xC1_StrapExtendedFmtSupported_OFFSET), |
| 185 | TRUE, |
| 186 | Pcie |
| 187 | ); |
| 188 | } |