zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * Supporting services to access PCIe wrapper/core/PIF/PHY indirect register spaces |
| 6 | * |
| 7 | * |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: GNB |
| 12 | * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ |
| 13 | * |
| 14 | */ |
| 15 | /* |
| 16 | ***************************************************************************** |
| 17 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 18 | * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. |
| 19 | * All rights reserved. |
| 20 | * |
| 21 | * Redistribution and use in source and binary forms, with or without |
| 22 | * modification, are permitted provided that the following conditions are met: |
| 23 | * * Redistributions of source code must retain the above copyright |
| 24 | * notice, this list of conditions and the following disclaimer. |
| 25 | * * Redistributions in binary form must reproduce the above copyright |
| 26 | * notice, this list of conditions and the following disclaimer in the |
| 27 | * documentation and/or other materials provided with the distribution. |
| 28 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 29 | * its contributors may be used to endorse or promote products derived |
| 30 | * from this software without specific prior written permission. |
| 31 | * |
| 32 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 33 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 34 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 35 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 36 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 37 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 38 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 39 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 40 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 41 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 42 | * *************************************************************************** |
| 43 | * |
| 44 | */ |
| 45 | |
| 46 | #ifndef _PCIEWRAPPERREGACC_H_ |
| 47 | #define _PCIEWRAPPERREGACC_H_ |
| 48 | |
| 49 | //#define WRAP_SPACE(w, x) (0x01300000ul | (w << 16) | (x)) |
| 50 | //#define CORE_SPACE(c, x) (0x00010000ul | (c << 24) | (x)) |
| 51 | //#define PHY_SPACE(w, p, x) (0x00200000ul | ((p + 1) << 24) | (w << 16) | (x)) |
| 52 | //#define PIF_SPACE(w, p, x) (0x00100000ul | ((p + 1) << 24) | (w << 16) | (x)) |
| 53 | #define IMP_SPACE(x) (0x01080000ul | (x)) |
| 54 | |
| 55 | UINT32 |
| 56 | PcieRegisterRead ( |
| 57 | IN PCIe_WRAPPER_CONFIG *Wrapper, |
| 58 | IN UINT32 Address, |
| 59 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 60 | ); |
| 61 | |
| 62 | VOID |
| 63 | PcieRegisterWrite ( |
| 64 | IN PCIe_WRAPPER_CONFIG *Wrapper, |
| 65 | IN UINT32 Address, |
| 66 | IN UINT32 Value, |
| 67 | IN BOOLEAN S3Save, |
| 68 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 69 | ); |
| 70 | |
| 71 | UINT32 |
| 72 | PcieRegisterReadField ( |
| 73 | IN PCIe_WRAPPER_CONFIG *Wrapper, |
| 74 | IN UINT32 Address, |
| 75 | IN UINT8 FieldOffset, |
| 76 | IN UINT8 FieldWidth, |
| 77 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 78 | ); |
| 79 | |
| 80 | VOID |
| 81 | PcieRegisterWriteField ( |
| 82 | IN PCIe_WRAPPER_CONFIG *Wrapper, |
| 83 | IN UINT32 Address, |
| 84 | IN UINT8 FieldOffset, |
| 85 | IN UINT8 FieldWidth, |
| 86 | IN UINT32 Value, |
| 87 | IN BOOLEAN S3Save, |
| 88 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 89 | ); |
| 90 | |
| 91 | VOID |
| 92 | PcieRegisterRMW ( |
| 93 | IN PCIe_WRAPPER_CONFIG *Wrapper, |
| 94 | IN UINT32 Address, |
| 95 | IN UINT32 AndMask, |
| 96 | IN UINT32 OrMask, |
| 97 | IN BOOLEAN S3Save, |
| 98 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 99 | ); |
| 100 | |
| 101 | UINT32 |
| 102 | PcieSiliconRegisterRead ( |
| 103 | IN PCIe_SILICON_CONFIG *Silicon, |
| 104 | IN UINT32 Address, |
| 105 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 106 | ); |
| 107 | |
| 108 | VOID |
| 109 | PcieSiliconRegisterWrite ( |
| 110 | IN PCIe_SILICON_CONFIG *Silicon, |
| 111 | IN UINT32 Address, |
| 112 | IN UINT32 Value, |
| 113 | IN BOOLEAN S3Save, |
| 114 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 115 | ); |
| 116 | |
| 117 | VOID |
| 118 | PcieSiliconRegisterRMW ( |
| 119 | IN PCIe_SILICON_CONFIG *Silicon, |
| 120 | IN UINT32 Address, |
| 121 | IN UINT32 AndMask, |
| 122 | IN UINT32 OrMask, |
| 123 | IN BOOLEAN S3Save, |
| 124 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 125 | ); |
| 126 | |
| 127 | #endif |