zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * Supporting services to access PCIe wrapper/core/PIF/PHY indirect register spaces |
| 6 | * |
| 7 | * |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: GNB |
| 12 | * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ |
| 13 | * |
| 14 | */ |
| 15 | /* |
| 16 | ***************************************************************************** |
| 17 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 18 | * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. |
| 19 | * All rights reserved. |
| 20 | * |
| 21 | * Redistribution and use in source and binary forms, with or without |
| 22 | * modification, are permitted provided that the following conditions are met: |
| 23 | * * Redistributions of source code must retain the above copyright |
| 24 | * notice, this list of conditions and the following disclaimer. |
| 25 | * * Redistributions in binary form must reproduce the above copyright |
| 26 | * notice, this list of conditions and the following disclaimer in the |
| 27 | * documentation and/or other materials provided with the distribution. |
| 28 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 29 | * its contributors may be used to endorse or promote products derived |
| 30 | * from this software without specific prior written permission. |
| 31 | * |
| 32 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 33 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 34 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 35 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 36 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 37 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 38 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 39 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 40 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 41 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 42 | * *************************************************************************** |
| 43 | * |
| 44 | */ |
| 45 | |
| 46 | #include "AGESA.h" |
| 47 | #include "Ids.h" |
| 48 | #include "Gnb.h" |
| 49 | #include "GnbPcie.h" |
| 50 | #include "GnbPcieFamServices.h" |
| 51 | #include "GnbCommonLib.h" |
| 52 | #include "GnbPcieConfig.h" |
| 53 | #include "GnbPcieInitLibV1.h" |
| 54 | #include "Filecode.h" |
| 55 | #define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEWRAPPERREGACC_FILECODE |
| 56 | /*----------------------------------------------------------------------------------------*/ |
| 57 | /** |
| 58 | * Read PCIe register value. |
| 59 | * |
| 60 | * Support for unify register access through index/data pair on GNB |
| 61 | * |
| 62 | * @param[in] Wrapper Pointer to Wrapper descriptor |
| 63 | * @param[in] Address Register address |
| 64 | * @param[in] Pcie Pointer to global PCIe configuration |
| 65 | * @retval Register Value |
| 66 | */ |
| 67 | UINT32 |
| 68 | PcieRegisterRead ( |
| 69 | IN PCIe_WRAPPER_CONFIG *Wrapper, |
| 70 | IN UINT32 Address, |
| 71 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 72 | ) |
| 73 | { |
| 74 | if ((Wrapper->Features.AccessEncoding == 1) && ((Address & 0xff0000) == 0x010000)) { |
| 75 | Address = (Address & 0xffff) | 0x1400000 | ((Address >> 8) & 0xF0000); |
| 76 | } |
| 77 | return PcieSiliconRegisterRead (PcieConfigGetParentSilicon (Wrapper), Address, Pcie); |
| 78 | } |
| 79 | |
| 80 | /*----------------------------------------------------------------------------------------*/ |
| 81 | /** |
| 82 | * Read PCIe register value. |
| 83 | * |
| 84 | * Support for unify register access through index/data pair on GNB |
| 85 | * |
| 86 | * @param[in] Silicon Pointer to silicon descriptor |
| 87 | * @param[in] Address Register address |
| 88 | * @param[in] Pcie Pointer to global PCIe configuration |
| 89 | * @retval Register Value |
| 90 | */ |
| 91 | |
| 92 | UINT32 |
| 93 | PcieSiliconRegisterRead ( |
| 94 | IN PCIe_SILICON_CONFIG *Silicon, |
| 95 | IN UINT32 Address, |
| 96 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 97 | ) |
| 98 | { |
| 99 | UINT32 Value; |
| 100 | GnbLibPciWrite (Silicon->Address.AddressValue | 0xE0, AccessWidth32, &Address, GnbLibGetHeader (Pcie)); |
| 101 | GnbLibPciRead (Silicon->Address.AddressValue | 0xE4, AccessWidth32, &Value, GnbLibGetHeader (Pcie)); |
| 102 | return Value; |
| 103 | } |
| 104 | |
| 105 | /*----------------------------------------------------------------------------------------*/ |
| 106 | /** |
| 107 | * Write PCIe register value. |
| 108 | * |
| 109 | * Support for unify register access through index/data pair on GNB |
| 110 | * |
| 111 | * @param[in] Wrapper Pointer to wrapper descriptor |
| 112 | * @param[in] Address Register address |
| 113 | * @param[in] Value New register value |
| 114 | * @param[in] S3Save Save register for S3 (True/False) |
| 115 | * @param[in] Pcie Pointer to global PCIe configuration |
| 116 | */ |
| 117 | VOID |
| 118 | PcieRegisterWrite ( |
| 119 | IN PCIe_WRAPPER_CONFIG *Wrapper, |
| 120 | IN UINT32 Address, |
| 121 | IN UINT32 Value, |
| 122 | IN BOOLEAN S3Save, |
| 123 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 124 | ) |
| 125 | { |
| 126 | if ((Wrapper->Features.AccessEncoding == 1) && ((Address & 0xff0000) == 0x010000)) { |
| 127 | Address = (Address & 0xffff) | 0x1400000 | ((Address >> 8) & 0xF0000); |
| 128 | } |
| 129 | PcieSiliconRegisterWrite ( |
| 130 | PcieConfigGetParentSilicon (Wrapper), |
| 131 | Address, |
| 132 | Value, |
| 133 | S3Save, |
| 134 | Pcie |
| 135 | ); |
| 136 | } |
| 137 | |
| 138 | /*----------------------------------------------------------------------------------------*/ |
| 139 | /** |
| 140 | * Write PCIe register value. |
| 141 | * |
| 142 | * Support for unify register access through index/data pair on GNB |
| 143 | * |
| 144 | * @param[in] Silicon Pointer to silicon descriptor |
| 145 | * @param[in] Address Register address |
| 146 | * @param[in] Value New register value |
| 147 | * @param[in] S3Save Save register for S3 (True/False) |
| 148 | * @param[in] Pcie Pointer to global PCIe configuration |
| 149 | */ |
| 150 | VOID |
| 151 | PcieSiliconRegisterWrite ( |
| 152 | IN PCIe_SILICON_CONFIG *Silicon, |
| 153 | IN UINT32 Address, |
| 154 | IN UINT32 Value, |
| 155 | IN BOOLEAN S3Save, |
| 156 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 157 | ) |
| 158 | { |
| 159 | IDS_HDT_CONSOLE (PCIE_HOSTREG_TRACE, " *WR %s (%d:%d:%d):0x%08x = 0x%08x\n", |
| 160 | PcieFmDebugGetHostRegAddressSpaceString (Silicon, (UINT16) (Address >> 16)), |
| 161 | Silicon->Address.Address.Bus, |
| 162 | Silicon->Address.Address.Device, |
| 163 | Silicon->Address.Address.Function, |
| 164 | Address, |
| 165 | Value |
| 166 | ); |
| 167 | GnbLibPciWrite (Silicon->Address.AddressValue | 0xE0, S3Save ? AccessS3SaveWidth32 : AccessWidth32, &Address, GnbLibGetHeader (Pcie)); |
| 168 | GnbLibPciWrite (Silicon->Address.AddressValue | 0xE4, S3Save ? AccessS3SaveWidth32 : AccessWidth32, &Value, GnbLibGetHeader (Pcie)); |
| 169 | } |
| 170 | /*----------------------------------------------------------------------------------------*/ |
| 171 | /** |
| 172 | * Read PCIe register field. |
| 173 | * |
| 174 | * Support for unify register access through index/data pair on GNB |
| 175 | * |
| 176 | * @param[in] Wrapper Pointer to wrapper descriptor |
| 177 | * @param[in] Address Register address |
| 178 | * @param[in] FieldOffset Field offset |
| 179 | * @param[in] FieldWidth Field width |
| 180 | * @param[in] Pcie Pointer to global PCIe configuration |
| 181 | * @retval Register field value |
| 182 | */ |
| 183 | |
| 184 | UINT32 |
| 185 | PcieRegisterReadField ( |
| 186 | IN PCIe_WRAPPER_CONFIG *Wrapper, |
| 187 | IN UINT32 Address, |
| 188 | IN UINT8 FieldOffset, |
| 189 | IN UINT8 FieldWidth, |
| 190 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 191 | ) |
| 192 | { |
| 193 | UINT32 Value; |
| 194 | Value = PcieRegisterRead (Wrapper, Address, Pcie); |
| 195 | Value = (Value >> FieldOffset) & (~(0xFFFFFFFF << FieldWidth)); |
| 196 | return Value; |
| 197 | } |
| 198 | |
| 199 | /*----------------------------------------------------------------------------------------*/ |
| 200 | /** |
| 201 | * Write PCIe register field. |
| 202 | * |
| 203 | * Support for unify register access through index/data pair on GNB |
| 204 | * |
| 205 | * @param[in] Wrapper Pointer to wrapper descriptor |
| 206 | * @param[in] Address Register address |
| 207 | * @param[in] FieldOffset Field offset |
| 208 | * @param[in] FieldWidth Field width |
| 209 | * @param[in] Value Value to write |
| 210 | * @param[in] S3Save Save register for S3 (True/False) |
| 211 | * @param[in] Pcie Pointer to global PCIe configuration |
| 212 | */ |
| 213 | |
| 214 | |
| 215 | VOID |
| 216 | PcieRegisterWriteField ( |
| 217 | IN PCIe_WRAPPER_CONFIG *Wrapper, |
| 218 | IN UINT32 Address, |
| 219 | IN UINT8 FieldOffset, |
| 220 | IN UINT8 FieldWidth, |
| 221 | IN UINT32 Value, |
| 222 | IN BOOLEAN S3Save, |
| 223 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 224 | ) |
| 225 | { |
| 226 | UINT32 TempValue; |
| 227 | UINT32 Mask; |
| 228 | TempValue = PcieRegisterRead (Wrapper, Address, Pcie); |
| 229 | Mask = (~(0xFFFFFFFF << FieldWidth)); |
| 230 | Value &= Mask; |
| 231 | TempValue &= (~(Mask << FieldOffset)); |
| 232 | PcieRegisterWrite (Wrapper, Address, TempValue | (Value << FieldOffset), S3Save, Pcie); |
| 233 | } |
| 234 | |
| 235 | /*----------------------------------------------------------------------------------------*/ |
| 236 | /** |
| 237 | * Read/Modify/Write PCIe register. |
| 238 | * |
| 239 | * Support for unify register access through index/data pair on GNB |
| 240 | * |
| 241 | * @param[in] Wrapper Pointer to wrapper descriptor |
| 242 | * @param[in] Address Register address |
| 243 | * @param[in] AndMask Value & (~AndMask) |
| 244 | * @param[in] OrMask Value | OrMask |
| 245 | * @param[in] S3Save Save register for S3 (True/False) |
| 246 | * @param[in] Pcie Pointer to global PCIe configuration |
| 247 | */ |
| 248 | |
| 249 | VOID |
| 250 | PcieRegisterRMW ( |
| 251 | IN PCIe_WRAPPER_CONFIG *Wrapper, |
| 252 | IN UINT32 Address, |
| 253 | IN UINT32 AndMask, |
| 254 | IN UINT32 OrMask, |
| 255 | IN BOOLEAN S3Save, |
| 256 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 257 | ) |
| 258 | { |
| 259 | PcieSiliconRegisterRMW ( |
| 260 | PcieConfigGetParentSilicon (Wrapper), |
| 261 | Address, |
| 262 | AndMask, |
| 263 | OrMask, |
| 264 | S3Save, |
| 265 | Pcie |
| 266 | ); |
| 267 | } |
| 268 | |
| 269 | /*----------------------------------------------------------------------------------------*/ |
| 270 | /** |
| 271 | * Read/Modify/Write PCIe register. |
| 272 | * |
| 273 | * Support for unify register access through index/data pair on GNB |
| 274 | * |
| 275 | * @param[in] Silicon Pointer to silicon descriptor |
| 276 | * @param[in] Address Register address |
| 277 | * @param[in] AndMask Value & (~AndMask) |
| 278 | * @param[in] OrMask Value | OrMask |
| 279 | * @param[in] S3Save Save register for S3 (True/False) |
| 280 | * @param[in] Pcie Pointer to global PCIe configuration |
| 281 | */ |
| 282 | |
| 283 | VOID |
| 284 | PcieSiliconRegisterRMW ( |
| 285 | IN PCIe_SILICON_CONFIG *Silicon, |
| 286 | IN UINT32 Address, |
| 287 | IN UINT32 AndMask, |
| 288 | IN UINT32 OrMask, |
| 289 | IN BOOLEAN S3Save, |
| 290 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 291 | ) |
| 292 | { |
| 293 | UINT32 Value; |
| 294 | Value = PcieSiliconRegisterRead (Silicon, Address, Pcie); |
| 295 | Value = (Value & (~AndMask)) | OrMask; |
| 296 | PcieSiliconRegisterWrite (Silicon, Address, Value, S3Save, Pcie); |
| 297 | } |