zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * PCIe PIF initialization routine |
| 6 | * |
| 7 | * |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: GNB |
| 12 | * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ |
| 13 | * |
| 14 | */ |
| 15 | /* |
| 16 | ***************************************************************************** |
| 17 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 18 | * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. |
| 19 | * All rights reserved. |
| 20 | * |
| 21 | * Redistribution and use in source and binary forms, with or without |
| 22 | * modification, are permitted provided that the following conditions are met: |
| 23 | * * Redistributions of source code must retain the above copyright |
| 24 | * notice, this list of conditions and the following disclaimer. |
| 25 | * * Redistributions in binary form must reproduce the above copyright |
| 26 | * notice, this list of conditions and the following disclaimer in the |
| 27 | * documentation and/or other materials provided with the distribution. |
| 28 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 29 | * its contributors may be used to endorse or promote products derived |
| 30 | * from this software without specific prior written permission. |
| 31 | * |
| 32 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 33 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 34 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 35 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 36 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 37 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 38 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 39 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 40 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 41 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 42 | * *************************************************************************** |
| 43 | * |
| 44 | */ |
| 45 | /*---------------------------------------------------------------------------------------- |
| 46 | * M O D U L E S U S E D |
| 47 | *---------------------------------------------------------------------------------------- |
| 48 | */ |
| 49 | |
| 50 | #include "AGESA.h" |
| 51 | #include "Ids.h" |
| 52 | #include "amdlib.h" |
| 53 | #include "Gnb.h" |
| 54 | #include "GnbPcie.h" |
| 55 | #include "GnbCommonLib.h" |
| 56 | #include "GnbPcieConfig.h" |
| 57 | #include "GnbPcieInitLibV1.h" |
| 58 | #include "GnbRegistersLN.h" |
| 59 | #include "Filecode.h" |
| 60 | #define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPIFSERVICES_FILECODE |
| 61 | /*---------------------------------------------------------------------------------------- |
| 62 | * D E F I N I T I O N S A N D M A C R O S |
| 63 | *---------------------------------------------------------------------------------------- |
| 64 | */ |
| 65 | |
| 66 | #define PIF_GANG_0to1 0x1 |
| 67 | #define PIF_GANG_2to3 (0x1 << 1) |
| 68 | #define PIF_GANG_4to5 (0x1 << 2) |
| 69 | #define PIF_GANG_6to7 (0x1 << 3) |
| 70 | #define PIF_GANG_0to3 (0x1 << 4) |
| 71 | #define PIF_GANG_4to7 (0x1 << 8) |
| 72 | #define PIF_GANG_0to7 (0x1 << 9) |
| 73 | #define PIF_GANG_ALL (0x1 << 25) |
| 74 | |
| 75 | /*---------------------------------------------------------------------------------------- |
| 76 | * T Y P E D E F S A N D S T R U C T U R E S |
| 77 | *---------------------------------------------------------------------------------------- |
| 78 | */ |
| 79 | |
| 80 | /*---------------------------------------------------------------------------------------- |
| 81 | * P R O T O T Y P E S O F L O C A L F U N C T I O N S |
| 82 | *---------------------------------------------------------------------------------------- |
| 83 | */ |
| 84 | |
| 85 | |
| 86 | /*---------------------------------------------------------------------------------------- |
| 87 | * E X P O R T E D F U N C T I O N S |
| 88 | *---------------------------------------------------------------------------------------- |
| 89 | */ |
| 90 | |
| 91 | |
| 92 | /*----------------------------------------------------------------------------------------*/ |
| 93 | /** |
| 94 | * Apply PIF ganging for all lanes for given wrapper |
| 95 | * |
| 96 | * |
| 97 | * |
| 98 | * @param[in] Wrapper Pointer to Wrapper config descriptor |
| 99 | * @param[in] Pcie Pointer to PICe configuration data area |
| 100 | */ |
| 101 | |
| 102 | |
| 103 | VOID |
| 104 | PciePifApplyGanging ( |
| 105 | IN PCIe_WRAPPER_CONFIG *Wrapper, |
| 106 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 107 | ) |
| 108 | { |
| 109 | PCIe_ENGINE_CONFIG *EngineList; |
| 110 | UINT32 LaneBitmap; |
| 111 | UINT8 Pif; |
| 112 | D0F0xE4_PIF_0011_STRUCT D0F0xE4_PIF_0011[2]; |
| 113 | IDS_HDT_CONSOLE (GNB_TRACE, "PciePifApplyGanging Enter\n"); |
| 114 | LibAmdMemFill (&D0F0xE4_PIF_0011, 0, sizeof (D0F0xE4_PIF_0011), GnbLibGetHeader (Pcie)); |
| 115 | EngineList = PcieConfigGetChildEngine (Wrapper); |
| 116 | while (EngineList != NULL) { |
| 117 | if (PcieLibIsEngineAllocated (EngineList)) { |
| 118 | LaneBitmap = PcieUtilGetEngineLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE | LANE_TYPE_DDI_PHY_NATIVE, 0, EngineList); |
| 119 | switch (LaneBitmap) { |
| 120 | case 0x0003: |
| 121 | D0F0xE4_PIF_0011[0].Field.X2Lane10 = 0x1; |
| 122 | break; |
| 123 | case 0x000c: |
| 124 | D0F0xE4_PIF_0011[0].Field.X2Lane32 = 0x1; |
| 125 | break; |
| 126 | case 0x0030: |
| 127 | D0F0xE4_PIF_0011[0].Field.X2Lane54 = 0x1; |
| 128 | break; |
| 129 | case 0x00c0: |
| 130 | D0F0xE4_PIF_0011[0].Field.X2Lane76 = 0x1; |
| 131 | break; |
| 132 | case 0x000f: |
| 133 | D0F0xE4_PIF_0011[0].Field.X4Lane30 = 0x1; |
| 134 | break; |
| 135 | case 0x00f0: |
| 136 | D0F0xE4_PIF_0011[0].Field.X4Lane74 = 0x1; |
| 137 | break; |
| 138 | case 0x00ff: |
| 139 | D0F0xE4_PIF_0011[0].Field.X8Lane70 = 0x1; |
| 140 | break; |
| 141 | case 0x0300: |
| 142 | D0F0xE4_PIF_0011[1].Field.X2Lane10 = 1; |
| 143 | break; |
| 144 | case 0x0c00: |
| 145 | D0F0xE4_PIF_0011[1].Field.X2Lane32 = 0x1; |
| 146 | break; |
| 147 | case 0x3000: |
| 148 | D0F0xE4_PIF_0011[1].Field.X2Lane54 = 0x1; |
| 149 | break; |
| 150 | case 0xc000: |
| 151 | D0F0xE4_PIF_0011[1].Field.X2Lane76 = 0x1; |
| 152 | break; |
| 153 | case 0x0f00: |
| 154 | D0F0xE4_PIF_0011[1].Field.X4Lane30 = 0x1; |
| 155 | break; |
| 156 | case 0xf000: |
| 157 | D0F0xE4_PIF_0011[1].Field.X4Lane74 = 0x1; |
| 158 | break; |
| 159 | case 0xff00: |
| 160 | D0F0xE4_PIF_0011[1].Field.X8Lane70 = 0x1; |
| 161 | break; |
| 162 | case 0xffff: |
| 163 | D0F0xE4_PIF_0011[0].Field.MultiPif = 0x1; |
| 164 | D0F0xE4_PIF_0011[1].Field.MultiPif = 0x1; |
| 165 | break; |
| 166 | default: |
| 167 | break; |
| 168 | } |
| 169 | } |
| 170 | EngineList = PcieLibGetNextDescriptor (EngineList); |
| 171 | } |
| 172 | for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) { |
| 173 | PcieRegisterWrite ( |
| 174 | Wrapper, |
| 175 | PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0011_ADDRESS), |
| 176 | D0F0xE4_PIF_0011[Pif].Value, |
| 177 | FALSE, |
| 178 | Pcie |
| 179 | ); |
| 180 | } |
| 181 | IDS_HDT_CONSOLE (GNB_TRACE, "PciePifApplyGanging Exit\n"); |
| 182 | } |
| 183 | |
| 184 | |
| 185 | /*----------------------------------------------------------------------------------------*/ |
| 186 | /** |
| 187 | * PLL powerdown |
| 188 | * |
| 189 | * |
| 190 | * @param[in] LaneBitmap Power down PLL for these lanes |
| 191 | * @param[in] Wrapper Pointer to Wrapper config descriptor |
| 192 | * @param[in] Pcie Pointer to PICe configuration data area |
| 193 | */ |
| 194 | |
| 195 | VOID |
| 196 | PciePifPllPowerDown ( |
| 197 | IN UINT32 LaneBitmap, |
| 198 | IN PCIe_WRAPPER_CONFIG *Wrapper, |
| 199 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 200 | ) |
| 201 | { |
| 202 | UINT8 Nibble; |
| 203 | UINT16 NibbleBitmap; |
| 204 | D0F0xE4_PIF_0012_STRUCT D0F0xE4_PIF_0012; |
| 205 | IDS_HDT_CONSOLE (GNB_TRACE, "PciePifPllPowerDown Enter\n"); |
| 206 | for (Nibble = 0; Nibble < 4; Nibble++) { |
| 207 | NibbleBitmap = (0xF << (Nibble * 4)); |
| 208 | if ((LaneBitmap & NibbleBitmap) == NibbleBitmap) { |
| 209 | D0F0xE4_PIF_0012.Value = PcieRegisterRead ( |
| 210 | Wrapper, |
| 211 | PIF_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PIF_0012_ADDRESS + (Nibble & 0x1)), |
| 212 | Pcie |
| 213 | ); |
| 214 | |
| 215 | D0F0xE4_PIF_0012.Field.PllPowerStateInTxs2 = PifPowerStateOff; |
| 216 | D0F0xE4_PIF_0012.Field.PllPowerStateInOff = PifPowerStateOff; |
| 217 | D0F0xE4_PIF_0012.Field.TxPowerStateInTxs2 = PifPowerStateOff; |
| 218 | D0F0xE4_PIF_0012.Field.RxPowerStateInRxs2 = PifPowerStateOff; |
| 219 | PcieRegisterWrite ( |
| 220 | Wrapper, |
| 221 | PIF_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PIF_0012_ADDRESS + (Nibble & 0x1)), |
| 222 | D0F0xE4_PIF_0012.Value, |
| 223 | TRUE, |
| 224 | Pcie |
| 225 | ); |
| 226 | } |
| 227 | } |
| 228 | IDS_HDT_CONSOLE (GNB_TRACE, "PciePifPllPowerDown Exit\n"); |
| 229 | } |
| 230 | |
| 231 | /*----------------------------------------------------------------------------------------*/ |
| 232 | /** |
| 233 | * PLL init for DDI |
| 234 | * |
| 235 | * |
| 236 | * |
| 237 | * @param[in] Wrapper Pointer to Wrapper config descriptor |
| 238 | * @param[in] Pcie Pointer to PICe configuration data area |
| 239 | */ |
| 240 | |
| 241 | VOID |
| 242 | PciePifPllInitForDdi ( |
| 243 | IN PCIe_WRAPPER_CONFIG *Wrapper, |
| 244 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 245 | ) |
| 246 | { |
| 247 | UINT8 Nibble; |
| 248 | UINT32 LaneBitmap; |
| 249 | D0F0xE4_PIF_0012_STRUCT D0F0xE4_PIF_0012; |
| 250 | IDS_HDT_CONSOLE (GNB_TRACE, "PciePifPllInitForDdi Enter\n"); |
| 251 | LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_DDI_PHY_NATIVE, 0, Wrapper); |
| 252 | for (Nibble = 0; Nibble < 4; Nibble++) { |
| 253 | if (LaneBitmap & (0xF << (Nibble * 4))) { |
| 254 | D0F0xE4_PIF_0012.Value = PcieRegisterRead ( |
| 255 | Wrapper, |
| 256 | PIF_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PIF_0012_ADDRESS + (Nibble & 0x1)), |
| 257 | Pcie |
| 258 | ); |
| 259 | |
| 260 | D0F0xE4_PIF_0012.Field.PllPowerStateInTxs2 = PifPowerStateOff; |
| 261 | D0F0xE4_PIF_0012.Field.PllPowerStateInOff = PifPowerStateOff; |
| 262 | D0F0xE4_PIF_0012.Field.PllRampUpTime = 0x2; |
| 263 | PcieRegisterWrite ( |
| 264 | Wrapper, |
| 265 | PIF_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PIF_0012_ADDRESS + (Nibble & 0x1)), |
| 266 | D0F0xE4_PIF_0012.Value, |
| 267 | FALSE, |
| 268 | Pcie |
| 269 | ); |
| 270 | } |
| 271 | } |
| 272 | IDS_HDT_CONSOLE (GNB_TRACE, "PciePifPllInitForDdi Exit\n"); |
| 273 | } |
| 274 | |
| 275 | /*----------------------------------------------------------------------------------------*/ |
| 276 | /** |
| 277 | * Poll for on PIF to indicate action completion |
| 278 | * |
| 279 | * |
| 280 | * |
| 281 | * @param[in] Wrapper Pointer to wrapper config descriptor |
| 282 | * @param[in] Pcie Pointer to global PCIe configuration |
| 283 | */ |
| 284 | VOID |
| 285 | PciePollPifForCompeletion ( |
| 286 | IN PCIe_WRAPPER_CONFIG *Wrapper, |
| 287 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 288 | ) |
| 289 | { |
| 290 | //UINT32 TimeStamp; |
| 291 | UINT8 Pif; |
| 292 | D0F0xE4_PIF_0015_STRUCT D0F0xE4_PIF_0015; |
| 293 | //TimeStamp = PcieTimerGetTimeStamp (Pcie); |
| 294 | for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) { |
| 295 | do { |
| 296 | D0F0xE4_PIF_0015.Value = PcieRegisterRead ( |
| 297 | Wrapper, |
| 298 | PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0015_ADDRESS), |
| 299 | Pcie |
| 300 | ); |
| 301 | //if (TIMESTAMPS_DELTA (TimeStamp, PcieTimerGetTimeStamp (Pcie)) > 100) { |
| 302 | // break; |
| 303 | //} |
| 304 | } while ((D0F0xE4_PIF_0015.Value & 0xff) != 0xff); |
| 305 | } |
| 306 | } |
| 307 | |
| 308 | /*----------------------------------------------------------------------------------------*/ |
| 309 | /** |
| 310 | * Disable fifo reset |
| 311 | * |
| 312 | * |
| 313 | * |
| 314 | * @param[in] Wrapper Pointer to Wrapper config descriptor |
| 315 | * @param[in] Pcie Pointer to PICe configuration data area |
| 316 | */ |
| 317 | |
| 318 | |
| 319 | VOID |
| 320 | PciePifDisableFifoReset ( |
| 321 | IN PCIe_WRAPPER_CONFIG *Wrapper, |
| 322 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 323 | ) |
| 324 | { |
| 325 | UINT8 Pif; |
| 326 | for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) { |
| 327 | PcieRegisterWriteField ( |
| 328 | Wrapper, |
| 329 | PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS), |
| 330 | D0F0xE4_PIF_0010_RxDetectFifoResetMode_OFFSET, |
| 331 | D0F0xE4_PIF_0010_RxDetectFifoResetMode_WIDTH, |
| 332 | 0, |
| 333 | FALSE, |
| 334 | Pcie |
| 335 | ); |
| 336 | } |
| 337 | } |
| 338 | |
| 339 | /*----------------------------------------------------------------------------------------*/ |
| 340 | /** |
| 341 | * Program LS2 exit time |
| 342 | * |
| 343 | * |
| 344 | * |
| 345 | * @param[in] Wrapper Pointer to wrapper config descriptor |
| 346 | * @param[in] Pcie Pointer to global PCIe configuration |
| 347 | */ |
| 348 | |
| 349 | VOID |
| 350 | PciePifSetLs2ExitTime ( |
| 351 | IN PCIe_WRAPPER_CONFIG *Wrapper, |
| 352 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 353 | ) |
| 354 | { |
| 355 | UINT8 Pif; |
| 356 | IDS_HDT_CONSOLE (GNB_TRACE, "PciePifSetLs2ExitTime Enter\n"); |
| 357 | for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) { |
| 358 | PcieRegisterWriteField ( |
| 359 | Wrapper, |
| 360 | PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS), |
| 361 | D0F0xE4_PIF_0010_Ls2ExitTime_OFFSET, |
| 362 | D0F0xE4_PIF_0010_Ls2ExitTime_WIDTH, |
| 363 | 0x0, |
| 364 | FALSE, |
| 365 | Pcie |
| 366 | ); |
| 367 | } |
| 368 | IDS_HDT_CONSOLE (GNB_TRACE, "PciePifSetLs2ExitTime Exit\n"); |
| 369 | } |
| 370 | |
| 371 | /*----------------------------------------------------------------------------------------*/ |
| 372 | /** |
| 373 | * Set PLL mode for L1 |
| 374 | * |
| 375 | * |
| 376 | * @param[in] LaneBitmap Power down PLL for these lanes |
| 377 | * @param[in] Wrapper Pointer to Wrapper config descriptor |
| 378 | * @param[in] Pcie Pointer to PICe configuration data area |
| 379 | */ |
| 380 | |
| 381 | VOID |
| 382 | PciePifSetPllModeForL1 ( |
| 383 | IN UINT32 LaneBitmap, |
| 384 | IN PCIe_WRAPPER_CONFIG *Wrapper, |
| 385 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 386 | ) |
| 387 | { |
| 388 | UINT8 Nibble; |
| 389 | D0F0xE4_PIF_0012_STRUCT D0F0xE4_PIF_0012; |
| 390 | for (Nibble = 0; Nibble < 4; Nibble++) { |
| 391 | if (LaneBitmap & (0xF << (Nibble * 4))) { |
| 392 | D0F0xE4_PIF_0012.Value = PcieRegisterRead ( |
| 393 | Wrapper, |
| 394 | PIF_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PIF_0012_ADDRESS + (Nibble & 0x1)), |
| 395 | Pcie |
| 396 | ); |
| 397 | D0F0xE4_PIF_0012.Field.RxPowerStateInRxs2 = PifPowerStateLS2; |
| 398 | D0F0xE4_PIF_0012.Field.TxPowerStateInTxs2 = PifPowerStateLS2; |
| 399 | D0F0xE4_PIF_0012.Field.PllPowerStateInTxs2 = PifPowerStateOff; |
| 400 | D0F0xE4_PIF_0012.Field.PllPowerStateInOff = PifPowerStateOff; |
| 401 | D0F0xE4_PIF_0012.Field.PllRampUpTime = 0x1; |
| 402 | PcieRegisterWrite ( |
| 403 | Wrapper, |
| 404 | PIF_SPACE (Wrapper->WrapId, (Nibble >> 1), D0F0xE4_PIF_0012_ADDRESS + (Nibble & 0x1)), |
| 405 | D0F0xE4_PIF_0012.Value, |
| 406 | TRUE, |
| 407 | Pcie |
| 408 | ); |
| 409 | } |
| 410 | } |
| 411 | } |
| 412 | |
| 413 | /*----------------------------------------------------------------------------------------*/ |
| 414 | /** |
| 415 | * Program receiver detection power mode |
| 416 | * |
| 417 | * |
| 418 | * |
| 419 | * @param[in] Wrapper Pointer to wrapper config descriptor |
| 420 | * @param[in] Pcie Pointer to global PCIe configuration |
| 421 | */ |
| 422 | |
| 423 | VOID |
| 424 | PciePifSetRxDetectPowerMode ( |
| 425 | IN PCIe_WRAPPER_CONFIG *Wrapper, |
| 426 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 427 | ) |
| 428 | { |
| 429 | UINT8 Pif; |
| 430 | IDS_HDT_CONSOLE (GNB_TRACE, "PciePifSetRxDetectPowerMode Enter\n"); |
| 431 | for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) { |
| 432 | PcieRegisterWriteField ( |
| 433 | Wrapper, |
| 434 | PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS), |
| 435 | D0F0xE4_PIF_0010_RxDetectTxPwrMode_OFFSET, |
| 436 | D0F0xE4_PIF_0010_RxDetectTxPwrMode_WIDTH, |
| 437 | 0x1, |
| 438 | FALSE, |
| 439 | Pcie |
| 440 | ); |
| 441 | } |
| 442 | IDS_HDT_CONSOLE (GNB_TRACE, "PciePifSetRxDetectPowerMode Enter\n"); |
| 443 | } |
| 444 | |
| 445 | |
| 446 | /*----------------------------------------------------------------------------------------*/ |
| 447 | /** |
| 448 | * Pll ramp up time |
| 449 | * |
| 450 | * |
| 451 | * |
| 452 | * @param[in] Rampup Ramp up time |
| 453 | * @param[in] Wrapper Pointer to wrapper config descriptor |
| 454 | * @param[in] Pcie Pointer to global PCIe configuration |
| 455 | */ |
| 456 | VOID |
| 457 | PciePifSetPllRampTime ( |
| 458 | IN PCIE_PLL_RAMPUP_TIME Rampup, |
| 459 | IN PCIe_WRAPPER_CONFIG *Wrapper, |
| 460 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 461 | ) |
| 462 | { |
| 463 | UINT8 Pif; |
| 464 | D0F0xE4_PIF_0012_STRUCT D0F0xE4_PIF_0012; |
| 465 | D0F0xE4_PIF_0013_STRUCT D0F0xE4_PIF_0013; |
| 466 | D0F0xE4_PIF_0010_STRUCT D0F0xE4_PIF_0010; |
| 467 | IDS_HDT_CONSOLE (GNB_TRACE, "PciePifSetPllRampTime Enter\n"); |
| 468 | for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) { |
| 469 | D0F0xE4_PIF_0012.Value = PcieRegisterRead ( |
| 470 | Wrapper, |
| 471 | PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0012_ADDRESS), |
| 472 | Pcie |
| 473 | ); |
| 474 | D0F0xE4_PIF_0013.Value = PcieRegisterRead ( |
| 475 | Wrapper, |
| 476 | PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0013_ADDRESS), |
| 477 | Pcie |
| 478 | ); |
| 479 | D0F0xE4_PIF_0010.Value = PcieRegisterRead ( |
| 480 | Wrapper, |
| 481 | PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS), |
| 482 | Pcie |
| 483 | ); |
| 484 | if (Rampup == NormalRampup) { |
| 485 | D0F0xE4_PIF_0012.Field.PllRampUpTime = 0x1; |
| 486 | D0F0xE4_PIF_0013.Field.PllRampUpTime = 0x1; |
| 487 | D0F0xE4_PIF_0010.Field.Ls2ExitTime = 0x0; |
| 488 | } else { |
| 489 | D0F0xE4_PIF_0012.Field.PllRampUpTime = 0x3; |
| 490 | D0F0xE4_PIF_0013.Field.PllRampUpTime = 0x3; |
| 491 | D0F0xE4_PIF_0010.Field.Ls2ExitTime = 0x6; |
| 492 | } |
| 493 | PcieRegisterWrite ( |
| 494 | Wrapper, |
| 495 | PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0012_ADDRESS), |
| 496 | D0F0xE4_PIF_0012.Value, |
| 497 | FALSE, |
| 498 | Pcie |
| 499 | ); |
| 500 | PcieRegisterWrite ( |
| 501 | Wrapper, |
| 502 | PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0013_ADDRESS), |
| 503 | D0F0xE4_PIF_0013.Value, |
| 504 | FALSE, |
| 505 | Pcie |
| 506 | ); |
| 507 | PcieRegisterWrite ( |
| 508 | Wrapper, |
| 509 | PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0010_ADDRESS), |
| 510 | D0F0xE4_PIF_0010.Value, |
| 511 | FALSE, |
| 512 | Pcie |
| 513 | ); |
| 514 | } |
| 515 | IDS_HDT_CONSOLE (GNB_TRACE, "PciePifSetPllRampTime Exit\n"); |
| 516 | } |
| 517 | |
| 518 | |
| 519 | /*----------------------------------------------------------------------------------------*/ |
| 520 | /** |
| 521 | * Power down PIFs |
| 522 | * |
| 523 | * |
| 524 | * |
| 525 | * @param[in] Control Power up or Power down control |
| 526 | * @param[in] Wrapper Pointer to wrapper config descriptor |
| 527 | * @param[in] Pcie Pointer to global PCIe configuration |
| 528 | */ |
| 529 | VOID |
| 530 | PciePifPllPowerControl ( |
| 531 | IN PCIE_PIF_POWER_CONTROL Control, |
| 532 | IN PCIe_WRAPPER_CONFIG *Wrapper, |
| 533 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 534 | ) |
| 535 | { |
| 536 | UINT8 Pif; |
| 537 | UINT8 PllPowerStateInOff; |
| 538 | PllPowerStateInOff = (Control == PowerDownPifs) ? PifPowerStateOff : PifPowerStateL0; |
| 539 | for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) { |
| 540 | PcieRegisterWriteField ( |
| 541 | Wrapper, |
| 542 | PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0012_ADDRESS), |
| 543 | D0F0xE4_PIF_0012_PllPowerStateInOff_OFFSET, |
| 544 | D0F0xE4_PIF_0012_PllPowerStateInOff_WIDTH, |
| 545 | PllPowerStateInOff, |
| 546 | FALSE, |
| 547 | Pcie |
| 548 | ); |
| 549 | PcieRegisterWriteField ( |
| 550 | Wrapper, |
| 551 | PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0013_ADDRESS), |
| 552 | D0F0xE4_PIF_0013_PllPowerStateInOff_OFFSET, |
| 553 | D0F0xE4_PIF_0013_PllPowerStateInOff_WIDTH, |
| 554 | PllPowerStateInOff, |
| 555 | FALSE, |
| 556 | Pcie |
| 557 | ); |
| 558 | } |
| 559 | } |
| 560 | |
| 561 | |
| 562 | /*----------------------------------------------------------------------------------------*/ |
| 563 | /** |
| 564 | * Power down PIFs |
| 565 | * |
| 566 | * |
| 567 | * |
| 568 | * @param[in] Control Power up/Down control |
| 569 | * @param[in] Wrapper Pointer to wrapper config descriptor |
| 570 | * @param[in] Pcie Pointer to global PCIe configuration |
| 571 | */ |
| 572 | VOID |
| 573 | PciePifFullPowerStateControl ( |
| 574 | IN PCIE_PIF_POWER_CONTROL Control, |
| 575 | IN PCIe_WRAPPER_CONFIG *Wrapper, |
| 576 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 577 | ) |
| 578 | { |
| 579 | UINT8 Pif; |
| 580 | D0F0xE4_PIF_0012_STRUCT D0F0xE4_PIF_0012; |
| 581 | D0F0xE4_PIF_0013_STRUCT D0F0xE4_PIF_0013; |
| 582 | for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) { |
| 583 | D0F0xE4_PIF_0012.Value = PcieRegisterRead ( |
| 584 | Wrapper, |
| 585 | PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0012_ADDRESS), |
| 586 | Pcie |
| 587 | ); |
| 588 | D0F0xE4_PIF_0013.Value = PcieRegisterRead ( |
| 589 | Wrapper, |
| 590 | PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0013_ADDRESS), |
| 591 | Pcie |
| 592 | ); |
| 593 | if (Control == PowerDownPifs) { |
| 594 | D0F0xE4_PIF_0012.Field.PllPowerStateInOff = PifPowerStateOff; |
| 595 | D0F0xE4_PIF_0012.Field.PllPowerStateInTxs2 = PifPowerStateOff; |
| 596 | D0F0xE4_PIF_0012.Field.TxPowerStateInTxs2 = PifPowerStateOff; |
| 597 | D0F0xE4_PIF_0012.Field.RxPowerStateInRxs2 = PifPowerStateOff; |
| 598 | D0F0xE4_PIF_0013.Field.PllPowerStateInOff = PifPowerStateOff; |
| 599 | D0F0xE4_PIF_0013.Field.PllPowerStateInTxs2 = PifPowerStateOff; |
| 600 | D0F0xE4_PIF_0013.Field.TxPowerStateInTxs2 = PifPowerStateOff; |
| 601 | D0F0xE4_PIF_0013.Field.RxPowerStateInRxs2 = PifPowerStateOff; |
| 602 | } else { |
| 603 | D0F0xE4_PIF_0012.Field.PllPowerStateInOff = PifPowerStateLS2; |
| 604 | D0F0xE4_PIF_0012.Field.PllPowerStateInTxs2 = PifPowerStateLS2; |
| 605 | D0F0xE4_PIF_0012.Field.TxPowerStateInTxs2 = PifPowerStateL0; |
| 606 | D0F0xE4_PIF_0012.Field.RxPowerStateInRxs2 = PifPowerStateL0; |
| 607 | D0F0xE4_PIF_0013.Field.PllPowerStateInOff = PifPowerStateLS2; |
| 608 | D0F0xE4_PIF_0013.Field.PllPowerStateInTxs2 = PifPowerStateLS2; |
| 609 | D0F0xE4_PIF_0013.Field.TxPowerStateInTxs2 = PifPowerStateL0; |
| 610 | D0F0xE4_PIF_0013.Field.RxPowerStateInRxs2 = PifPowerStateL0; |
| 611 | } |
| 612 | PcieRegisterWrite ( |
| 613 | Wrapper, |
| 614 | PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0012_ADDRESS), |
| 615 | D0F0xE4_PIF_0012.Value, |
| 616 | FALSE, |
| 617 | Pcie |
| 618 | ); |
| 619 | PcieRegisterWrite ( |
| 620 | Wrapper, |
| 621 | PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0013_ADDRESS), |
| 622 | D0F0xE4_PIF_0013.Value, |
| 623 | FALSE, |
| 624 | Pcie |
| 625 | ); |
| 626 | } |
| 627 | } |