zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * Service procedure to calculate PCIe topology segment maximum exit latency |
| 6 | * |
| 7 | * |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: GNB |
| 12 | * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ |
| 13 | * |
| 14 | */ |
| 15 | /* |
| 16 | ***************************************************************************** |
| 17 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 18 | * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. |
| 19 | * All rights reserved. |
| 20 | * |
| 21 | * Redistribution and use in source and binary forms, with or without |
| 22 | * modification, are permitted provided that the following conditions are met: |
| 23 | * * Redistributions of source code must retain the above copyright |
| 24 | * notice, this list of conditions and the following disclaimer. |
| 25 | * * Redistributions in binary form must reproduce the above copyright |
| 26 | * notice, this list of conditions and the following disclaimer in the |
| 27 | * documentation and/or other materials provided with the distribution. |
| 28 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 29 | * its contributors may be used to endorse or promote products derived |
| 30 | * from this software without specific prior written permission. |
| 31 | * |
| 32 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 33 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 34 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 35 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 36 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 37 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 38 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 39 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 40 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 41 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 42 | * *************************************************************************** |
| 43 | * |
| 44 | */ |
| 45 | |
| 46 | /*---------------------------------------------------------------------------------------- |
| 47 | * M O D U L E S U S E D |
| 48 | *---------------------------------------------------------------------------------------- |
| 49 | */ |
| 50 | #include "AGESA.h" |
| 51 | #include "Ids.h" |
| 52 | #include "Gnb.h" |
| 53 | #include "GnbPcie.h" |
| 54 | #include "GnbCommonLib.h" |
| 55 | #include "GnbPcieInitLibV1.h" |
| 56 | #include "Filecode.h" |
| 57 | #define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPMEXITLATENCY_FILECODE |
| 58 | /*---------------------------------------------------------------------------------------- |
| 59 | * D E F I N I T I O N S A N D M A C R O S |
| 60 | *---------------------------------------------------------------------------------------- |
| 61 | */ |
| 62 | |
| 63 | |
| 64 | /*---------------------------------------------------------------------------------------- |
| 65 | * T Y P E D E F S A N D S T R U C T U R E S |
| 66 | *---------------------------------------------------------------------------------------- |
| 67 | */ |
| 68 | |
| 69 | typedef struct { |
| 70 | GNB_PCI_SCAN_DATA ScanData; |
| 71 | PCIe_ASPM_LATENCY_INFO *AspmLatencyInfo; |
| 72 | PCI_ADDR DownstreamPort; |
| 73 | UINT8 LinkCount; |
| 74 | } PCIE_EXIT_LATENCY_DATA; |
| 75 | |
| 76 | /*---------------------------------------------------------------------------------------- |
| 77 | * P R O T O T Y P E S O F L O C A L F U N C T I O N S |
| 78 | *---------------------------------------------------------------------------------------- |
| 79 | */ |
| 80 | |
| 81 | SCAN_STATUS |
| 82 | PcieAspmGetMaxExitLatencyCallback ( |
| 83 | IN PCI_ADDR Device, |
| 84 | IN OUT GNB_PCI_SCAN_DATA *ScanData |
| 85 | ); |
| 86 | |
| 87 | /*----------------------------------------------------------------------------------------*/ |
| 88 | /** |
| 89 | * Determine ASPM L-state maximum exit latency for PCIe segment |
| 90 | * |
| 91 | * Scan through all link in segment to determine maxim exit latency requirement by EPs. |
| 92 | * |
| 93 | * @param[in] DownstreamPort PCI address of PCIe port |
| 94 | * @param[out] AspmLatencyInfo Latency info |
| 95 | * @param[in] StdHeader Standard configuration header |
| 96 | * |
| 97 | */ |
| 98 | |
| 99 | VOID |
| 100 | PcieAspmGetMaxExitLatency ( |
| 101 | IN PCI_ADDR DownstreamPort, |
| 102 | OUT PCIe_ASPM_LATENCY_INFO *AspmLatencyInfo, |
| 103 | IN AMD_CONFIG_PARAMS *StdHeader |
| 104 | ) |
| 105 | { |
| 106 | PCIE_EXIT_LATENCY_DATA PcieExitLatencyData; |
| 107 | PcieExitLatencyData.AspmLatencyInfo = AspmLatencyInfo; |
| 108 | PcieExitLatencyData.ScanData.StdHeader = StdHeader; |
| 109 | PcieExitLatencyData.LinkCount = 0; |
| 110 | PcieExitLatencyData.ScanData.GnbScanCallback = PcieAspmGetMaxExitLatencyCallback; |
| 111 | GnbLibPciScan (DownstreamPort, DownstreamPort, &PcieExitLatencyData.ScanData); |
| 112 | } |
| 113 | |
| 114 | /*----------------------------------------------------------------------------------------*/ |
| 115 | /** |
| 116 | * Evaluate device |
| 117 | * |
| 118 | * |
| 119 | * |
| 120 | * @param[in] Device PCI Address |
| 121 | * @param[in,out] ScanData Scan configuration data |
| 122 | * @retval Scan Status of 0 |
| 123 | */ |
| 124 | |
| 125 | SCAN_STATUS |
| 126 | PcieAspmGetMaxExitLatencyCallback ( |
| 127 | IN PCI_ADDR Device, |
| 128 | IN OUT GNB_PCI_SCAN_DATA *ScanData |
| 129 | ) |
| 130 | { |
| 131 | SCAN_STATUS ScanStatus; |
| 132 | PCIE_EXIT_LATENCY_DATA *PcieExitLatencyData; |
| 133 | PCIE_DEVICE_TYPE DeviceType; |
| 134 | UINT32 Value; |
| 135 | UINT8 PcieCapPtr; |
| 136 | UINT8 L1AcceptableLatency; |
| 137 | |
| 138 | PcieExitLatencyData = (PCIE_EXIT_LATENCY_DATA*) ScanData; |
| 139 | ScanStatus = SCAN_SUCCESS; |
| 140 | DeviceType = GnbLibGetPcieDeviceType (Device, ScanData->StdHeader); |
| 141 | IDS_HDT_CONSOLE (GNB_TRACE, " PcieAspmGetMaxExitLatencyCallback for Device = %d:%d:%d\n", |
| 142 | Device.Address.Bus, |
| 143 | Device.Address.Device, |
| 144 | Device.Address.Function |
| 145 | ); |
| 146 | switch (DeviceType) { |
| 147 | case PcieDeviceRootComplex: |
| 148 | case PcieDeviceDownstreamPort: |
| 149 | PcieExitLatencyData->DownstreamPort = Device; |
| 150 | PcieExitLatencyData->LinkCount++; |
| 151 | GnbLibPciScanSecondaryBus (Device, &PcieExitLatencyData->ScanData); |
| 152 | PcieExitLatencyData->LinkCount--; |
| 153 | break; |
| 154 | case PcieDeviceUpstreamPort: |
| 155 | GnbLibPciScanSecondaryBus (Device, &PcieExitLatencyData->ScanData); |
| 156 | break; |
| 157 | case PcieDeviceEndPoint: |
| 158 | case PcieDeviceLegacyEndPoint: |
| 159 | PcieCapPtr = GnbLibFindPciCapability (Device.AddressValue, PCIE_CAP_ID, ScanData->StdHeader); |
| 160 | ASSERT (PcieCapPtr != 0); |
| 161 | GnbLibPciRead ( |
| 162 | Device.AddressValue | (PcieCapPtr + PCIE_LINK_CAP_REGISTER), |
| 163 | AccessWidth32, |
| 164 | &Value, |
| 165 | ScanData->StdHeader |
| 166 | ); |
| 167 | if ((Value & PCIE_ASPM_L1_SUPPORT_CAP) != 0) { |
| 168 | GnbLibPciRead ( |
| 169 | Device.AddressValue | (PcieCapPtr + PCIE_DEVICE_CAP_REGISTER), |
| 170 | AccessWidth32, |
| 171 | &Value, |
| 172 | ScanData->StdHeader |
| 173 | ); |
| 174 | L1AcceptableLatency = (UINT8) (1 << ((Value >> 9) & 0x7)); |
| 175 | if (PcieExitLatencyData->LinkCount > 1) { |
| 176 | L1AcceptableLatency = L1AcceptableLatency + PcieExitLatencyData->LinkCount; |
| 177 | } |
| 178 | if (PcieExitLatencyData->AspmLatencyInfo->MaxL1ExitLatency < L1AcceptableLatency) { |
| 179 | PcieExitLatencyData->AspmLatencyInfo->MaxL1ExitLatency = L1AcceptableLatency; |
| 180 | } |
| 181 | IDS_HDT_CONSOLE (PCIE_MISC, " Device max exit latency L1 - %d us\n", |
| 182 | L1AcceptableLatency |
| 183 | ); |
| 184 | } |
| 185 | break; |
| 186 | default: |
| 187 | break; |
| 188 | } |
| 189 | return SCAN_SUCCESS; |
| 190 | } |
| 191 | |