zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 1 | /** |
| 2 | * @file |
| 3 | * |
| 4 | * ALIB ASL library |
| 5 | * |
| 6 | * |
| 7 | * |
| 8 | * @xrefitem bom "File Content Label" "Release Content" |
| 9 | * @e project: AGESA |
| 10 | * @e sub-project: GNB |
| 11 | * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 01:16:51 -0800 (Wed, 22 Dec 2010) $ |
| 12 | * |
| 13 | */ |
| 14 | /* |
| 15 | ***************************************************************************** |
| 16 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 17 | * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. |
| 18 | * All rights reserved. |
| 19 | * |
| 20 | * Redistribution and use in source and binary forms, with or without |
| 21 | * modification, are permitted provided that the following conditions are met: |
| 22 | * * Redistributions of source code must retain the above copyright |
| 23 | * notice, this list of conditions and the following disclaimer. |
| 24 | * * Redistributions in binary form must reproduce the above copyright |
| 25 | * notice, this list of conditions and the following disclaimer in the |
| 26 | * documentation and/or other materials provided with the distribution. |
| 27 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 28 | * its contributors may be used to endorse or promote products derived |
| 29 | * from this software without specific prior written permission. |
| 30 | * |
| 31 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 32 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 33 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 34 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 35 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 36 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 37 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 38 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 39 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 40 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 41 | * *************************************************************************** |
| 42 | * |
| 43 | */ |
| 44 | |
| 45 | |
| 46 | /*----------------------------------------------------------------------------------------*/ |
| 47 | /** |
| 48 | * Read PCI config register through MMIO |
| 49 | * |
| 50 | * Arg0 - PCI address Bus/device/func |
| 51 | * Arg1 - Register offset |
| 52 | */ |
| 53 | Method (procPciDwordRead, 2, Serialized) { |
| 54 | Add (varPcieBase, ShiftLeft (Arg0, 12), Local0) |
| 55 | Add (Arg1, Local0, Local0) |
| 56 | OperationRegion(varOperationRegionMmio, SystemMemory, Local0, 0x4) |
| 57 | Field(varOperationRegionMmio, DWordAcc, NoLock, Preserve) { |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 58 | varPciReg32, 32, |
| 59 | } |
| 60 | return (varPciReg32) |
| 61 | } |
| 62 | /*----------------------------------------------------------------------------------------*/ |
| 63 | /** |
| 64 | * Write PCI config register through MMIO |
| 65 | * |
| 66 | * Arg0 - PCI address Bus/device/func |
| 67 | * Arg1 - Register offset |
| 68 | * Arg2 - Value |
| 69 | */ |
| 70 | Method (procPciDwordWrite, 3, Serialized) { |
| 71 | Add (varPcieBase, ShiftLeft (Arg0, 12), Local0) |
| 72 | Add (Arg1, Local0, Local0) |
| 73 | OperationRegion(varOperationRegionMmio, SystemMemory, Local0, 0x4) |
| 74 | Field(varOperationRegionMmio, DWordAcc, NoLock, Preserve) { |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 75 | varPciReg32, 32, |
| 76 | } |
| 77 | Store (Arg2, varPciReg32) |
| 78 | } |
| 79 | /*----------------------------------------------------------------------------------------*/ |
| 80 | /** |
| 81 | * Write PCI config register through MMIO |
| 82 | * |
| 83 | * Arg0 - PCI address Bus/device/func |
| 84 | * Arg1 - Register offset |
| 85 | * Arg2 - AND mask |
| 86 | * Arg3 - OR mask |
| 87 | */ |
| 88 | Method (procPciDwordRMW, 4, Serialized) { |
| 89 | Store (procPciDwordRead (Arg0, Arg1), Local0) |
| 90 | Or (And (Local0, Arg2), Arg3, Local0) |
| 91 | procPciDwordWrite (Arg0, Arg1, Local0) |
| 92 | } |
| 93 | |
| 94 | Mutex(varPciePortAccessMutex, 0) |
| 95 | /*----------------------------------------------------------------------------------------*/ |
| 96 | /** |
| 97 | * Read PCIe port indirect register |
| 98 | * |
| 99 | * Arg0 - Port Index |
| 100 | * Arg1 - Register offset |
| 101 | * |
| 102 | */ |
| 103 | Method (procPciePortIndirectRegisterRead, 2, NotSerialized) { |
| 104 | Acquire(varPciePortAccessMutex, 0xFFFF) |
| 105 | Store (ShiftLeft (Add( Arg0, 2), 3), Local0) |
| 106 | procPciDwordWrite (Local0, 0xe0, Arg1) |
| 107 | Store (procPciDwordRead (Local0, 0xe4), Local0) |
| 108 | Release (varPciePortAccessMutex) |
| 109 | return (Local0) |
| 110 | } |
| 111 | |
| 112 | /*----------------------------------------------------------------------------------------*/ |
| 113 | /** |
| 114 | * Write PCIe port indirect register |
| 115 | * |
| 116 | * Arg0 - Port Index |
| 117 | * Arg1 - Register offset |
| 118 | * Arg2 - Value |
| 119 | */ |
| 120 | Method (procPciePortIndirectRegisterWrite, 3, NotSerialized) { |
| 121 | Acquire(varPciePortAccessMutex, 0xFFFF) |
| 122 | Store (ShiftLeft (Add( Arg0, 2), 3), Local0) |
| 123 | procPciDwordWrite (Local0, 0xe0, Arg1) |
| 124 | procPciDwordWrite (Local0, 0xe4, Arg2) |
| 125 | Release (varPciePortAccessMutex) |
| 126 | } |
| 127 | /*----------------------------------------------------------------------------------------*/ |
| 128 | /** |
| 129 | * Read PCIe port indirect register |
| 130 | * |
| 131 | * Arg0 - Port Index |
| 132 | * Arg1 - Register offset |
| 133 | * Arg2 - AND Mask |
| 134 | * Arg3 - OR Mask |
| 135 | * |
| 136 | */ |
| 137 | Method (procPciePortIndirectRegisterRMW, 4, NotSerialized) { |
| 138 | Store (procPciePortIndirectRegisterRead (Arg0, Arg1), Local0) |
| 139 | Or (And (Local0, Arg2), Arg3, Local0) |
| 140 | procPciePortIndirectRegisterWrite (Arg0, Arg1, Local0) |
| 141 | } |
| 142 | Mutex(varHostAccessMutex, 0) |
| 143 | /*----------------------------------------------------------------------------------------*/ |
| 144 | /** |
| 145 | * Read PCIe port indirect register |
| 146 | * |
| 147 | * Arg0 - BDF |
| 148 | * Arg1 - Register offset |
| 149 | * Arg2 - Register address |
| 150 | * |
| 151 | */ |
| 152 | Method (procIndirectRegisterRead, 3, NotSerialized) { |
| 153 | Acquire(varHostAccessMutex, 0xFFFF) |
| 154 | procPciDwordWrite (Arg0, Arg1, Arg2) |
| 155 | Store (procPciDwordRead (Arg0, Add (Arg1, 4)), Local0) |
| 156 | Release(varHostAccessMutex) |
| 157 | return (Local0) |
| 158 | } |
| 159 | |
| 160 | /*----------------------------------------------------------------------------------------*/ |
| 161 | /** |
| 162 | * Write PCIe port indirect register |
| 163 | * |
| 164 | * Arg0 - BDF |
| 165 | * Arg1 - Register offset |
| 166 | * Arg2 - Register address |
| 167 | * Arg3 - Value |
| 168 | */ |
| 169 | Method (procIndirectRegisterWrite, 4, NotSerialized) { |
| 170 | Acquire(varHostAccessMutex, 0xFFFF) |
| 171 | procPciDwordWrite (Arg0, Arg1, Arg2) |
| 172 | procPciDwordWrite (Arg0, Add (Arg1, 4), Arg3) |
| 173 | Release(varHostAccessMutex) |
| 174 | } |
| 175 | |
| 176 | /*----------------------------------------------------------------------------------------*/ |
| 177 | /** |
| 178 | * Read Modify Write indirect registers |
| 179 | * |
| 180 | * Arg0 - BDF |
| 181 | * Arg1 - Register Offset |
| 182 | * Arg2 - Register Address |
| 183 | * Arg3 - AND Mask |
| 184 | * Arg4 - OR Mask |
| 185 | * |
| 186 | */ |
| 187 | Method (procIndirectRegisterRMW, 5, NotSerialized) { |
| 188 | Store (procIndirectRegisterRead (Arg0, Arg1, Arg2), Local0) |
| 189 | Or (And (Local0, Arg3), Arg4, Local0) |
| 190 | procIndirectRegisterWrite (Arg0, Arg1, Arg2, Local0) |
| 191 | } |
| 192 | |
| 193 | /*----------------------------------------------------------------------------------------*/ |
| 194 | /** |
| 195 | * Find Pci Capability |
| 196 | * |
| 197 | * Arg0 - PCI address Bus/device/func |
| 198 | * Arg1 - Capability id |
| 199 | */ |
| 200 | Method (procFindPciCapability, 2, NotSerialized) { |
| 201 | Store (0x34, Local1) |
| 202 | if (LEqual (procPciDwordRead (Arg0, 0x0), 0xFFFFFFFF)) { |
| 203 | // Device not present |
| 204 | return (0) |
| 205 | } |
| 206 | Store (1, Local0) |
| 207 | while (LEqual (Local0, 1)) { |
| 208 | Store (And (procPciDwordRead (Arg0, Local1), 0xFF), Local1) |
| 209 | if (LEqual (Local1, 0)) { |
| 210 | break |
| 211 | } |
| 212 | if (LEqual (And (procPciDwordRead (Arg0, Local1), 0xFF), Arg1)) { |
| 213 | Store (0, Local0) |
| 214 | } else { |
| 215 | Increment (Local1) |
| 216 | } |
| 217 | } |
| 218 | return (Local1) |
| 219 | } |
| 220 | |
| 221 | /*----------------------------------------------------------------------------------------*/ |
| 222 | /** |
| 223 | * |
| 224 | * |
| 225 | * Arg0 - Aspm |
| 226 | * Arg1 - 0: Read, 1: Write |
| 227 | */ |
| 228 | Method (procPcieSbAspmControl, 2, Serialized) { |
| 229 | // Create an opregion for PM IO Registers |
| 230 | OperationRegion (PMIO, SystemIO, 0xCD6, 0x2) |
| 231 | Field (PMIO, ByteAcc, NoLock, Preserve) |
| 232 | { |
| 233 | PMRI, 8, |
| 234 | PMRD, 8 |
| 235 | } |
| 236 | IndexField (PMRI, PMRD, ByteAcc, NoLock, Preserve) |
| 237 | { |
| 238 | Offset(0xE0), // IO Base address of A-Link Express/ A-Link Bridge register |
| 239 | ABAR, 32, |
| 240 | } |
| 241 | OperationRegion (ACFG, SystemIO, ABAR, 0x8) |
| 242 | Field (ACFG, DWordAcc, Nolock, Preserve) //AB_INDX/AB_DATA |
| 243 | { |
| 244 | ABIX, 32, |
| 245 | ABDA, 32 |
| 246 | } |
| 247 | |
| 248 | Store (0, Local0) |
| 249 | if (LEqual (Arg1, 0)) { |
| 250 | Store (0x80000068, ABIX) |
| 251 | Store (ABDA, Local0) |
| 252 | return (Local0) |
| 253 | } else { |
| 254 | Store (0x80000068, ABIX) |
| 255 | Store (ABDA, Local0) |
| 256 | Or (And (Local0, 0xfffffffc), Arg0, Local0) |
| 257 | Store (Local0, ABDA) |
| 258 | } |
| 259 | } |
| 260 | |