zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * PCIe late post initialization. |
| 6 | * |
| 7 | * |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: GNB |
| 12 | * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ |
| 13 | * |
| 14 | */ |
| 15 | /* |
| 16 | ***************************************************************************** |
| 17 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 18 | * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. |
| 19 | * All rights reserved. |
| 20 | * |
| 21 | * Redistribution and use in source and binary forms, with or without |
| 22 | * modification, are permitted provided that the following conditions are met: |
| 23 | * * Redistributions of source code must retain the above copyright |
| 24 | * notice, this list of conditions and the following disclaimer. |
| 25 | * * Redistributions in binary form must reproduce the above copyright |
| 26 | * notice, this list of conditions and the following disclaimer in the |
| 27 | * documentation and/or other materials provided with the distribution. |
| 28 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 29 | * its contributors may be used to endorse or promote products derived |
| 30 | * from this software without specific prior written permission. |
| 31 | * |
| 32 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 33 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 34 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 35 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 36 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 37 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 38 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 39 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 40 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 41 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 42 | * *************************************************************************** |
| 43 | * |
| 44 | */ |
| 45 | /*---------------------------------------------------------------------------------------- |
| 46 | * M O D U L E S U S E D |
| 47 | *---------------------------------------------------------------------------------------- |
| 48 | */ |
| 49 | #include "AGESA.h" |
| 50 | #include "amdlib.h" |
| 51 | #include "Ids.h" |
| 52 | #include "Gnb.h" |
| 53 | #include "GnbPcie.h" |
| 54 | #include "GnbPcieConfig.h" |
| 55 | #include "GnbPcieInitLibV1.h" |
| 56 | #include "GnbPcieInitLibV4.h" |
| 57 | #include "GnbFamServices.h" |
| 58 | #include "PcieLibTN.h" |
| 59 | #include "PciePowerGateTN.h" |
| 60 | #include "PciePortServicesV4.h" |
| 61 | #include "PcieMaxPayloadV4.h" |
| 62 | #include "OptionGnb.h" |
| 63 | #include "Filecode.h" |
| 64 | #define FILECODE PROC_GNB_MODULES_GNBINITTN_PCIEMIDINITTN_FILECODE |
| 65 | /*---------------------------------------------------------------------------------------- |
| 66 | * D E F I N I T I O N S A N D M A C R O S |
| 67 | *---------------------------------------------------------------------------------------- |
| 68 | */ |
| 69 | |
| 70 | extern GNB_BUILD_OPTIONS GnbBuildOptions; |
| 71 | extern CONST PCIE_PORT_REGISTER_TABLE_HEADER ROMDATA PortInitMidTableTN; |
| 72 | |
| 73 | /*---------------------------------------------------------------------------------------- |
| 74 | * T Y P E D E F S A N D S T R U C T U R E S |
| 75 | *---------------------------------------------------------------------------------------- |
| 76 | */ |
| 77 | |
| 78 | |
| 79 | /*---------------------------------------------------------------------------------------- |
| 80 | * P R O T O T Y P E S O F L O C A L F U N C T I O N S |
| 81 | *---------------------------------------------------------------------------------------- |
| 82 | */ |
| 83 | AGESA_STATUS |
| 84 | PcieMidInterfaceTN ( |
| 85 | IN AMD_CONFIG_PARAMS *StdHeader |
| 86 | ); |
| 87 | |
| 88 | |
| 89 | |
| 90 | /*----------------------------------------------------------------------------------------*/ |
| 91 | /** |
| 92 | * Callback to init various features on all active ports |
| 93 | * |
| 94 | * |
| 95 | * |
| 96 | * |
| 97 | * @param[in] Engine Pointer to engine config descriptor |
| 98 | * @param[in, out] Buffer Not used |
| 99 | * @param[in] Pcie Pointer to global PCIe configuration |
| 100 | * |
| 101 | */ |
| 102 | |
| 103 | VOID |
| 104 | STATIC |
| 105 | PcieMidPortInitCallbackTN ( |
| 106 | IN PCIe_ENGINE_CONFIG *Engine, |
| 107 | IN OUT VOID *Buffer, |
| 108 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 109 | ) |
| 110 | { |
| 111 | PciePortProgramRegisterTable (PortInitMidTableTN.Table, PortInitMidTableTN.Length, Engine, TRUE, Pcie); |
| 112 | if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS) || Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled) { |
| 113 | PcieEnableSlotPowerLimit (Engine, Pcie); |
| 114 | if (GnbFmCheckIommuPresent ((GNB_HANDLE*) PcieConfigGetParentSilicon (Engine), GnbLibGetHeader (Pcie))) { |
| 115 | PcieInitPortForIommuV4 (Engine, Pcie); |
| 116 | } |
| 117 | } |
| 118 | PcieEnableAspm (Engine, Pcie); |
| 119 | if (GnbBuildOptions.CfgMaxPayloadEnable) { |
| 120 | PcieSetMaxPayload (Engine->Type.Port.Address, GnbLibGetHeader (Pcie)); |
| 121 | } |
| 122 | } |
| 123 | |
| 124 | /*----------------------------------------------------------------------------------------*/ |
| 125 | /** |
| 126 | * Master procedure to init various features on all active ports |
| 127 | * |
| 128 | * |
| 129 | * |
| 130 | * |
| 131 | * @param[in] Pcie Pointer to global PCIe configuration |
| 132 | * @retval AGESA_STATUS |
| 133 | * |
| 134 | */ |
| 135 | |
| 136 | AGESA_STATUS |
| 137 | STATIC |
| 138 | PcieMidPortInitTN ( |
| 139 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 140 | ) |
| 141 | { |
| 142 | AGESA_STATUS Status; |
| 143 | PCIE_LINK_SPEED_CAP GlobalSpeedCap; |
| 144 | |
| 145 | Status = AGESA_SUCCESS; |
| 146 | PcieConfigRunProcForAllEngines ( |
| 147 | DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, |
| 148 | PcieMidPortInitCallbackTN, |
| 149 | NULL, |
| 150 | Pcie |
| 151 | ); |
| 152 | |
| 153 | GlobalSpeedCap = PcieUtilGlobalGenCapability ( |
| 154 | PCIE_PORT_GEN_CAP_BOOT | PCIE_GLOBAL_GEN_CAP_TRAINED_PORTS | PCIE_GLOBAL_GEN_CAP_HOTPLUG_PORTS, |
| 155 | Pcie |
| 156 | ); |
| 157 | |
| 158 | |
| 159 | PcieSetVoltageTN (GlobalSpeedCap, Pcie); |
| 160 | |
| 161 | return Status; |
| 162 | } |
| 163 | |
| 164 | /*----------------------------------------------------------------------------------------*/ |
| 165 | /** |
| 166 | * Per wrapper Pcie Late Init. |
| 167 | * |
| 168 | * |
| 169 | * @param[in] Wrapper Pointer to wrapper configuration descriptor |
| 170 | * @param[in] Buffer Pointer buffer |
| 171 | * @param[in] Pcie Pointer to global PCIe configuration |
| 172 | */ |
| 173 | AGESA_STATUS |
| 174 | STATIC |
| 175 | PcieMidInitCallbackTN ( |
| 176 | IN PCIe_WRAPPER_CONFIG *Wrapper, |
| 177 | IN OUT VOID *Buffer, |
| 178 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 179 | ) |
| 180 | { |
| 181 | PciePwrPowerDownUnusedLanes (Wrapper, Pcie); |
| 182 | PciePowerDownPllInL1TN (Wrapper, Pcie); |
| 183 | PciePwrClockGatingV4 (Wrapper, Pcie); |
| 184 | PcieLockRegisters (Wrapper, Pcie); |
| 185 | return AGESA_SUCCESS; |
| 186 | } |
| 187 | |
| 188 | /*----------------------------------------------------------------------------------------*/ |
| 189 | /** |
| 190 | * Pcie Late Init |
| 191 | * |
| 192 | * Late PCIe initialization |
| 193 | * |
| 194 | * @param[in] Pcie Pointer to global PCIe configuration |
| 195 | * @retval AGESA_SUCCESS Topology successfully mapped |
| 196 | * @retval AGESA_ERROR Topology can not be mapped |
| 197 | */ |
| 198 | |
| 199 | AGESA_STATUS |
| 200 | STATIC |
| 201 | PcieMidInitTN ( |
| 202 | IN PCIe_PLATFORM_CONFIG *Pcie |
| 203 | ) |
| 204 | { |
| 205 | AGESA_STATUS AgesaStatus; |
| 206 | AGESA_STATUS Status; |
| 207 | IDS_HDT_CONSOLE (GNB_TRACE, "PcieMidInitTN Enter\n"); |
| 208 | AgesaStatus = AGESA_SUCCESS; |
| 209 | |
| 210 | Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PcieMidInitCallbackTN, NULL, Pcie); |
| 211 | AGESA_STATUS_UPDATE (Status, AgesaStatus); |
| 212 | |
| 213 | Status = PciePowerGateTN (Pcie); |
| 214 | AGESA_STATUS_UPDATE (Status, AgesaStatus); |
| 215 | |
| 216 | IDS_HDT_CONSOLE (GNB_TRACE, "PcieMidInitTN Exit [0x%x]\n", AgesaStatus); |
| 217 | return AgesaStatus; |
| 218 | } |
| 219 | |
| 220 | /*----------------------------------------------------------------------------------------*/ |
| 221 | /** |
| 222 | * PCIe Mid Init |
| 223 | * |
| 224 | * |
| 225 | * |
| 226 | * @param[in] StdHeader Standard configuration header |
| 227 | * @retval AGESA_STATUS |
| 228 | */ |
| 229 | AGESA_STATUS |
| 230 | PcieMidInterfaceTN ( |
| 231 | IN AMD_CONFIG_PARAMS *StdHeader |
| 232 | ) |
| 233 | { |
| 234 | AGESA_STATUS AgesaStatus; |
| 235 | AGESA_STATUS Status; |
| 236 | PCIe_PLATFORM_CONFIG *Pcie; |
| 237 | IDS_HDT_CONSOLE (GNB_TRACE, "PcieMidInterfaceTN Enter\n"); |
| 238 | AgesaStatus = AGESA_SUCCESS; |
| 239 | Status = PcieLocateConfigurationData (StdHeader, &Pcie); |
| 240 | AGESA_STATUS_UPDATE (Status, AgesaStatus); |
| 241 | if (Status == AGESA_SUCCESS) { |
| 242 | PciePortsVisibilityControlTN (UnhidePorts, Pcie); |
| 243 | |
| 244 | Status = PcieMidPortInitTN (Pcie); |
| 245 | AGESA_STATUS_UPDATE (Status, AgesaStatus); |
| 246 | ASSERT (Status == AGESA_SUCCESS); |
| 247 | |
| 248 | Status = PcieMidInitTN (Pcie); |
| 249 | AGESA_STATUS_UPDATE (Status, AgesaStatus); |
| 250 | ASSERT (Status == AGESA_SUCCESS); |
| 251 | |
| 252 | PciePortsVisibilityControlTN (HidePorts, Pcie); |
| 253 | } |
| 254 | IDS_HDT_CONSOLE (GNB_TRACE, "PcieMidInterfaceTN Exit [0x%x]\n", AgesaStatus); |
| 255 | return AgesaStatus; |
| 256 | } |