zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * GFx tables |
| 6 | * |
| 7 | * |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: GNB |
| 12 | * @e \$Revision: 64726 $ @e \$Date: 2012-01-30 01:00:01 -0600 (Mon, 30 Jan 2012) $ |
| 13 | * |
| 14 | */ |
| 15 | /* |
| 16 | ***************************************************************************** |
| 17 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 18 | * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. |
| 19 | * All rights reserved. |
| 20 | * |
| 21 | * Redistribution and use in source and binary forms, with or without |
| 22 | * modification, are permitted provided that the following conditions are met: |
| 23 | * * Redistributions of source code must retain the above copyright |
| 24 | * notice, this list of conditions and the following disclaimer. |
| 25 | * * Redistributions in binary form must reproduce the above copyright |
| 26 | * notice, this list of conditions and the following disclaimer in the |
| 27 | * documentation and/or other materials provided with the distribution. |
| 28 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 29 | * its contributors may be used to endorse or promote products derived |
| 30 | * from this software without specific prior written permission. |
| 31 | * |
| 32 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 33 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 34 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 35 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 36 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 37 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 38 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 39 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 40 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 41 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 42 | * *************************************************************************** |
| 43 | * |
| 44 | */ |
| 45 | /*---------------------------------------------------------------------------------------- |
| 46 | * M O D U L E S U S E D |
| 47 | *---------------------------------------------------------------------------------------- |
| 48 | */ |
| 49 | #include "AGESA.h" |
| 50 | #include "Gnb.h" |
| 51 | #include "GnbPcie.h" |
| 52 | #include "GnbCommonLib.h" |
| 53 | #include "GnbTable.h" |
| 54 | #include "GnbRegistersTN.h" |
| 55 | #include "cpuFamilyTranslation.h" |
| 56 | #include "GnbInitTN.h" |
| 57 | |
| 58 | /*---------------------------------------------------------------------------------------- |
| 59 | * D E F I N I T I O N S A N D M A C R O S |
| 60 | *---------------------------------------------------------------------------------------- |
| 61 | */ |
| 62 | |
| 63 | |
| 64 | /*---------------------------------------------------------------------------------------- |
| 65 | * T Y P E D E F S A N D S T R U C T U R E S |
| 66 | *---------------------------------------------------------------------------------------- |
| 67 | */ |
| 68 | |
| 69 | |
| 70 | /*---------------------------------------------------------------------------------------- |
| 71 | * P R O T O T Y P E S O F L O C A L F U N C T I O N S |
| 72 | *---------------------------------------------------------------------------------------- |
| 73 | */ |
| 74 | |
| 75 | |
| 76 | /*---------------------------------------------------------------------------------------- |
| 77 | * T A B L E S |
| 78 | *---------------------------------------------------------------------------------------- |
| 79 | */ |
| 80 | |
| 81 | GNB_TABLE ROMDATA GfxGmcColockGatingDisableTN [] = { |
| 82 | //2.1 Disable clock-gating |
| 83 | GNB_ENTRY_WR (TYPE_GMM , 0x20c0 , 0x00000C80), |
| 84 | GNB_ENTRY_WR (TYPE_GMM , 0x2478 , 0x00000400), |
| 85 | GNB_ENTRY_WR (TYPE_GMM , 0x20b8 , 0x00000400), |
| 86 | GNB_ENTRY_WR (TYPE_GMM , 0x20bc , 0x00000400), |
| 87 | GNB_ENTRY_WR (TYPE_GMM , 0x2648 , 0x00000400), |
| 88 | GNB_ENTRY_WR (TYPE_GMM , 0x264c , 0x00000400), |
| 89 | GNB_ENTRY_WR (TYPE_GMM , 0x2650 , 0x00000400), |
| 90 | GNB_ENTRY_WR (TYPE_GMM , 0x15c0 , 0x00001401), |
| 91 | GNB_ENTRY_TERMINATE |
| 92 | }; |
| 93 | |
| 94 | |
| 95 | GNB_TABLE ROMDATA GfxGmcInitTableTN [] = { |
| 96 | GNB_ENTRY_RMW (D18F5x178_TYPE, D18F5x178_ADDRESS, D18F5x178_SwGfxDis_MASK, 0 << D18F5x178_SwGfxDis_OFFSET), |
| 97 | //2.2 System memory address translation |
| 98 | GNB_ENTRY_COPY (GMMx2814_TYPE, GMMx2814_ADDRESS, 0, 32, D18F2x40_dct0_TYPE, D18F2x40_dct0_ADDRESS, 0, 32), |
| 99 | GNB_ENTRY_COPY (GMMx2818_TYPE, GMMx2818_ADDRESS, 0, 32, D18F2x40_dct1_TYPE, D18F2x40_dct1_ADDRESS, 0, 32), |
| 100 | GNB_ENTRY_COPY (GMMx281C_TYPE, GMMx281C_ADDRESS, 0, 32, D18F2x44_dct0_TYPE, D18F2x44_dct0_ADDRESS, 0, 32), |
| 101 | GNB_ENTRY_COPY (GMMx2820_TYPE, GMMx2820_ADDRESS, 0, 32, D18F2x44_dct1_TYPE, D18F2x44_dct1_ADDRESS, 0, 32), |
| 102 | GNB_ENTRY_COPY (GMMx2824_TYPE, GMMx2824_ADDRESS, 0, 32, D18F2x48_dct0_TYPE, D18F2x48_dct0_ADDRESS, 0, 32), |
| 103 | GNB_ENTRY_COPY (GMMx2828_TYPE, GMMx2828_ADDRESS, 0, 32, D18F2x48_dct1_TYPE, D18F2x48_dct1_ADDRESS, 0, 32), |
| 104 | GNB_ENTRY_COPY (GMMx282C_TYPE, GMMx282C_ADDRESS, 0, 32, D18F2x4C_dct0_TYPE, D18F2x4C_dct0_ADDRESS, 0, 32), |
| 105 | GNB_ENTRY_COPY (GMMx2830_TYPE, GMMx2830_ADDRESS, 0, 32, D18F2x4C_dct1_TYPE, D18F2x4C_dct1_ADDRESS, 0, 32), |
| 106 | GNB_ENTRY_COPY (GMMx2834_TYPE, GMMx2834_ADDRESS, 0, 32, D18F2x60_dct0_TYPE, D18F2x60_dct0_ADDRESS, 0, 32), |
| 107 | GNB_ENTRY_COPY (GMMx2838_TYPE, GMMx2838_ADDRESS, 0, 32, D18F2x64_dct0_TYPE, D18F2x64_dct0_ADDRESS, 0, 32), |
| 108 | GNB_ENTRY_COPY (GMMx283C_TYPE, GMMx283C_ADDRESS, 0, 32, D18F2x60_dct1_TYPE, D18F2x60_dct1_ADDRESS, 0, 32), |
| 109 | GNB_ENTRY_COPY (GMMx2840_TYPE, GMMx2840_ADDRESS, 0, 32, D18F2x64_dct1_TYPE, D18F2x64_dct1_ADDRESS, 0, 32), |
| 110 | GNB_ENTRY_COPY (GMMx2844_TYPE, GMMx2844_ADDRESS, 0, 8, D18F2x80_dct0_TYPE, D18F2x80_dct0_ADDRESS, 0, 8), |
| 111 | GNB_ENTRY_COPY (GMMx2844_TYPE, GMMx2844_ADDRESS, 16, 1, D18F2x94_dct0_TYPE, D18F2x94_dct0_ADDRESS, 22, 1), |
| 112 | GNB_ENTRY_COPY (GMMx2844_TYPE, GMMx2844_ADDRESS, 19, 1, D18F2xA8_dct0_TYPE, D18F2xA8_dct0_ADDRESS, 20, 1), |
| 113 | GNB_ENTRY_COPY (GMMx2848_TYPE, GMMx2848_ADDRESS, 0, 8, D18F2x80_dct1_TYPE, D18F2x80_dct1_ADDRESS, 0, 8), |
| 114 | GNB_ENTRY_COPY (GMMx2848_TYPE, GMMx2848_ADDRESS, 16, 1, D18F2x94_dct1_TYPE, D18F2x94_dct1_ADDRESS, 22, 1), |
| 115 | GNB_ENTRY_COPY (GMMx2848_TYPE, GMMx2848_ADDRESS, 19, 1, D18F2xA8_dct1_TYPE, D18F2xA8_dct1_ADDRESS, 20, 1), |
| 116 | GNB_ENTRY_COPY (GMMx284C_TYPE, GMMx284C_ADDRESS, 0, 32, TYPE_D18F2 , 0x110 , 0, 32), |
| 117 | GNB_ENTRY_COPY (GMMx2850_TYPE, GMMx2850_ADDRESS, 0, 32, D18F2x114_TYPE, D18F2x114_ADDRESS, 0, 32), |
| 118 | GNB_ENTRY_COPY (GMMx2854_TYPE, GMMx2854_ADDRESS, 0, 32, D18F1xF0_TYPE, D18F1xF0_ADDRESS, 0, 32), |
| 119 | //GNB_ENTRY_COPY (GMMx2858_TYPE, GMMx2858_ADDRESS, 0, 32, ????, ????, 0, 32), |
| 120 | GNB_ENTRY_COPY (GMMx285C_TYPE, GMMx285C_ADDRESS, 0, 32, TYPE_D18F2 , 0x10c , 0, 32), |
| 121 | // 2.4 RENG init |
| 122 | GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000000), |
| 123 | GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x001b0a05), |
| 124 | GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x0000001D), |
| 125 | GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00080500), |
| 126 | GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000027), |
| 127 | GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x0001050c), |
| 128 | GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x0000002a), |
| 129 | GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x1000051e), |
| 130 | GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x000000ff), |
| 131 | GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x000000ff), |
| 132 | GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x0000002e), |
| 133 | GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00010536), |
| 134 | GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000031), |
| 135 | GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x0001053e), |
| 136 | GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000034), |
| 137 | GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00010546), |
| 138 | GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000037), |
| 139 | GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x001a054e), |
| 140 | GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000053), |
| 141 | GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x0001056f), |
| 142 | GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000056), |
| 143 | GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00010572), |
| 144 | GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000059), |
| 145 | GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00020575), |
| 146 | GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x0000005d), |
| 147 | GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00000800), |
| 148 | GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x0000005f), |
| 149 | GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x001a0801), |
| 150 | GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x0000007b), |
| 151 | GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x0001082a), |
| 152 | GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x0000007e), |
| 153 | GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x0014082d), |
| 154 | GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000094), |
| 155 | GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00040843), |
| 156 | GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x0000009a), |
| 157 | GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00170851), |
| 158 | GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x000000b3), |
| 159 | GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x001d086a), |
| 160 | GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x000000d2), |
| 161 | GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00000891), |
| 162 | GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x000000d4), |
| 163 | GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00000893), |
| 164 | GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x000000d6), |
| 165 | GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00020895), |
| 166 | GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x000000da), |
| 167 | GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x00020899), |
| 168 | GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x000000de), |
| 169 | GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x0002089d), |
| 170 | GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x000000e2), |
| 171 | GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x000208a1), |
| 172 | GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x000000e6), |
| 173 | GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x006808cd), |
| 174 | GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000150), |
| 175 | GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x0016094d), |
| 176 | GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000168), |
| 177 | GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x000d096d), |
| 178 | GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000177), |
| 179 | GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x0009097f), |
| 180 | GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x00000182), |
| 181 | GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x000a098a), |
| 182 | GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x0000018e), |
| 183 | GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x000d0998), |
| 184 | GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x0000019d), |
| 185 | GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x000409a7), |
| 186 | GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x000001a3), |
| 187 | GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x003709cd), |
| 188 | GNB_ENTRY_WR (TYPE_GMM , 0x28cc , 0x000001dc), |
| 189 | GNB_ENTRY_WR (TYPE_GMM , 0x28d0 , 0x000f0a21), |
| 190 | GNB_ENTRY_WR (GMMx28D4_TYPE, GMMx28D4_ADDRESS, 0x7b1ec000), |
| 191 | GNB_ENTRY_WR (GMMx28D8_TYPE, GMMx28D8_ADDRESS, 0x200cf01d), |
| 192 | // 2.5 |
| 193 | GNB_ENTRY_RMW (GMMx5490_TYPE, GMMx5490_ADDRESS, GMMx5490_FB_WRITE_EN_MASK | GMMx5490_FB_READ_EN_MASK, (1 << GMMx5490_FB_READ_EN_OFFSET) | (1 << GMMx5490_FB_WRITE_EN_OFFSET)), |
| 194 | // 2.6 Perfromance tuning |
| 195 | GNB_ENTRY_WR (TYPE_GMM , 0x27d0 , 0x10734847), |
| 196 | GNB_ENTRY_WR (TYPE_GMM , 0x27c0 , 0x00032005), |
| 197 | GNB_ENTRY_WR (TYPE_GMM , 0x27c4 , 0x00C12008), |
| 198 | GNB_ENTRY_WR (TYPE_GMM , 0x27d4 , 0x00003d3c), |
| 199 | GNB_ENTRY_WR (TYPE_GMM , 0x277c , 0x00000007), |
| 200 | GNB_ENTRY_WR (TYPE_GMM , 0x2198 , 0x000221b1), |
| 201 | GNB_ENTRY_WR (TYPE_GMM , 0x2750 , 0x00080A20), |
| 202 | GNB_ENTRY_WR (TYPE_GMM , 0x201c , 0x66660006), |
| 203 | GNB_ENTRY_WR (TYPE_GMM , 0x2020 , 0x70770007), |
| 204 | GNB_ENTRY_WR (TYPE_GMM , 0x2018 , 0x66070050), |
| 205 | GNB_ENTRY_WR (TYPE_GMM , 0x2014 , 0x77550000), |
| 206 | GNB_ENTRY_WR (TYPE_GMM , 0x2794 , 0xfcfcfdfc), |
| 207 | GNB_ENTRY_WR (TYPE_GMM , 0x2798 , 0xfcfcfdfc), |
| 208 | GNB_ENTRY_WR (TYPE_GMM , 0x27a4 , 0x00ffffff), |
| 209 | GNB_ENTRY_WR (TYPE_GMM , 0x27a8 , 0x00ffffff), |
| 210 | GNB_ENTRY_WR (TYPE_GMM , 0x278c , 0x00000004), |
| 211 | GNB_ENTRY_WR (TYPE_GMM , 0x2790 , 0x00000004), |
| 212 | GNB_ENTRY_WR (TYPE_GMM , 0x2628 , 0x44111222), |
| 213 | GNB_ENTRY_WR (TYPE_GMM , 0x25e0 , 0x00000004), |
| 214 | GNB_ENTRY_WR (TYPE_GMM , 0x262c , 0x11222111), |
| 215 | GNB_ENTRY_WR (TYPE_GMM , 0x25e4 , 0x00000002), |
| 216 | //2.7 Miscellaneous programming |
| 217 | GNB_ENTRY_WR (TYPE_GMM , 0x20b4 , 0x00000000), |
| 218 | //2.8 Enabling garlic interface |
| 219 | GNB_ENTRY_RMW (TYPE_GMM , 0x2878 , 0x1 , 1 << 0 ), |
| 220 | // Limit number of garlic credits to 12 |
| 221 | GNB_ENTRY_WR (TYPE_GMM , 0x276c , 0x000000ff), |
| 222 | GNB_ENTRY_WR (TYPE_GMM , 0x2898 , 0x01800360), |
| 223 | GNB_ENTRY_RMW (TYPE_GMM , 0x289c , 0x8000 , 1 << 15 ), |
| 224 | GNB_ENTRY_REV_RMW (0x0000000000000100ull , TYPE_GMM , 0x289c , 0x8000 , 0 << 15 ), |
| 225 | GNB_ENTRY_RMW (GMMxC64_TYPE, GMMxC64_ADDRESS, GMMxC64_MCIFMEM_CACHE_MODE_DIS_MASK, 0 << GMMxC64_MCIFMEM_CACHE_MODE_DIS_OFFSET), |
| 226 | GNB_ENTRY_REV_RMW (0x0000000000000100ull , GMMxC64_TYPE, GMMxC64_ADDRESS, GMMxC64_MCIFMEM_CACHE_MODE_DIS_MASK, 1 << GMMxC64_MCIFMEM_CACHE_MODE_DIS_OFFSET), |
| 227 | //2.10 UVD and VCE latency |
| 228 | //These settings are to improve UVD and VCE latency. |
| 229 | //They need these settings to get good memory performance. |
| 230 | GNB_ENTRY_WR (TYPE_GMM , 0x2750 , 0x00080200), |
| 231 | GNB_ENTRY_WR (TYPE_GMM , 0x2190 , 0x001EA1A1), |
| 232 | GNB_ENTRY_WR (TYPE_GMM , 0x2180 , 0x0000A1E1), |
| 233 | GNB_ENTRY_WR (TYPE_GMM , 0x218c , 0x000FA1E1), |
| 234 | GNB_ENTRY_WR (GMMx2188_TYPE, GMMx2188_ADDRESS, 0x0000A1E1), |
| 235 | GNB_ENTRY_WR (TYPE_GMM , 0x21f0 , 0x0000A1F1), |
| 236 | GNB_ENTRY_WR (TYPE_GMM , 0x21ec , 0x0000A1F1), |
| 237 | GNB_ENTRY_WR (TYPE_GMM , 0x21f8 , 0x0000A1E1), |
| 238 | GNB_ENTRY_WR (TYPE_GMM , 0x21f4 , 0x0000A1E1), |
| 239 | GNB_ENTRY_RMW (TYPE_GMM , 0x690 , 0x20000000 , 1 << 29 ), |
| 240 | GNB_ENTRY_RMW (TYPE_GMM , 0x21a8 , 0x4 , 0), |
| 241 | //MC Performance settings base on memory channel configuration, so, move settings to GfxGmcInitializeSequencerTN() |
| 242 | // GNB_ENTRY_WR (TYPE_GMM , 0x2214 , 0x00000003), |
| 243 | GNB_ENTRY_WR (TYPE_GMM , 0x2218 , 0x0000000C), |
| 244 | GNB_ENTRY_WR (GMMx2888_TYPE, GMMx2888_ADDRESS, 0x000007DE), |
| 245 | GNB_ENTRY_WR (GMMx25C8_TYPE, GMMx25C8_ADDRESS, 0x00403932), |
| 246 | GNB_ENTRY_WR (GMMx2114_TYPE, GMMx2114_ADDRESS, 0x00000015), |
| 247 | //2.11 Remove blackout |
| 248 | GNB_ENTRY_WR (GMMx25C0_TYPE, GMMx25C0_ADDRESS, 0x00000000), |
| 249 | GNB_ENTRY_WR (TYPE_GMM , 0x20ec , 0x000001DC), |
| 250 | GNB_ENTRY_WR (TYPE_GMM , 0x20d4 , 0x00000016), |
| 251 | GNB_ENTRY_WR (TYPE_GMM , 0x20ac , 0x00000000), |
| 252 | GNB_ENTRY_RMW (TYPE_GMM , 0x2760 , 0x3 , 1 << 0 ), |
| 253 | GNB_ENTRY_TERMINATE |
| 254 | }; |
| 255 | |
| 256 | GNB_TABLE ROMDATA GfxGmcColockGatingEnableTN [] = { |
| 257 | GNB_ENTRY_WR (TYPE_GMM , 0x20c0 , 0x00040c80), |
| 258 | GNB_ENTRY_WR (TYPE_GMM , 0x2478 , 0x00040400), |
| 259 | GNB_ENTRY_WR (TYPE_GMM , 0x20b8 , 0x00040400), |
| 260 | GNB_ENTRY_WR (TYPE_GMM , 0x20bc , 0x00040400), |
| 261 | GNB_ENTRY_WR (TYPE_GMM , 0x2648 , 0x00040400), |
| 262 | GNB_ENTRY_WR (TYPE_GMM , 0x264c , 0x00040400), |
| 263 | GNB_ENTRY_WR (TYPE_GMM , 0x2650 , 0x00040400), |
| 264 | GNB_ENTRY_WR (TYPE_GMM , 0x15c0 , 0x00041401), |
| 265 | //In addition to above registers it is necessary to reset override bits for VMC, MCB, and MCD blocks |
| 266 | //Implement in GnbCgttOverrideTN |
| 267 | GNB_ENTRY_TERMINATE |
| 268 | }; |
| 269 | |
| 270 | GNB_TABLE ROMDATA GfxEnvInitTableTN [] = { |
| 271 | GNB_ENTRY_PROPERTY_RMW ( |
| 272 | TABLE_PROPERTY_IGFX_DISABLED, |
| 273 | TYPE_GMM , |
| 274 | 0xe60 , |
| 275 | 0x0, |
| 276 | (0x1 << 1 ) | (0x1 << 0 ) | |
| 277 | (0x1 << 5 ) | (0x1 << 2 ) | |
| 278 | (0x1 << 7 ) | (0x1 << 6 ) | |
| 279 | (0x1 << 9 ) | (0x1 << 8 ) | |
| 280 | (0x1 << 11 ) | (0x1 << 10 ) | |
| 281 | (0x1 << 14 ) | (0x1 << 13 ) | |
| 282 | (0x1 << 17 ) | (0x1 << 15 ) | |
| 283 | (0x1 << 19 ) | (0x1 << 18 ) | |
| 284 | (0x1 << 24 ) | (0x1 << 20 ) |
| 285 | ), |
| 286 | //--------------------------------------------------------------------------- |
| 287 | // Configure GMC Power Island |
| 288 | GNB_ENTRY_WR ( |
| 289 | D0F0xBC_xE0300004_TYPE, |
| 290 | D0F0xBC_xE0300004_ADDRESS, |
| 291 | (10 << 0 ) | (4 << 8 ) | |
| 292 | (5 << 16 ) |
| 293 | ), |
| 294 | GNB_ENTRY_WR ( |
| 295 | D0F0xBC_xE0300000_TYPE, |
| 296 | D0F0xBC_xE0300000_ADDRESS, |
| 297 | (0xff << D0F0xBC_xE0300000_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300000_WriteOp_OFFSET) | |
| 298 | (2 << D0F0xBC_xE0300000_RegAddr_OFFSET) |
| 299 | ), |
| 300 | GNB_ENTRY_STALL (1), |
| 301 | GNB_ENTRY_WR ( |
| 302 | D0F0xBC_xE0300004_TYPE, |
| 303 | D0F0xBC_xE0300004_ADDRESS, |
| 304 | (90 << 0 ) | (50 << 12 ) |
| 305 | ), |
| 306 | GNB_ENTRY_WR ( |
| 307 | D0F0xBC_xE0300000_TYPE, |
| 308 | D0F0xBC_xE0300000_ADDRESS, |
| 309 | (0xff << D0F0xBC_xE0300000_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300000_WriteOp_OFFSET) | |
| 310 | (3 << D0F0xBC_xE0300000_RegAddr_OFFSET) |
| 311 | ), |
| 312 | GNB_ENTRY_STALL (1), |
| 313 | GNB_ENTRY_WR ( |
| 314 | D0F0xBC_xE0300004_TYPE, |
| 315 | D0F0xBC_xE0300004_ADDRESS, |
| 316 | 0x0 |
| 317 | ), |
| 318 | GNB_ENTRY_WR ( |
| 319 | D0F0xBC_xE0300000_TYPE, |
| 320 | D0F0xBC_xE0300000_ADDRESS, |
| 321 | (0xff << D0F0xBC_xE0300000_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300000_WriteOp_OFFSET) | (1 << D0F0xBC_xE0300000_RegAddr_OFFSET) |
| 322 | ), |
| 323 | GNB_ENTRY_STALL (1), |
| 324 | // Shutdown GMC if integrated GFX disabled |
| 325 | GNB_ENTRY_PROPERTY_RMW ( |
| 326 | TABLE_PROPERTY_IGFX_DISABLED, |
| 327 | D0F0xBC_xE0003024_TYPE, |
| 328 | D0F0xBC_xE0003024_ADDRESS, |
| 329 | 0x1, |
| 330 | 0x1 |
| 331 | ), |
| 332 | GNB_ENTRY_PROPERTY_WR ( |
| 333 | TABLE_PROPERTY_IGFX_DISABLED, |
| 334 | D0F0xBC_xE0300000_TYPE, |
| 335 | D0F0xBC_xE0300000_ADDRESS, |
| 336 | (0xff << D0F0xBC_xE0300000_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300000_PowerDown_OFFSET) | |
| 337 | (1 << D0F0xBC_xE0300000_P1Select_OFFSET) | (1 << D0F0xBC_xE0300000_P2Select_OFFSET) |
| 338 | ), |
| 339 | GNB_ENTRY_PROPERTY_POLL ( |
| 340 | TABLE_PROPERTY_IGFX_DISABLED, |
| 341 | D0F0xBC_xE0300200_TYPE, |
| 342 | D0F0xBC_xE0300200_ADDRESS, |
| 343 | D0F0xBC_xE0300200_P1IsoN_MASK, |
| 344 | 0 |
| 345 | ), |
| 346 | GNB_ENTRY_PROPERTY_RMW ( |
| 347 | TABLE_PROPERTY_IGFX_DISABLED, |
| 348 | D0F0xBC_xE0003024_TYPE, |
| 349 | D0F0xBC_xE0003024_ADDRESS, |
| 350 | 0x1, |
| 351 | 0x0 |
| 352 | ), |
| 353 | //--------------------------------------------------------------------------- |
| 354 | // Configure UVD Power Island |
| 355 | GNB_ENTRY_WR ( |
| 356 | D0F0xBC_xE0300040_TYPE, |
| 357 | D0F0xBC_xE0300040_ADDRESS, |
| 358 | (10 << 0 ) | (50 << 8 ) | |
| 359 | (5 << 16 ) |
| 360 | ), |
| 361 | GNB_ENTRY_WR ( |
| 362 | D0F0xBC_xE030003C_TYPE, |
| 363 | D0F0xBC_xE030003C_ADDRESS, |
| 364 | (0xff << D0F0xBC_xE030003C_FsmAddr_OFFSET) | (1 << D0F0xBC_xE030003C_WriteOp_OFFSET) | |
| 365 | (2 << D0F0xBC_xE030003C_RegAddr_OFFSET) |
| 366 | ), |
| 367 | GNB_ENTRY_STALL (1), |
| 368 | GNB_ENTRY_WR ( |
| 369 | D0F0xBC_xE0300040_TYPE, |
| 370 | D0F0xBC_xE0300040_ADDRESS, |
| 371 | (50 << 0 ) | (50 << 12 ) |
| 372 | ), |
| 373 | GNB_ENTRY_WR ( |
| 374 | D0F0xBC_xE030003C_TYPE, |
| 375 | D0F0xBC_xE030003C_ADDRESS, |
| 376 | (0xff << D0F0xBC_xE030003C_FsmAddr_OFFSET) | (1 << D0F0xBC_xE030003C_WriteOp_OFFSET) | |
| 377 | (3 << D0F0xBC_xE030003C_RegAddr_OFFSET) |
| 378 | ), |
| 379 | GNB_ENTRY_STALL (1), |
| 380 | GNB_ENTRY_WR ( |
| 381 | D0F0xBC_xE0300040_TYPE, |
| 382 | D0F0xBC_xE0300040_ADDRESS, |
| 383 | 0x0 |
| 384 | ), |
| 385 | GNB_ENTRY_WR ( |
| 386 | D0F0xBC_xE030003C_TYPE, |
| 387 | D0F0xBC_xE030003C_ADDRESS, |
| 388 | (0xff << D0F0xBC_xE030003C_FsmAddr_OFFSET) | (1 << D0F0xBC_xE030003C_WriteOp_OFFSET) | (1 << D0F0xBC_xE030003C_RegAddr_OFFSET) |
| 389 | ), |
| 390 | GNB_ENTRY_STALL (1), |
| 391 | // Shutdown UVD if integrated GFX disabled |
| 392 | GNB_ENTRY_PROPERTY_RMW ( |
| 393 | TABLE_PROPERTY_IGFX_DISABLED, |
| 394 | D0F0xBC_xE0003024_TYPE, |
| 395 | D0F0xBC_xE0003024_ADDRESS, |
| 396 | 0x1, |
| 397 | 0x1 |
| 398 | ), |
| 399 | GNB_ENTRY_PROPERTY_WR ( |
| 400 | TABLE_PROPERTY_IGFX_DISABLED, |
| 401 | D0F0xBC_xE030003C_TYPE, |
| 402 | D0F0xBC_xE030003C_ADDRESS, |
| 403 | (0xff << D0F0xBC_xE030003C_FsmAddr_OFFSET) | (1 << D0F0xBC_xE030003C_PowerDown_OFFSET) | |
| 404 | (1 << D0F0xBC_xE030003C_P1Select_OFFSET) | (1 << D0F0xBC_xE030003C_P2Select_OFFSET) |
| 405 | ), |
| 406 | GNB_ENTRY_PROPERTY_POLL ( |
| 407 | TABLE_PROPERTY_IGFX_DISABLED, |
| 408 | D0F0xBC_xE0300218_TYPE, |
| 409 | D0F0xBC_xE0300218_ADDRESS, |
| 410 | D0F0xBC_xE0300218_P1IsoN_MASK, |
| 411 | 0x0 |
| 412 | ), |
| 413 | GNB_ENTRY_PROPERTY_RMW ( |
| 414 | TABLE_PROPERTY_IGFX_DISABLED, |
| 415 | D0F0xBC_xE0300324_TYPE, |
| 416 | D0F0xBC_xE0300324_ADDRESS, |
| 417 | D0F0xBC_xE0300324_UvdPgfsmClockEn_MASK, |
| 418 | 0x0 |
| 419 | ), |
| 420 | GNB_ENTRY_PROPERTY_RMW ( |
| 421 | TABLE_PROPERTY_IGFX_DISABLED, |
| 422 | D0F0xBC_xE0003024_TYPE, |
| 423 | D0F0xBC_xE0003024_ADDRESS, |
| 424 | 0x1, |
| 425 | 0x0 |
| 426 | ), |
| 427 | //--------------------------------------------------------------------------- |
| 428 | // Configure VCE Power Island |
| 429 | GNB_ENTRY_WR ( |
| 430 | D0F0xBC_xE0300028_TYPE, |
| 431 | D0F0xBC_xE0300028_ADDRESS, |
| 432 | (10 << 0 ) | (50 << 8 ) | |
| 433 | (5 << 16 ) |
| 434 | ), |
| 435 | GNB_ENTRY_WR ( |
| 436 | D0F0xBC_xE0300024_TYPE, |
| 437 | D0F0xBC_xE0300024_ADDRESS, |
| 438 | (0xff << D0F0xBC_xE0300024_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300024_WriteOp_OFFSET) | |
| 439 | (2 << D0F0xBC_xE0300024_RegAddr_OFFSET) |
| 440 | ), |
| 441 | GNB_ENTRY_STALL (1), |
| 442 | GNB_ENTRY_WR ( |
| 443 | D0F0xBC_xE0300028_TYPE, |
| 444 | D0F0xBC_xE0300028_ADDRESS, |
| 445 | (50 << 0 ) | (50 << 12 ) |
| 446 | ), |
| 447 | GNB_ENTRY_WR ( |
| 448 | D0F0xBC_xE0300024_TYPE, |
| 449 | D0F0xBC_xE0300024_ADDRESS, |
| 450 | (0xff << D0F0xBC_xE0300024_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300024_WriteOp_OFFSET) | |
| 451 | (3 << D0F0xBC_xE0300024_RegAddr_OFFSET) |
| 452 | ), |
| 453 | GNB_ENTRY_STALL (1), |
| 454 | GNB_ENTRY_WR ( |
| 455 | D0F0xBC_xE0300028_TYPE, |
| 456 | D0F0xBC_xE0300028_ADDRESS, |
| 457 | 0x0 |
| 458 | ), |
| 459 | GNB_ENTRY_WR ( |
| 460 | D0F0xBC_xE0300024_TYPE, |
| 461 | D0F0xBC_xE0300024_ADDRESS, |
| 462 | (0xff << D0F0xBC_xE0300024_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300024_WriteOp_OFFSET) | (1 << D0F0xBC_xE0300024_RegAddr_OFFSET) |
| 463 | ), |
| 464 | GNB_ENTRY_STALL (1), |
| 465 | // Shutdown VCE if integrated GFX disabled |
| 466 | GNB_ENTRY_PROPERTY_RMW ( |
| 467 | TABLE_PROPERTY_IGFX_DISABLED, |
| 468 | D0F0xBC_xE0003024_TYPE, |
| 469 | D0F0xBC_xE0003024_ADDRESS, |
| 470 | 0x1, |
| 471 | 0x1 |
| 472 | ), |
| 473 | GNB_ENTRY_PROPERTY_WR ( |
| 474 | TABLE_PROPERTY_IGFX_DISABLED, |
| 475 | D0F0xBC_xE0300024_TYPE, |
| 476 | D0F0xBC_xE0300024_ADDRESS, |
| 477 | (0xff << D0F0xBC_xE0300024_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300024_PowerDown_OFFSET) | |
| 478 | (1 << D0F0xBC_xE0300024_P1Select_OFFSET) | (1 << D0F0xBC_xE0300024_P2Select_OFFSET) |
| 479 | ), |
| 480 | GNB_ENTRY_PROPERTY_POLL ( |
| 481 | TABLE_PROPERTY_IGFX_DISABLED, |
| 482 | D0F0xBC_xE030020C_TYPE, |
| 483 | D0F0xBC_xE030020C_ADDRESS, |
| 484 | D0F0xBC_xE030020C_P1IsoN_MASK, |
| 485 | 0x0 |
| 486 | ), |
| 487 | GNB_ENTRY_PROPERTY_RMW ( |
| 488 | TABLE_PROPERTY_IGFX_DISABLED, |
| 489 | D0F0xBC_xE0300324_TYPE, |
| 490 | D0F0xBC_xE0300324_ADDRESS, |
| 491 | D0F0xBC_xE0300324_VcePgfsmClockEn_MASK, |
| 492 | 0x0 |
| 493 | ), |
| 494 | GNB_ENTRY_PROPERTY_RMW ( |
| 495 | TABLE_PROPERTY_IGFX_DISABLED, |
| 496 | D0F0xBC_xE0003024_TYPE, |
| 497 | D0F0xBC_xE0003024_ADDRESS, |
| 498 | 0x1, |
| 499 | 0x0 |
| 500 | ), |
| 501 | |
| 502 | //--------------------------------------------------------------------------- |
| 503 | // Configure DCE Power Island |
| 504 | // Step 1: Take control over DC2 PGFSM. By default display sends power up/down commands. |
| 505 | GNB_ENTRY_WR ( |
| 506 | D0F0xBC_xE03002DC_TYPE, |
| 507 | D0F0xBC_xE03002DC_ADDRESS, |
| 508 | (1 << D0F0xBC_xE03002DC_DC2_PGFSM_CONTROL_OFFSET) |
| 509 | ), |
| 510 | //Step 2: Read CC_RCU_FUSES register |
| 511 | //If Internal GPU is fused off go to Step 3, ELSE Go to Step 4. |
| 512 | |
| 513 | //Step 3: Enable PGFSM commands during reset |
| 514 | GNB_ENTRY_PROPERTY_RMW ( |
| 515 | TABLE_PROPERTY_IGFX_DISABLED, |
| 516 | D0F0xBC_xE0003024_TYPE, |
| 517 | D0F0xBC_xE0003024_ADDRESS, |
| 518 | 0x1, |
| 519 | 0x1 |
| 520 | ), |
| 521 | //Step 4: |
| 522 | GNB_ENTRY_WR ( |
| 523 | D0F0xBC_xE0300034_TYPE, |
| 524 | D0F0xBC_xE0300034_ADDRESS, |
| 525 | (10 << 0 ) | (50 << 8 ) | |
| 526 | (5 << 16 ) |
| 527 | ), |
| 528 | GNB_ENTRY_WR ( |
| 529 | D0F0xBC_xE0300030_TYPE, |
| 530 | D0F0xBC_xE0300030_ADDRESS, |
| 531 | (0xff << D0F0xBC_xE0300030_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300030_WriteOp_OFFSET) | |
| 532 | (2 << D0F0xBC_xE0300030_RegAddr_OFFSET) |
| 533 | ), |
| 534 | GNB_ENTRY_STALL (1), |
| 535 | GNB_ENTRY_WR ( |
| 536 | D0F0xBC_xE0300034_TYPE, |
| 537 | D0F0xBC_xE0300034_ADDRESS, |
| 538 | (50 << 0 ) | (50 << 12 ) |
| 539 | ), |
| 540 | GNB_ENTRY_WR ( |
| 541 | D0F0xBC_xE0300030_TYPE, |
| 542 | D0F0xBC_xE0300030_ADDRESS, |
| 543 | (0xff << D0F0xBC_xE0300030_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300030_WriteOp_OFFSET) | |
| 544 | (3 << D0F0xBC_xE0300030_WriteOp_OFFSET) |
| 545 | ), |
| 546 | GNB_ENTRY_STALL (1), |
| 547 | GNB_ENTRY_WR ( |
| 548 | D0F0xBC_xE0300034_TYPE, |
| 549 | D0F0xBC_xE0300034_ADDRESS, |
| 550 | 0x0 |
| 551 | ), |
| 552 | GNB_ENTRY_WR ( |
| 553 | D0F0xBC_xE0300030_TYPE, |
| 554 | D0F0xBC_xE0300030_ADDRESS, |
| 555 | (0xff << D0F0xBC_xE0300030_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300030_WriteOp_OFFSET) | (1 << D0F0xBC_xE0300030_WriteOp_OFFSET) |
| 556 | ), |
| 557 | GNB_ENTRY_STALL (1), |
| 558 | //Step 5: IF (cc_rcu_fuses.f.gpu_dis == 0x1) Skip Step6 ELSE Go to Step 6 |
| 559 | //Step 6: Disable PGFSM commands during reset. Move to after shutdown DCE. |
| 560 | //Step 7: Release control over DC2 PGFSM. Move to after shutdown DCE. |
| 561 | |
| 562 | // Shutdown DCE if integrated GFX disabled |
| 563 | //Step 1: Take control over DC2 PGFSM. By default display sends power up down commands. |
| 564 | //Step 2: Read CC_RCU_FUSES register |
| 565 | //Step 3: Enable PGFSM commands during reset |
| 566 | //Step 4: Make sure SCLK frequency is below 400Mhz |
| 567 | //Step 5: Enable PGFSM clock |
| 568 | GNB_ENTRY_PROPERTY_RMW ( |
| 569 | TABLE_PROPERTY_IGFX_DISABLED, |
| 570 | D0F0xBC_xE0300324_TYPE, |
| 571 | D0F0xBC_xE0300324_ADDRESS, |
| 572 | D0F0xBC_xE0300324_Dc2PgfsmClockEn_MASK, |
| 573 | (1 << D0F0xBC_xE0300324_Dc2PgfsmClockEn_OFFSET) |
| 574 | ), |
| 575 | //Step 6 |
| 576 | GNB_ENTRY_PROPERTY_WR ( |
| 577 | TABLE_PROPERTY_IGFX_DISABLED, |
| 578 | D0F0xBC_xE0300030_TYPE, |
| 579 | D0F0xBC_xE0300030_ADDRESS, |
| 580 | (0xff << D0F0xBC_xE0300030_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300030_PowerDown_OFFSET) | |
| 581 | (1 << D0F0xBC_xE0300030_P1Select_OFFSET) | (1 << D0F0xBC_xE0300030_P2Select_OFFSET) |
| 582 | ), |
| 583 | //Step 7 |
| 584 | GNB_ENTRY_PROPERTY_POLL ( |
| 585 | TABLE_PROPERTY_IGFX_DISABLED, |
| 586 | D0F0xBC_xE0300210_TYPE, |
| 587 | D0F0xBC_xE0300210_ADDRESS, |
| 588 | D0F0xBC_xE0300210_P1IsoN_MASK, |
| 589 | (0 << D0F0xBC_xE0300210_P1IsoN_OFFSET) |
| 590 | ), |
| 591 | //Step 8: Restore previous SCLK divider |
| 592 | //Step 9: Wait PSO daughter to be asserted |
| 593 | GNB_ENTRY_PROPERTY_POLL ( |
| 594 | TABLE_PROPERTY_IGFX_DISABLED, |
| 595 | TYPE_D0F0xBC , |
| 596 | 0xe0300210 , |
| 597 | 0x2000 , |
| 598 | (1 << 13 ) |
| 599 | ), |
| 600 | //Step 10: Turn off PGFSM clock |
| 601 | GNB_ENTRY_PROPERTY_RMW ( |
| 602 | TABLE_PROPERTY_IGFX_DISABLED, |
| 603 | D0F0xBC_xE0300324_TYPE, |
| 604 | D0F0xBC_xE0300324_ADDRESS, |
| 605 | D0F0xBC_xE0300324_Dc2PgfsmClockEn_MASK, |
| 606 | (0 << D0F0xBC_xE0300324_Dc2PgfsmClockEn_OFFSET) |
| 607 | ), |
| 608 | //Step 11: Disable PGFSM commands during reset. Same final 2 step as DCE power island |
| 609 | GNB_ENTRY_RMW ( |
| 610 | D0F0xBC_xE0003024_TYPE, |
| 611 | D0F0xBC_xE0003024_ADDRESS, |
| 612 | 0x1, |
| 613 | 0x0 |
| 614 | ), |
| 615 | GNB_ENTRY_WR ( |
| 616 | D0F0xBC_xE03002DC_TYPE, |
| 617 | D0F0xBC_xE03002DC_ADDRESS, |
| 618 | (0 << D0F0xBC_xE03002DC_DC2_PGFSM_CONTROL_OFFSET) |
| 619 | ), |
| 620 | |
| 621 | //--------------------------------------------------------------------------- |
| 622 | // Configure GFX Power Island |
| 623 | |
| 624 | //Step 3 |
| 625 | GNB_ENTRY_WR ( |
| 626 | D0F0xBC_xE0300058_TYPE, |
| 627 | D0F0xBC_xE0300058_ADDRESS, |
| 628 | (5 << 16 ) | (4 << 8 ) | |
| 629 | (10 << 0 ) //reg0 |
| 630 | ), |
| 631 | GNB_ENTRY_WR ( |
| 632 | D0F0xBC_xE0300054_TYPE, |
| 633 | D0F0xBC_xE0300054_ADDRESS, |
| 634 | (0xff << D0F0xBC_xE0300054_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300054_WriteOp_OFFSET) | |
| 635 | (2 << D0F0xBC_xE0300054_RegAddr_OFFSET) |
| 636 | ), |
| 637 | GNB_ENTRY_STALL (1), |
| 638 | GNB_ENTRY_WR ( |
| 639 | D0F0xBC_xE0300058_TYPE, |
| 640 | D0F0xBC_xE0300058_ADDRESS, |
| 641 | (50 << 0 ) | (50 << 12 ) //reg1 |
| 642 | ), |
| 643 | GNB_ENTRY_WR ( |
| 644 | D0F0xBC_xE0300054_TYPE, |
| 645 | D0F0xBC_xE0300054_ADDRESS, |
| 646 | (0xff << D0F0xBC_xE0300054_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300054_WriteOp_OFFSET) | |
| 647 | (3 << D0F0xBC_xE0300054_RegAddr_OFFSET) |
| 648 | ), |
| 649 | GNB_ENTRY_STALL (1), |
| 650 | GNB_ENTRY_WR ( |
| 651 | D0F0xBC_xE0300058_TYPE, |
| 652 | D0F0xBC_xE0300058_ADDRESS, |
| 653 | 0 // control |
| 654 | ), |
| 655 | GNB_ENTRY_WR ( |
| 656 | D0F0xBC_xE0300054_TYPE, |
| 657 | D0F0xBC_xE0300054_ADDRESS, |
| 658 | (0xff << D0F0xBC_xE0300054_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300054_WriteOp_OFFSET) | |
| 659 | (1 << D0F0xBC_xE0300054_RegAddr_OFFSET) |
| 660 | ), |
| 661 | GNB_ENTRY_STALL (1), |
| 662 | // Step 4 |
| 663 | GNB_ENTRY_WR ( |
| 664 | D0F0xBC_xE0300074_TYPE, |
| 665 | D0F0xBC_xE0300074_ADDRESS, |
| 666 | (5 << 16 ) | (4 << 8 ) | |
| 667 | (10 << 0 ) //reg0 |
| 668 | ), |
| 669 | GNB_ENTRY_WR ( |
| 670 | D0F0xBC_xE0300070_TYPE, |
| 671 | D0F0xBC_xE0300070_ADDRESS, |
| 672 | (0xff << D0F0xBC_xE0300070_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300070_WriteOp_OFFSET) | |
| 673 | (2 << D0F0xBC_xE0300070_RegAddr_OFFSET) |
| 674 | ), |
| 675 | GNB_ENTRY_STALL (1), |
| 676 | GNB_ENTRY_WR ( |
| 677 | D0F0xBC_xE0300074_TYPE, |
| 678 | D0F0xBC_xE0300074_ADDRESS, |
| 679 | (50 << 0 ) | (50 << 12 ) //reg1 |
| 680 | ), |
| 681 | GNB_ENTRY_WR ( |
| 682 | D0F0xBC_xE0300070_TYPE, |
| 683 | D0F0xBC_xE0300070_ADDRESS, |
| 684 | (0xff << D0F0xBC_xE0300070_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300070_WriteOp_OFFSET) | |
| 685 | (3 << D0F0xBC_xE0300070_RegAddr_OFFSET) |
| 686 | ), |
| 687 | GNB_ENTRY_STALL (1), |
| 688 | GNB_ENTRY_WR ( |
| 689 | D0F0xBC_xE0300074_TYPE, |
| 690 | D0F0xBC_xE0300074_ADDRESS, |
| 691 | 0 // control |
| 692 | ), |
| 693 | GNB_ENTRY_WR ( |
| 694 | D0F0xBC_xE0300070_TYPE, |
| 695 | D0F0xBC_xE0300070_ADDRESS, |
| 696 | (0xff << D0F0xBC_xE0300070_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300070_WriteOp_OFFSET) | |
| 697 | (1 << D0F0xBC_xE0300070_RegAddr_OFFSET) |
| 698 | ), |
| 699 | GNB_ENTRY_STALL (1), |
| 700 | // Step 5 |
| 701 | GNB_ENTRY_WR ( |
| 702 | D0F0xBC_xE0300090_TYPE, |
| 703 | D0F0xBC_xE0300090_ADDRESS, |
| 704 | (5 << 16 ) | (4 << 8 ) | |
| 705 | (10 << 0 ) //reg0 |
| 706 | ), |
| 707 | GNB_ENTRY_WR ( |
| 708 | D0F0xBC_xE030008C_TYPE, |
| 709 | D0F0xBC_xE030008C_ADDRESS, |
| 710 | (0xff << D0F0xBC_xE030008C_FsmAddr_OFFSET) | (1 << D0F0xBC_xE030008C_WriteOp_OFFSET) | |
| 711 | (2 << D0F0xBC_xE030008C_RegAddr_OFFSET) |
| 712 | ), |
| 713 | GNB_ENTRY_STALL (1), |
| 714 | GNB_ENTRY_WR ( |
| 715 | D0F0xBC_xE0300090_TYPE, |
| 716 | D0F0xBC_xE0300090_ADDRESS, |
| 717 | (50 << 0 ) | (50 << 12 ) //reg1 |
| 718 | ), |
| 719 | GNB_ENTRY_WR ( |
| 720 | D0F0xBC_xE030008C_TYPE, |
| 721 | D0F0xBC_xE030008C_ADDRESS, |
| 722 | (0xff << D0F0xBC_xE030008C_FsmAddr_OFFSET) | (1 << D0F0xBC_xE030008C_WriteOp_OFFSET) | |
| 723 | (3 << D0F0xBC_xE030008C_RegAddr_OFFSET) |
| 724 | ), |
| 725 | GNB_ENTRY_STALL (1), |
| 726 | GNB_ENTRY_WR ( |
| 727 | D0F0xBC_xE0300090_TYPE, |
| 728 | D0F0xBC_xE0300090_ADDRESS, |
| 729 | 0 // control |
| 730 | ), |
| 731 | GNB_ENTRY_WR ( |
| 732 | D0F0xBC_xE030008C_TYPE, |
| 733 | D0F0xBC_xE030008C_ADDRESS, |
| 734 | (0xff << D0F0xBC_xE030008C_FsmAddr_OFFSET) | (1 << D0F0xBC_xE030008C_WriteOp_OFFSET) | |
| 735 | (1 << D0F0xBC_xE030008C_RegAddr_OFFSET) |
| 736 | ), |
| 737 | GNB_ENTRY_STALL (1), |
| 738 | // Step 6 |
| 739 | GNB_ENTRY_WR ( |
| 740 | D0F0xBC_xE03000AC_TYPE, |
| 741 | D0F0xBC_xE03000AC_ADDRESS, |
| 742 | (5 << 16 ) | (4 << 8 ) | |
| 743 | (10 << 0 ) //reg0 |
| 744 | ), |
| 745 | GNB_ENTRY_WR ( |
| 746 | D0F0xBC_xE03000A8_TYPE, |
| 747 | D0F0xBC_xE03000A8_ADDRESS, |
| 748 | (0xff << D0F0xBC_xE03000A8_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000A8_WriteOp_OFFSET) | |
| 749 | (2 << D0F0xBC_xE03000A8_RegAddr_OFFSET) |
| 750 | ), |
| 751 | GNB_ENTRY_STALL (1), |
| 752 | GNB_ENTRY_WR ( |
| 753 | D0F0xBC_xE03000AC_TYPE, |
| 754 | D0F0xBC_xE03000AC_ADDRESS, |
| 755 | (50 << 0 ) | (50 << 12 ) //reg1 |
| 756 | ), |
| 757 | GNB_ENTRY_WR ( |
| 758 | D0F0xBC_xE03000A8_TYPE, |
| 759 | D0F0xBC_xE03000A8_ADDRESS, |
| 760 | (0xff << D0F0xBC_xE03000A8_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000A8_WriteOp_OFFSET) | |
| 761 | (3 << D0F0xBC_xE03000A8_RegAddr_OFFSET) |
| 762 | ), |
| 763 | GNB_ENTRY_STALL (1), |
| 764 | GNB_ENTRY_WR ( |
| 765 | D0F0xBC_xE03000AC_TYPE, |
| 766 | D0F0xBC_xE03000AC_ADDRESS, |
| 767 | 0 // control |
| 768 | ), |
| 769 | GNB_ENTRY_WR ( |
| 770 | D0F0xBC_xE03000A8_TYPE, |
| 771 | D0F0xBC_xE03000A8_ADDRESS, |
| 772 | (0xff << D0F0xBC_xE03000A8_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000A8_WriteOp_OFFSET) | |
| 773 | (1 << D0F0xBC_xE03000A8_RegAddr_OFFSET) |
| 774 | ), |
| 775 | GNB_ENTRY_STALL (1), |
| 776 | // Step 7 |
| 777 | GNB_ENTRY_WR ( |
| 778 | D0F0xBC_xE03000C8_TYPE, |
| 779 | D0F0xBC_xE03000C8_ADDRESS, |
| 780 | (5 << 16 ) | (4 << 8 ) | |
| 781 | (10 << 0 ) //reg0 |
| 782 | ), |
| 783 | GNB_ENTRY_WR ( |
| 784 | D0F0xBC_xE03000C4_TYPE, |
| 785 | D0F0xBC_xE03000C4_ADDRESS, |
| 786 | (0xff << D0F0xBC_xE03000C4_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000C4_WriteOp_OFFSET) | |
| 787 | (2 << D0F0xBC_xE03000C4_RegAddr_OFFSET) |
| 788 | ), |
| 789 | GNB_ENTRY_STALL (1), |
| 790 | GNB_ENTRY_WR ( |
| 791 | D0F0xBC_xE03000C8_TYPE, |
| 792 | D0F0xBC_xE03000C8_ADDRESS, |
| 793 | (50 << 0 ) | (50 << 12 ) //reg1 |
| 794 | ), |
| 795 | GNB_ENTRY_WR ( |
| 796 | D0F0xBC_xE03000C4_TYPE, |
| 797 | D0F0xBC_xE03000C4_ADDRESS, |
| 798 | (0xff << D0F0xBC_xE03000C4_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000C4_WriteOp_OFFSET) | |
| 799 | (3 << D0F0xBC_xE03000C4_RegAddr_OFFSET) |
| 800 | ), |
| 801 | GNB_ENTRY_STALL (1), |
| 802 | GNB_ENTRY_WR ( |
| 803 | D0F0xBC_xE03000C8_TYPE, |
| 804 | D0F0xBC_xE03000C8_ADDRESS, |
| 805 | 0 // control |
| 806 | ), |
| 807 | GNB_ENTRY_WR ( |
| 808 | D0F0xBC_xE03000C4_TYPE, |
| 809 | D0F0xBC_xE03000C4_ADDRESS, |
| 810 | (0xff << D0F0xBC_xE03000C4_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000C4_WriteOp_OFFSET) | |
| 811 | (1 << D0F0xBC_xE03000C4_RegAddr_OFFSET) |
| 812 | ), |
| 813 | GNB_ENTRY_STALL (1), |
| 814 | // Step 8 |
| 815 | GNB_ENTRY_WR ( |
| 816 | D0F0xBC_xE03000E4_TYPE, |
| 817 | D0F0xBC_xE03000E4_ADDRESS, |
| 818 | (5 << 16 ) | (4 << 8 ) | |
| 819 | (10 << 0 ) //reg0 |
| 820 | ), |
| 821 | GNB_ENTRY_WR ( |
| 822 | D0F0xBC_xE03000E0_TYPE, |
| 823 | D0F0xBC_xE03000E0_ADDRESS, |
| 824 | (0xff << D0F0xBC_xE03000E0_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000E0_WriteOp_OFFSET) | |
| 825 | (2 << D0F0xBC_xE03000E0_RegAddr_OFFSET) |
| 826 | ), |
| 827 | GNB_ENTRY_STALL (1), |
| 828 | GNB_ENTRY_WR ( |
| 829 | D0F0xBC_xE03000E4_TYPE, |
| 830 | D0F0xBC_xE03000E4_ADDRESS, |
| 831 | (50 << 0 ) | (50 << 12 ) //reg1 |
| 832 | ), |
| 833 | GNB_ENTRY_WR ( |
| 834 | D0F0xBC_xE03000E0_TYPE, |
| 835 | D0F0xBC_xE03000E0_ADDRESS, |
| 836 | (0xff << D0F0xBC_xE03000E0_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000E0_WriteOp_OFFSET) | |
| 837 | (3 << D0F0xBC_xE03000E0_RegAddr_OFFSET) |
| 838 | ), |
| 839 | GNB_ENTRY_STALL (1), |
| 840 | GNB_ENTRY_WR ( |
| 841 | D0F0xBC_xE03000E4_TYPE, |
| 842 | D0F0xBC_xE03000E4_ADDRESS, |
| 843 | 0 // control |
| 844 | ), |
| 845 | GNB_ENTRY_WR ( |
| 846 | D0F0xBC_xE03000E0_TYPE, |
| 847 | D0F0xBC_xE03000E0_ADDRESS, |
| 848 | (0xff << D0F0xBC_xE03000E0_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000E0_WriteOp_OFFSET) | |
| 849 | (1 << D0F0xBC_xE03000E0_RegAddr_OFFSET) |
| 850 | ), |
| 851 | GNB_ENTRY_STALL (1), |
| 852 | // Step 9 |
| 853 | GNB_ENTRY_WR ( |
| 854 | D0F0xBC_xE0300100_TYPE, |
| 855 | D0F0xBC_xE0300100_ADDRESS, |
| 856 | (5 << 16 ) | (4 << 8 ) | |
| 857 | (10 << 0 ) //reg0 |
| 858 | ), |
| 859 | GNB_ENTRY_WR ( |
| 860 | D0F0xBC_xE03000FC_TYPE, |
| 861 | D0F0xBC_xE03000FC_ADDRESS, |
| 862 | (0xff << D0F0xBC_xE03000FC_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000FC_WriteOp_OFFSET) | |
| 863 | (2 << D0F0xBC_xE03000FC_RegAddr_OFFSET) |
| 864 | ), |
| 865 | GNB_ENTRY_STALL (1), |
| 866 | GNB_ENTRY_WR ( |
| 867 | D0F0xBC_xE0300100_TYPE, |
| 868 | D0F0xBC_xE0300100_ADDRESS, |
| 869 | (50 << 0 ) | (50 << 12 ) //reg1 |
| 870 | ), |
| 871 | GNB_ENTRY_WR ( |
| 872 | D0F0xBC_xE03000FC_TYPE, |
| 873 | D0F0xBC_xE03000FC_ADDRESS, |
| 874 | (0xff << D0F0xBC_xE03000FC_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000FC_WriteOp_OFFSET) | |
| 875 | (3 << D0F0xBC_xE03000FC_RegAddr_OFFSET) |
| 876 | ), |
| 877 | GNB_ENTRY_STALL (1), |
| 878 | GNB_ENTRY_WR ( |
| 879 | D0F0xBC_xE0300100_TYPE, |
| 880 | D0F0xBC_xE0300100_ADDRESS, |
| 881 | 0 // control |
| 882 | ), |
| 883 | GNB_ENTRY_WR ( |
| 884 | D0F0xBC_xE03000FC_TYPE, |
| 885 | D0F0xBC_xE03000FC_ADDRESS, |
| 886 | (0xff << D0F0xBC_xE03000FC_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000FC_WriteOp_OFFSET) | |
| 887 | (1 << D0F0xBC_xE03000FC_RegAddr_OFFSET) |
| 888 | ), |
| 889 | GNB_ENTRY_STALL (1), |
| 890 | // Step 10 |
| 891 | GNB_ENTRY_RMW ( |
| 892 | TYPE_D0F0xBC , |
| 893 | 0xe0300328 , |
| 894 | 0x1 | 0x2 | |
| 895 | 0x4 | 0x8 | |
| 896 | 0x10 | 0x20 | |
| 897 | 0x40 , |
| 898 | 0x0 |
| 899 | ), |
| 900 | // Step 12 |
| 901 | GNB_ENTRY_RMW ( |
| 902 | D0F0xBC_xE0003024_TYPE, |
| 903 | D0F0xBC_xE0003024_ADDRESS, |
| 904 | 0x1, |
| 905 | 0x0 |
| 906 | ), |
| 907 | // Shutdown Gfx if integrated GFX disabled |
| 908 | // Step 2 |
| 909 | GNB_ENTRY_PROPERTY_RMW ( |
| 910 | TABLE_PROPERTY_IGFX_DISABLED, |
| 911 | D0F0xBC_xE0003024_TYPE, |
| 912 | D0F0xBC_xE0003024_ADDRESS, |
| 913 | 0x1, |
| 914 | 0x1 |
| 915 | ), |
| 916 | // Step 3: Save current SCLK. Make sure SCLK frequency is below 400Mhz |
| 917 | // Step 5 |
| 918 | GNB_ENTRY_PROPERTY_RMW ( |
| 919 | TABLE_PROPERTY_IGFX_DISABLED, |
| 920 | TYPE_D0F0xBC , |
| 921 | 0xe0300328 , |
| 922 | 0x1 | 0x2 | |
| 923 | 0x4 | 0x8 | |
| 924 | 0x10 | 0x20 | |
| 925 | 0x40 , |
| 926 | (1 << 0 ) | (1 << 1 ) | |
| 927 | (1 << 2 ) | (1 << 3 ) | |
| 928 | (1 << 4 ) | (1 << 5 ) | |
| 929 | (1 << 6 ) |
| 930 | ), |
| 931 | // Step 6 |
| 932 | GNB_ENTRY_PROPERTY_WR ( |
| 933 | TABLE_PROPERTY_IGFX_DISABLED, |
| 934 | D0F0xBC_xE0300054_TYPE, |
| 935 | D0F0xBC_xE0300054_ADDRESS, |
| 936 | (0xff << D0F0xBC_xE0300054_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300054_PowerDown_OFFSET) | |
| 937 | (1 << D0F0xBC_xE0300054_P1Select_OFFSET) | (1 << D0F0xBC_xE0300054_P2Select_OFFSET) |
| 938 | ), |
| 939 | // Step 7 |
| 940 | GNB_ENTRY_PROPERTY_WR ( |
| 941 | TABLE_PROPERTY_IGFX_DISABLED, |
| 942 | D0F0xBC_xE0300070_TYPE, |
| 943 | D0F0xBC_xE0300070_ADDRESS, |
| 944 | (0xff << D0F0xBC_xE0300070_FsmAddr_OFFSET) | (1 << D0F0xBC_xE0300070_PowerDown_OFFSET) | |
| 945 | (1 << D0F0xBC_xE0300070_P1Select_OFFSET) | (1 << D0F0xBC_xE0300070_P2Select_OFFSET) |
| 946 | ), |
| 947 | // Step 8 |
| 948 | GNB_ENTRY_PROPERTY_WR ( |
| 949 | TABLE_PROPERTY_IGFX_DISABLED, |
| 950 | D0F0xBC_xE030008C_TYPE, |
| 951 | D0F0xBC_xE030008C_ADDRESS, |
| 952 | (0xff << D0F0xBC_xE030008C_FsmAddr_OFFSET) | (1 << D0F0xBC_xE030008C_PowerDown_OFFSET) | |
| 953 | (1 << D0F0xBC_xE030008C_P1Select_OFFSET) | (1 << D0F0xBC_xE030008C_P2Select_OFFSET) |
| 954 | ), |
| 955 | // Step 9 |
| 956 | GNB_ENTRY_PROPERTY_WR ( |
| 957 | TABLE_PROPERTY_IGFX_DISABLED, |
| 958 | D0F0xBC_xE03000A8_TYPE, |
| 959 | D0F0xBC_xE03000A8_ADDRESS, |
| 960 | (0xff << D0F0xBC_xE03000A8_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000A8_PowerDown_OFFSET) | |
| 961 | (1 << D0F0xBC_xE03000A8_P1Select_OFFSET) | (1 << D0F0xBC_xE03000A8_P2Select_OFFSET) |
| 962 | ), |
| 963 | // Step 10 |
| 964 | GNB_ENTRY_PROPERTY_WR ( |
| 965 | TABLE_PROPERTY_IGFX_DISABLED, |
| 966 | D0F0xBC_xE03000C4_TYPE, |
| 967 | D0F0xBC_xE03000C4_ADDRESS, |
| 968 | (0xff << D0F0xBC_xE03000C4_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000C4_PowerDown_OFFSET) | |
| 969 | (1 << D0F0xBC_xE03000C4_P1Select_OFFSET) | (1 << D0F0xBC_xE03000C4_P2Select_OFFSET) |
| 970 | ), |
| 971 | // Step 11 |
| 972 | GNB_ENTRY_PROPERTY_WR ( |
| 973 | TABLE_PROPERTY_IGFX_DISABLED, |
| 974 | D0F0xBC_xE03000E0_TYPE, |
| 975 | D0F0xBC_xE03000E0_ADDRESS, |
| 976 | (0xff << D0F0xBC_xE03000E0_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000E0_PowerDown_OFFSET) | |
| 977 | (1 << D0F0xBC_xE03000E0_P1Select_OFFSET) | (1 << D0F0xBC_xE03000E0_P2Select_OFFSET) |
| 978 | ), |
| 979 | // Step 12 |
| 980 | GNB_ENTRY_PROPERTY_WR ( |
| 981 | TABLE_PROPERTY_IGFX_DISABLED, |
| 982 | D0F0xBC_xE03000FC_TYPE, |
| 983 | D0F0xBC_xE03000FC_ADDRESS, |
| 984 | (0xff << D0F0xBC_xE03000FC_FsmAddr_OFFSET) | (1 << D0F0xBC_xE03000FC_PowerDown_OFFSET) | |
| 985 | (1 << D0F0xBC_xE03000FC_P1Select_OFFSET) | (1 << D0F0xBC_xE03000FC_P2Select_OFFSET) |
| 986 | ), |
| 987 | // Step 13 |
| 988 | GNB_ENTRY_PROPERTY_POLL ( |
| 989 | TABLE_PROPERTY_IGFX_DISABLED, |
| 990 | D0F0xBC_xE03002F4_TYPE, |
| 991 | D0F0xBC_xE03002F4_ADDRESS, |
| 992 | 0xFFFFFFFF, |
| 993 | 0 |
| 994 | ), |
| 995 | // Step 14 |
| 996 | GNB_ENTRY_PROPERTY_POLL ( |
| 997 | TABLE_PROPERTY_IGFX_DISABLED, |
| 998 | D0F0xBC_xE03002F0_TYPE, |
| 999 | D0F0xBC_xE03002F0_ADDRESS, |
| 1000 | 0xFFFFFFFF, |
| 1001 | 0 |
| 1002 | ), |
| 1003 | // Step 15: Restore SCLK that is saved in step 4 |
| 1004 | // Step 16 |
| 1005 | GNB_ENTRY_FULL_POLL ( |
| 1006 | TABLE_PROPERTY_IGFX_DISABLED, |
| 1007 | (AMD_F15_TN_ALL & 0x0000000000000100ull) /* AMD_F15_TN_GT_A0 */, |
| 1008 | D0F0xBC_xE03002FC_TYPE, |
| 1009 | D0F0xBC_xE03002FC_ADDRESS, |
| 1010 | 0xFFFFFFFF, |
| 1011 | 0x3FFFFFFF |
| 1012 | ), |
| 1013 | // Step 17 |
| 1014 | GNB_ENTRY_FULL_POLL ( |
| 1015 | TABLE_PROPERTY_IGFX_DISABLED, |
| 1016 | (AMD_F15_TN_ALL & 0x0000000000000100ull) /* AMD_F15_TN_GT_A0 */, |
| 1017 | D0F0xBC_xE03002E4_TYPE, |
| 1018 | D0F0xBC_xE03002E4_ADDRESS, |
| 1019 | 0xFFFFFFFF, |
| 1020 | 0x3FFFF |
| 1021 | ), |
| 1022 | // Step 18 |
| 1023 | GNB_ENTRY_PROPERTY_RMW ( |
| 1024 | TABLE_PROPERTY_IGFX_DISABLED, |
| 1025 | TYPE_D0F0xBC , |
| 1026 | 0xe0300328 , |
| 1027 | 0x1 | 0x2 | |
| 1028 | 0x4 | 0x8 | |
| 1029 | 0x10 | 0x20 | |
| 1030 | 0x40 , |
| 1031 | 0 |
| 1032 | ), |
| 1033 | // Step 19 |
| 1034 | GNB_ENTRY_PROPERTY_RMW ( |
| 1035 | TABLE_PROPERTY_IGFX_DISABLED, |
| 1036 | D0F0xBC_xE0003024_TYPE, |
| 1037 | D0F0xBC_xE0003024_ADDRESS, |
| 1038 | 0x1, |
| 1039 | 0x0 |
| 1040 | ), |
| 1041 | //--------------------------------------------------------------------------- |
| 1042 | // Isolate DC, SYS and CP tile when Internal Graphics is disabled |
| 1043 | // Step 2: Reduce SCLK frequency to 100Mhz. Save current SCLK divider. |
| 1044 | // Step 3 |
| 1045 | GNB_ENTRY_PROPERTY_RMW ( |
| 1046 | TABLE_PROPERTY_IGFX_DISABLED, |
| 1047 | D0F0xBC_xE0003034_TYPE, |
| 1048 | D0F0xBC_xE0003034_ADDRESS, |
| 1049 | D0F0xBC_xE0003034_SysIso_MASK | D0F0xBC_xE0003034_CpIso_MASK | |
| 1050 | D0F0xBC_xE0003034_Dc0Iso_MASK | D0F0xBC_xE0003034_Dc1Iso_MASK | |
| 1051 | D0F0xBC_xE0003034_DciIso_MASK | D0F0xBC_xE0003034_DcipgIso_MASK, |
| 1052 | (1 << D0F0xBC_xE0003034_SysIso_OFFSET) | (1 << D0F0xBC_xE0003034_CpIso_OFFSET) | |
| 1053 | (1 << D0F0xBC_xE0003034_Dc0Iso_OFFSET) | (1 << D0F0xBC_xE0003034_Dc1Iso_OFFSET) | |
| 1054 | (1 << D0F0xBC_xE0003034_DciIso_OFFSET) | (1 << D0F0xBC_xE0003034_DcipgIso_OFFSET) |
| 1055 | ), |
| 1056 | //Step 4: Restore pervious SCLK frequency |
| 1057 | |
| 1058 | //--------------------------------------------------------------------------- |
| 1059 | // For IOMMU add logic of GfxDis |
| 1060 | GNB_ENTRY_PROPERTY_RMW ( |
| 1061 | TABLE_PROPERTY_IGFX_DISABLED, |
| 1062 | D0F2xF4_x57_TYPE, |
| 1063 | D0F2xF4_x57_ADDRESS, |
| 1064 | D0F2xF4_x57_L1ImuIntGfxDis_MASK, |
| 1065 | (0x1 << D0F2xF4_x57_L1ImuIntGfxDis_OFFSET) |
| 1066 | ), |
| 1067 | |
| 1068 | GNB_ENTRY_TERMINATE |
| 1069 | }; |