zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * Service procedure to initialize Power Play Table |
| 6 | * |
| 7 | * |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: GNB |
| 12 | * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ |
| 13 | * |
| 14 | */ |
| 15 | /* |
| 16 | ***************************************************************************** |
| 17 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 18 | * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. |
| 19 | * All rights reserved. |
| 20 | * |
| 21 | * Redistribution and use in source and binary forms, with or without |
| 22 | * modification, are permitted provided that the following conditions are met: |
| 23 | * * Redistributions of source code must retain the above copyright |
| 24 | * notice, this list of conditions and the following disclaimer. |
| 25 | * * Redistributions in binary form must reproduce the above copyright |
| 26 | * notice, this list of conditions and the following disclaimer in the |
| 27 | * documentation and/or other materials provided with the distribution. |
| 28 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 29 | * its contributors may be used to endorse or promote products derived |
| 30 | * from this software without specific prior written permission. |
| 31 | * |
| 32 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 33 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 34 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 35 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 36 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 37 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 38 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 39 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 40 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 41 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 42 | * *************************************************************************** |
| 43 | * |
| 44 | */ |
| 45 | #ifndef _GFXPOWERPLAYTABLE_H_ |
| 46 | #define _GFXPOWERPLAYTABLE_H_ |
| 47 | |
| 48 | #pragma pack (push, 1) |
| 49 | |
| 50 | #define POLICY_LABEL_BATTERY 0x1 |
| 51 | #define POLICY_LABEL_PERFORMANCE 0x2 |
| 52 | |
| 53 | #define MAX_NUM_OF_SW_STATES 10 |
| 54 | #define MAX_NUM_OF_DPM_STATES 10 |
| 55 | #define MAX_NUM_OF_VCE_CLK_STATES 5 |
| 56 | #define MAX_NUM_OF_VCE_STATES 6 |
| 57 | #define MAX_NUM_OF_FUSED_DPM_STATES 5 |
| 58 | #define MAX_NUM_OF_FUSED_SW_STATES 6 |
| 59 | /// ATOM_PPLIB_POWERPLAYTABLE::ulPlatformCaps |
| 60 | #define ATOM_PP_PLATFORM_CAP_BACKBIAS 1 |
| 61 | #define ATOM_PP_PLATFORM_CAP_POWERPLAY 2 |
| 62 | #define ATOM_PP_PLATFORM_CAP_SBIOSPOWERSOURCE 4 |
| 63 | #define ATOM_PP_PLATFORM_CAP_ASPM_L0s 8 |
| 64 | #define ATOM_PP_PLATFORM_CAP_ASPM_L1 16 |
| 65 | #define ATOM_PP_PLATFORM_CAP_HARDWAREDC 32 |
| 66 | #define ATOM_PP_PLATFORM_CAP_GEMINIPRIMARY 64 |
| 67 | #define ATOM_PP_PLATFORM_CAP_STEPVDDC 128 |
| 68 | #define ATOM_PP_PLATFORM_CAP_VOLTAGECONTROL 256 |
| 69 | #define ATOM_PP_PLATFORM_CAP_SIDEPORTCONTROL 512 |
| 70 | #define ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1 1024 |
| 71 | #define ATOM_PP_PLATFORM_CAP_HTLINKCONTROL 2048 |
| 72 | #define ATOM_PP_PLATFORM_CAP_MVDDCONTROL 4096 |
| 73 | #define ATOM_PP_PLATFORM_CAP_GOTO_BOOT_ON_ALERT 0x2000 // Go to boot state on alerts, e.g. on an AC->DC transition. |
| 74 | #define ATOM_PP_PLATFORM_CAP_DONT_WAIT_FOR_VBLANK_ON_ALERT 0x4000 // Do NOT wait for VBLANK during an alert (e.g. AC->DC transition). |
| 75 | #define ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL 0x8000 // Does |
| 76 | #define ATOM_PP_PLATFORM_CAP_REGULATOR_HOT 0x00010000ul // Enable the 'regulator hot' feature. |
| 77 | #define ATOM_PP_PLATFORM_CAP_BACO 0x00020000ul // Does the driver supports BACO state. |
| 78 | |
| 79 | |
| 80 | #define ATOM_PPLIB_CLASSIFICATION_UI_BATTERY 1 |
| 81 | #define ATOM_PPLIB_CLASSIFICATION_UI_BALANCED 3 |
| 82 | #define ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE 5 |
| 83 | |
| 84 | #define ATOM_PPLIB_CLASSIFICATION_BOOT 0x0008 |
| 85 | #define ATOM_PPLIB_CLASSIFICATION_THERMAL 0x0010 |
| 86 | #define ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE 0x0020 |
| 87 | #define ATOM_PPLIB_CLASSIFICATION_REST 0x0040 |
| 88 | #define ATOM_PPLIB_CLASSIFICATION_FORCED 0x0080 |
| 89 | #define ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE 0x0100 |
| 90 | #define ATOM_PPLIB_CLASSIFICATION_OVERDRIVETEMPLATE 0x0200 |
| 91 | #define ATOM_PPLIB_CLASSIFICATION_UVDSTATE 0x0400 |
| 92 | #define ATOM_PPLIB_CLASSIFICATION_3DLOW 0x0800 |
| 93 | #define ATOM_PPLIB_CLASSIFICATION_ACPI 0x1000 |
| 94 | #define ATOM_PPLIB_CLASSIFICATION_HD2STATE 0x2000 |
| 95 | #define ATOM_PPLIB_CLASSIFICATION_HDSTATE 0x4000 |
| 96 | #define ATOM_PPLIB_CLASSIFICATION_SDSTATE 0x8000 |
| 97 | #define ATOM_PPLIB_CLASSIFICATION_NONUVDSTATE 0x0000 |
| 98 | |
| 99 | #define ATOM_PPLIB_CLASSIFICATION2_MVC 0x0004 //Multi-View |
| 100 | |
| 101 | #define ATOM_PPLIB_ENABLE_VARIBRIGHT 0x00008000ul |
| 102 | #define ATOM_PPLIB_ENABLE_DRR 0x00080000ul |
| 103 | |
| 104 | #define ATOM_PP_FANPARAMETERS_NOFAN 0x80 |
| 105 | #define ATOM_PP_THERMALCONTROLLER_SUMO 0x0E |
| 106 | |
| 107 | /// DPM state info |
| 108 | typedef struct _ATOM_PPLIB_SUMO_CLOCK_INFO { |
| 109 | USHORT usEngineClockLow; ///< Sclk [15:0] (Sclk in 10khz) |
| 110 | UCHAR ucEngineClockHigh; ///< Sclk [23:16](Sclk in 10khz) |
| 111 | UCHAR vddcIndex; ///< 2-bit VDDC index; |
| 112 | USHORT tdpLimit; ///< TDP Limit |
| 113 | USHORT rsv1; ///< Reserved |
| 114 | ULONG rsv2[2]; ///< Reserved |
| 115 | } ATOM_PPLIB_SUMO_CLOCK_INFO; |
| 116 | |
| 117 | /// Non clock info |
| 118 | typedef struct _ATOM_PPLIB_NONCLOCK_INFO { |
| 119 | USHORT usClassification; ///< State classification see ATOM_PPLIB_CLASSIFICATION_* |
| 120 | UCHAR ucMinTemperature; ///< Reserved |
| 121 | UCHAR ucMaxTemperature; ///< Reserved |
| 122 | ULONG ulCapsAndSettings; ///< Capability Setting (ATOM_PPLIB_ENABLE_DRR or ATOM_PPLIB_ENABLE_VARIBRIGHT or 0) |
| 123 | UCHAR ucRequiredPower; ///< Reserved |
| 124 | USHORT usClassification2; ///< Reserved |
| 125 | ULONG ulVCLK; ///< UVD clocks VCLK unit is in 10KHz |
| 126 | ULONG ulDCLK; ///< UVD clocks DCLK unit is in 10KHz |
| 127 | UCHAR ucUnused[5]; ///< Reserved |
| 128 | } ATOM_PPLIB_NONCLOCK_INFO; |
| 129 | |
| 130 | /// Thermal controller info stub |
| 131 | typedef struct _ATOM_PPLIB_THERMALCONTROLLER { |
| 132 | UCHAR ucType; ///< Reserved. Should be set 0xE |
| 133 | UCHAR ucI2cLine; ///< Reserved. Should be set 0 |
| 134 | UCHAR ucI2cAddress; ///< Reserved. Should be set 0 |
| 135 | UCHAR ucFanParameters; ///< Reserved. Should be set 0x80 |
| 136 | UCHAR ucFanMinRPM; ///< Reserved. Should be set 0 |
| 137 | UCHAR ucFanMaxRPM; ///< Reserved. Should be set 0 |
| 138 | UCHAR ucReserved; ///< Reserved. Should be set 0 |
| 139 | UCHAR ucFlags; ///< Reserved. Should be set 0 |
| 140 | } ATOM_PPLIB_THERMALCONTROLLER; |
| 141 | |
| 142 | /// SW state info |
| 143 | typedef struct _ATOM_PPLIB_STATE_V2 { |
| 144 | UCHAR ucNumDPMLevels; ///< Number of valid DPM levels in this state |
| 145 | UCHAR nonClockInfoIndex; ///< Index to the array of NonClockInfos |
| 146 | UCHAR ClockInfoIndex[1]; ///< Array of DPM states. Actual number calculated during state enumeration |
| 147 | } ATOM_PPLIB_STATE_V2; |
| 148 | |
| 149 | /// SW state Array |
| 150 | typedef struct { |
| 151 | UCHAR ucNumEntries; ///< Number of SW states |
| 152 | ATOM_PPLIB_STATE_V2 States[1]; ///< SW state info. Actual number calculated during state enumeration |
| 153 | } STATE_ARRAY; |
| 154 | |
| 155 | /// Clock info Array |
| 156 | typedef struct { |
| 157 | UCHAR ucNumEntries; ///< Number of ClockInfo entries |
| 158 | UCHAR ucEntrySize; ///< size of ATOM_PPLIB_SUMO_CLOCK_INFO |
| 159 | ATOM_PPLIB_SUMO_CLOCK_INFO ClockInfo[1]; ///< Clock info array. Size will be determined dynamically base on fuses |
| 160 | } CLOCK_INFO_ARRAY; |
| 161 | |
| 162 | /// Non clock info Array |
| 163 | typedef struct { |
| 164 | |
| 165 | UCHAR ucNumEntries; ///< Number of Entries; |
| 166 | UCHAR ucEntrySize; ///< Size of NonClockInfo |
| 167 | ATOM_PPLIB_NONCLOCK_INFO NonClockInfo[1]; ///< Non clock info array |
| 168 | } NON_CLOCK_INFO_ARRAY; |
| 169 | |
| 170 | /// VCE clock info |
| 171 | typedef struct { |
| 172 | USHORT usEVClkLow; ///< EVCLK low |
| 173 | UCHAR ucEVClkHigh; ///< EVCLK high |
| 174 | USHORT usECClkLow; ///< ECCLK low |
| 175 | UCHAR ucECClkHigh; ///< ECCLK high |
| 176 | } VCECLOCKINFO; |
| 177 | |
| 178 | /// VCE clock info array |
| 179 | typedef struct { |
| 180 | UCHAR ucNumEntries; ///< Number of entries |
| 181 | VCECLOCKINFO entries[1]; ///< VCE clock arrau |
| 182 | } VCECLOCKINFOARRAY; |
| 183 | |
| 184 | /// VCE voltage limit record |
| 185 | typedef struct { |
| 186 | USHORT usVoltage; ///< Voltage index |
| 187 | UCHAR ucVCEClockInfoIndex; ///< Index of VCE clock state |
| 188 | } ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_RECORD; |
| 189 | |
| 190 | /// VCE voltage limit table |
| 191 | typedef struct { |
| 192 | UCHAR numEntries; ///< Number of entries |
| 193 | ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_RECORD entries[1]; ///< Coltage limit state array |
| 194 | } ATOM_PPLIB_VCE_CLOCK_VOLTAGE_LIMIT_TABLE; |
| 195 | |
| 196 | /// VCE state record |
| 197 | typedef struct { |
| 198 | UCHAR ucVCEClockInfoIndex; ///< Index of VCE clock state |
| 199 | UCHAR ucClockInfoIndex; ///< Index of SCLK clock state |
| 200 | } ATOM_PPLIB_VCE_STATE_RECORD; |
| 201 | |
| 202 | /// VCE state table |
| 203 | typedef struct { |
| 204 | UCHAR numEntries; ///< Number of state entries |
| 205 | ATOM_PPLIB_VCE_STATE_RECORD entries[1]; ///< State entries |
| 206 | } ATOM_PPLIB_VCE_STATE_TABLE; |
| 207 | |
| 208 | /// Extended header |
| 209 | typedef struct { |
| 210 | USHORT usSize; ///< size of header |
| 211 | ULONG rsv15; ///< reserved |
| 212 | ULONG rsv16; ///< reserved |
| 213 | USHORT usVCETableOffset; ///< offset of ATOM_PPLIB_VCE_TABLE |
| 214 | } ATOM_PPLIB_EXTENDEDHEADER; |
| 215 | |
| 216 | /// VCE table |
| 217 | typedef struct { |
| 218 | UCHAR revid; ///< revision ID |
| 219 | } ATOM_PPLIB_VCE_TABLE; |
| 220 | |
| 221 | /// Power Play table |
| 222 | typedef struct _ATOM_PPLIB_POWERPLAYTABLE3 { |
| 223 | ATOM_COMMON_TABLE_HEADER sHeader; ///< Common header |
| 224 | UCHAR ucDataRevision; ///< Revision of PP table |
| 225 | UCHAR Reserved1[4]; ///< Reserved |
| 226 | USHORT usStateArrayOffset; ///< Offset from start of this table to array of ucNumStates ATOM_PPLIB_STATE structures |
| 227 | USHORT usClockInfoArrayOffset; ///< Offset from start of the table to ClockInfoArray |
| 228 | USHORT usNonClockInfoArrayOffset; ///< Offset from Start of the table to NonClockInfoArray |
| 229 | USHORT Reserved2[2]; ///< Reserved |
| 230 | USHORT usTableSize; ///< the size of this structure, or the extended structure |
| 231 | ULONG ulPlatformCaps; ///< See ATOM_PPLIB_CAPS_* |
| 232 | ATOM_PPLIB_THERMALCONTROLLER sThermalController; ///< Thermal controller stub. |
| 233 | USHORT Reserved4[2]; ///< Reserved |
| 234 | UCHAR Reserved5; ///< Reserved |
| 235 | USHORT Reserved6; ///< Reserved |
| 236 | USHORT usFormatID; ///< Format ID |
| 237 | USHORT Reserved7[1]; ///< Reserved |
| 238 | USHORT usExtendendedHeaderOffset; ///< Extended header offset |
| 239 | } ATOM_PPLIB_POWERPLAYTABLE3; |
| 240 | |
| 241 | #pragma pack (pop) |
| 242 | |
| 243 | |
| 244 | AGESA_STATUS |
| 245 | GfxPowerPlayBuildTable ( |
| 246 | OUT VOID *Buffer, |
| 247 | IN GFX_PLATFORM_CONFIG *Gfx |
| 248 | ); |
| 249 | |
| 250 | |
| 251 | #endif |