zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * Various PCI service routines. |
| 6 | * |
| 7 | * |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: GNB |
| 12 | * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ |
| 13 | * |
| 14 | */ |
| 15 | /* |
| 16 | ***************************************************************************** |
| 17 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 18 | * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. |
| 19 | * All rights reserved. |
| 20 | * |
| 21 | * Redistribution and use in source and binary forms, with or without |
| 22 | * modification, are permitted provided that the following conditions are met: |
| 23 | * * Redistributions of source code must retain the above copyright |
| 24 | * notice, this list of conditions and the following disclaimer. |
| 25 | * * Redistributions in binary form must reproduce the above copyright |
| 26 | * notice, this list of conditions and the following disclaimer in the |
| 27 | * documentation and/or other materials provided with the distribution. |
| 28 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 29 | * its contributors may be used to endorse or promote products derived |
| 30 | * from this software without specific prior written permission. |
| 31 | * |
| 32 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 33 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 34 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 35 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 36 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 37 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 38 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 39 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 40 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 41 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 42 | * *************************************************************************** |
| 43 | * |
| 44 | */ |
| 45 | |
| 46 | #ifndef _GNBLIBPCI_H_ |
| 47 | #define _GNBLIBPCI_H_ |
| 48 | |
| 49 | #define PCIE_CAP_ID 0x10 |
| 50 | #define IOMMU_CAP_ID 0x0F |
| 51 | |
| 52 | /// PCIe device type |
| 53 | typedef enum { |
| 54 | PcieDeviceEndPoint, ///< Endpoint |
| 55 | PcieDeviceLegacyEndPoint, ///< Legacy endpoint |
| 56 | PcieDeviceRootComplex = 4, ///< Root complex |
| 57 | PcieDeviceUpstreamPort, ///< Upstream port |
| 58 | PcieDeviceDownstreamPort, ///< Downstream Port |
| 59 | PcieDevicePcieToPcix, ///< PCIe to PCI/PCIx bridge |
| 60 | PcieDevicePcixToPcie, ///< PCI/PCIx to PCIe bridge |
| 61 | PcieNotPcieDevice = 0xff ///< unknown device |
| 62 | } PCIE_DEVICE_TYPE; |
| 63 | |
| 64 | typedef UINT32 SCAN_STATUS; |
| 65 | |
| 66 | #define SCAN_SKIP_FUNCTIONS 0x1 |
| 67 | #define SCAN_SKIP_DEVICES 0x2 |
| 68 | #define SCAN_SKIP_BUSES 0x4 |
| 69 | #define SCAN_SUCCESS 0x0 |
| 70 | |
| 71 | // Forward declaration needed for multi-structure mutual references |
| 72 | AGESA_FORWARD_DECLARATION (GNB_PCI_SCAN_DATA); |
| 73 | |
| 74 | typedef SCAN_STATUS (*GNB_SCAN_CALLBACK) ( |
| 75 | IN PCI_ADDR Device, |
| 76 | IN OUT GNB_PCI_SCAN_DATA *ScanData |
| 77 | ); |
| 78 | |
| 79 | ///Scan supporting data |
| 80 | struct _GNB_PCI_SCAN_DATA { |
| 81 | GNB_SCAN_CALLBACK GnbScanCallback; ///< Callback for each found device |
| 82 | AMD_CONFIG_PARAMS *StdHeader; ///< Standard configuration header |
| 83 | }; |
| 84 | |
| 85 | #define PCIE_CAP_ID 0x10 |
| 86 | #define PCIE_LINK_CAP_REGISTER 0x0C |
| 87 | #define PCIE_LINK_CTRL_REGISTER 0x10 |
| 88 | #define PCIE_DEVICE_CAP_REGISTER 0x04 |
| 89 | #define PCIE_DEVICE_CTRL_REGISTER 0x08 |
| 90 | #define PCIE_ASPM_L1_SUPPORT_CAP BIT11 |
| 91 | |
| 92 | #define MAX_PAYLOAD_128 0x0 ///< Max allowed payload size 128 bytes |
| 93 | #define MAX_PAYLOAD_256 0x1 ///< Max allowed payload size 256 bytes |
| 94 | #define MAX_PAYLOAD_512 0x2 ///< Max allowed payload size 512 bytes |
| 95 | #define MAX_PAYLOAD_1024 0x3 ///< Max allowed payload size 1024 bytes |
| 96 | #define MAX_PAYLOAD_2048 0x4 ///< Max allowed payload size 2048 bytes |
| 97 | #define MAX_PAYLOAD_4096 0x5 ///< Max allowed payload size 4096 bytes |
| 98 | #define MAX_PAYLOAD 0x5 ///< Max allowed payload size according to spec is 101b (4096 bytes) |
| 99 | |
| 100 | BOOLEAN |
| 101 | GnbLibPciIsDevicePresent ( |
| 102 | IN UINT32 Address, |
| 103 | IN AMD_CONFIG_PARAMS *StdHeader |
| 104 | ); |
| 105 | |
| 106 | BOOLEAN |
| 107 | GnbLibPciIsBridgeDevice ( |
| 108 | IN UINT32 Address, |
| 109 | IN AMD_CONFIG_PARAMS *StdHeader |
| 110 | ); |
| 111 | |
| 112 | BOOLEAN |
| 113 | GnbLibPciIsMultiFunctionDevice ( |
| 114 | IN UINT32 Address, |
| 115 | IN AMD_CONFIG_PARAMS *StdHeader |
| 116 | ); |
| 117 | |
| 118 | BOOLEAN |
| 119 | GnbLibPciIsPcieDevice ( |
| 120 | IN UINT32 Address, |
| 121 | IN AMD_CONFIG_PARAMS *StdHeader |
| 122 | ); |
| 123 | |
| 124 | UINT8 |
| 125 | GnbLibFindPciCapability ( |
| 126 | IN UINT32 Address, |
| 127 | IN UINT8 CapabilityId, |
| 128 | IN AMD_CONFIG_PARAMS *StdHeader |
| 129 | ); |
| 130 | |
| 131 | VOID |
| 132 | GnbLibPciScan ( |
| 133 | IN PCI_ADDR Start, |
| 134 | IN PCI_ADDR End, |
| 135 | IN GNB_PCI_SCAN_DATA *ScanData |
| 136 | ); |
| 137 | |
| 138 | VOID |
| 139 | GnbLibPciScanSecondaryBus ( |
| 140 | IN PCI_ADDR Bridge, |
| 141 | IN OUT GNB_PCI_SCAN_DATA *ScanData |
| 142 | ); |
| 143 | |
| 144 | PCIE_DEVICE_TYPE |
| 145 | GnbLibGetPcieDeviceType ( |
| 146 | IN PCI_ADDR Device, |
| 147 | IN AMD_CONFIG_PARAMS *StdHeader |
| 148 | ); |
| 149 | |
| 150 | VOID |
| 151 | GnbLibS3SaveConfigSpace ( |
| 152 | IN UINT32 Address, |
| 153 | IN UINT16 StartRegisterAddress, |
| 154 | IN UINT16 EndRegisterAddress, |
| 155 | IN ACCESS_WIDTH Width, |
| 156 | IN AMD_CONFIG_PARAMS *StdHeader |
| 157 | ); |
| 158 | |
| 159 | #endif |