| zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * Register definitions |
| 6 | * |
| 7 | * |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: GNB |
| 12 | * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ |
| 13 | * |
| 14 | */ |
| 15 | /* |
| 16 | ***************************************************************************** |
| 17 | * |
| Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 18 | * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. |
| 19 | * All rights reserved. |
| 20 | * |
| 21 | * Redistribution and use in source and binary forms, with or without |
| 22 | * modification, are permitted provided that the following conditions are met: |
| 23 | * * Redistributions of source code must retain the above copyright |
| 24 | * notice, this list of conditions and the following disclaimer. |
| 25 | * * Redistributions in binary form must reproduce the above copyright |
| 26 | * notice, this list of conditions and the following disclaimer in the |
| 27 | * documentation and/or other materials provided with the distribution. |
| 28 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 29 | * its contributors may be used to endorse or promote products derived |
| 30 | * from this software without specific prior written permission. |
| 31 | * |
| 32 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 33 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 34 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 35 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 36 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 37 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 38 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 39 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 40 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 41 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 42 | * *************************************************************************** |
| 43 | * |
| 44 | */ |
| 45 | |
| 46 | #ifndef _GNBREGISTERSLN_H_ |
| 47 | #define _GNBREGISTERSLN_H_ |
| 48 | #define TYPE_D0F0 0x1 |
| 49 | #define TYPE_D0F0x64 0x2 |
| 50 | #define TYPE_D0F0x98 0x3 |
| 51 | #define TYPE_D0F0xE4 0x5 |
| 52 | #define TYPE_DxF0 0x6 |
| 53 | #define TYPE_DxF0xE4 0x7 |
| 54 | #define TYPE_D18F1 0xb |
| 55 | #define TYPE_D18F2 0xc |
| 56 | #define TYPE_D18F3 0xd |
| 57 | #define TYPE_MSR 0x10 |
| 58 | #define TYPE_D1F0 0x11 |
| 59 | #define TYPE_GMM 0x12 |
| 60 | #define D18F2x9C 0xe |
| 61 | #define GMM 0x11 |
| 62 | #ifndef WRAP_SPACE |
| 63 | #define WRAP_SPACE(w, x) (0x01300000 | (w << 16) | (x)) |
| 64 | #endif |
| 65 | #ifndef CORE_SPACE |
| 66 | #define CORE_SPACE(c, x) (0x00010000 | (c << 24) | (x)) |
| 67 | #endif |
| 68 | #ifndef PHY_SPACE |
| 69 | #define PHY_SPACE(w, p, x) (0x00200000 | ((p + 1) << 24) | (w << 16) | (x)) |
| 70 | #endif |
| 71 | #ifndef PIF_SPACE |
| 72 | #define PIF_SPACE(w, p, x) (0x00100000 | ((p + 1) << 24) | (w << 16) | (x)) |
| 73 | #endif |
| 74 | // **** D0F0x00 Register Definition **** |
| 75 | // Address |
| 76 | #define D0F0x00_ADDRESS 0x0 |
| 77 | |
| 78 | // Type |
| 79 | #define D0F0x00_TYPE TYPE_D0F0 |
| 80 | // Field Data |
| 81 | #define D0F0x00_VendorID_OFFSET 0 |
| 82 | #define D0F0x00_VendorID_WIDTH 16 |
| 83 | #define D0F0x00_VendorID_MASK 0xffff |
| 84 | #define D0F0x00_DeviceID_OFFSET 16 |
| 85 | #define D0F0x00_DeviceID_WIDTH 16 |
| 86 | #define D0F0x00_DeviceID_MASK 0xffff0000 |
| 87 | |
| 88 | /// D0F0x00 |
| 89 | typedef union { |
| 90 | struct { ///< |
| 91 | UINT32 VendorID:16; ///< |
| 92 | UINT32 DeviceID:16; ///< |
| 93 | } Field; ///< |
| 94 | UINT32 Value; ///< |
| 95 | } D0F0x00_STRUCT; |
| 96 | |
| 97 | // **** D0F0x04 Register Definition **** |
| 98 | // Address |
| 99 | #define D0F0x04_ADDRESS 0x4 |
| 100 | |
| 101 | // Type |
| 102 | #define D0F0x04_TYPE TYPE_D0F0 |
| 103 | // Field Data |
| 104 | #define D0F0x04_IoAccessEn_OFFSET 0 |
| 105 | #define D0F0x04_IoAccessEn_WIDTH 1 |
| 106 | #define D0F0x04_IoAccessEn_MASK 0x1 |
| 107 | #define D0F0x04_MemAccessEn_OFFSET 1 |
| 108 | #define D0F0x04_MemAccessEn_WIDTH 1 |
| 109 | #define D0F0x04_MemAccessEn_MASK 0x2 |
| 110 | #define D0F0x04_BusMasterEn_OFFSET 2 |
| 111 | #define D0F0x04_BusMasterEn_WIDTH 1 |
| 112 | #define D0F0x04_BusMasterEn_MASK 0x4 |
| 113 | #define D0F0x04_SpecialCycleEn_OFFSET 3 |
| 114 | #define D0F0x04_SpecialCycleEn_WIDTH 1 |
| 115 | #define D0F0x04_SpecialCycleEn_MASK 0x8 |
| 116 | #define D0F0x04_MemWriteInvalidateEn_OFFSET 4 |
| 117 | #define D0F0x04_MemWriteInvalidateEn_WIDTH 1 |
| 118 | #define D0F0x04_MemWriteInvalidateEn_MASK 0x10 |
| 119 | #define D0F0x04_PalSnoopEn_OFFSET 5 |
| 120 | #define D0F0x04_PalSnoopEn_WIDTH 1 |
| 121 | #define D0F0x04_PalSnoopEn_MASK 0x20 |
| 122 | #define D0F0x04_ParityErrorEn_OFFSET 6 |
| 123 | #define D0F0x04_ParityErrorEn_WIDTH 1 |
| 124 | #define D0F0x04_ParityErrorEn_MASK 0x40 |
| 125 | #define D0F0x04_Reserved_7_7_OFFSET 7 |
| 126 | #define D0F0x04_Reserved_7_7_WIDTH 1 |
| 127 | #define D0F0x04_Reserved_7_7_MASK 0x80 |
| 128 | #define D0F0x04_SerrEn_OFFSET 8 |
| 129 | #define D0F0x04_SerrEn_WIDTH 1 |
| 130 | #define D0F0x04_SerrEn_MASK 0x100 |
| 131 | #define D0F0x04_FastB2BEn_OFFSET 9 |
| 132 | #define D0F0x04_FastB2BEn_WIDTH 1 |
| 133 | #define D0F0x04_FastB2BEn_MASK 0x200 |
| 134 | #define D0F0x04_Reserved_19_10_OFFSET 10 |
| 135 | #define D0F0x04_Reserved_19_10_WIDTH 10 |
| 136 | #define D0F0x04_Reserved_19_10_MASK 0xffc00 |
| 137 | #define D0F0x04_CapList_OFFSET 20 |
| 138 | #define D0F0x04_CapList_WIDTH 1 |
| 139 | #define D0F0x04_CapList_MASK 0x100000 |
| 140 | #define D0F0x04_PCI66En_OFFSET 21 |
| 141 | #define D0F0x04_PCI66En_WIDTH 1 |
| 142 | #define D0F0x04_PCI66En_MASK 0x200000 |
| 143 | #define D0F0x04_Reserved_22_22_OFFSET 22 |
| 144 | #define D0F0x04_Reserved_22_22_WIDTH 1 |
| 145 | #define D0F0x04_Reserved_22_22_MASK 0x400000 |
| 146 | #define D0F0x04_FastBackCapable_OFFSET 23 |
| 147 | #define D0F0x04_FastBackCapable_WIDTH 1 |
| 148 | #define D0F0x04_FastBackCapable_MASK 0x800000 |
| 149 | #define D0F0x04_Reserved_24_24_OFFSET 24 |
| 150 | #define D0F0x04_Reserved_24_24_WIDTH 1 |
| 151 | #define D0F0x04_Reserved_24_24_MASK 0x1000000 |
| 152 | #define D0F0x04_DevselTiming_OFFSET 25 |
| 153 | #define D0F0x04_DevselTiming_WIDTH 2 |
| 154 | #define D0F0x04_DevselTiming_MASK 0x6000000 |
| 155 | #define D0F0x04_SignalTargetAbort_OFFSET 27 |
| 156 | #define D0F0x04_SignalTargetAbort_WIDTH 1 |
| 157 | #define D0F0x04_SignalTargetAbort_MASK 0x8000000 |
| 158 | #define D0F0x04_ReceivedTargetAbort_OFFSET 28 |
| 159 | #define D0F0x04_ReceivedTargetAbort_WIDTH 1 |
| 160 | #define D0F0x04_ReceivedTargetAbort_MASK 0x10000000 |
| 161 | #define D0F0x04_ReceivedMasterAbort_OFFSET 29 |
| 162 | #define D0F0x04_ReceivedMasterAbort_WIDTH 1 |
| 163 | #define D0F0x04_ReceivedMasterAbort_MASK 0x20000000 |
| 164 | #define D0F0x04_SignaledSystemError_OFFSET 30 |
| 165 | #define D0F0x04_SignaledSystemError_WIDTH 1 |
| 166 | #define D0F0x04_SignaledSystemError_MASK 0x40000000 |
| 167 | #define D0F0x04_ParityErrorDetected_OFFSET 31 |
| 168 | #define D0F0x04_ParityErrorDetected_WIDTH 1 |
| 169 | #define D0F0x04_ParityErrorDetected_MASK 0x80000000 |
| 170 | |
| 171 | /// D0F0x04 |
| 172 | typedef union { |
| 173 | struct { ///< |
| 174 | UINT32 IoAccessEn:1 ; ///< |
| 175 | UINT32 MemAccessEn:1 ; ///< |
| 176 | UINT32 BusMasterEn:1 ; ///< |
| 177 | UINT32 SpecialCycleEn:1 ; ///< |
| 178 | UINT32 MemWriteInvalidateEn:1 ; ///< |
| 179 | UINT32 PalSnoopEn:1 ; ///< |
| 180 | UINT32 ParityErrorEn:1 ; ///< |
| 181 | UINT32 Reserved_7_7:1 ; ///< |
| 182 | UINT32 SerrEn:1 ; ///< |
| 183 | UINT32 FastB2BEn:1 ; ///< |
| 184 | UINT32 Reserved_19_10:10; ///< |
| 185 | UINT32 CapList:1 ; ///< |
| 186 | UINT32 PCI66En:1 ; ///< |
| 187 | UINT32 Reserved_22_22:1 ; ///< |
| 188 | UINT32 FastBackCapable:1 ; ///< |
| 189 | UINT32 Reserved_24_24:1 ; ///< |
| 190 | UINT32 DevselTiming:2 ; ///< |
| 191 | UINT32 SignalTargetAbort:1 ; ///< |
| 192 | UINT32 ReceivedTargetAbort:1 ; ///< |
| 193 | UINT32 ReceivedMasterAbort:1 ; ///< |
| 194 | UINT32 SignaledSystemError:1 ; ///< |
| 195 | UINT32 ParityErrorDetected:1 ; ///< |
| 196 | } Field; ///< |
| 197 | UINT32 Value; ///< |
| 198 | } D0F0x04_STRUCT; |
| 199 | |
| 200 | // **** D0F0x08 Register Definition **** |
| 201 | // Address |
| 202 | #define D0F0x08_ADDRESS 0x8 |
| 203 | |
| 204 | // Type |
| 205 | #define D0F0x08_TYPE TYPE_D0F0 |
| 206 | // Field Data |
| 207 | #define D0F0x08_RevID_OFFSET 0 |
| 208 | #define D0F0x08_RevID_WIDTH 8 |
| 209 | #define D0F0x08_RevID_MASK 0xff |
| 210 | #define D0F0x08_ClassCode_OFFSET 8 |
| 211 | #define D0F0x08_ClassCode_WIDTH 24 |
| 212 | #define D0F0x08_ClassCode_MASK 0xffffff00 |
| 213 | |
| 214 | /// D0F0x08 |
| 215 | typedef union { |
| 216 | struct { ///< |
| 217 | UINT32 RevID:8 ; ///< |
| 218 | UINT32 ClassCode:24; ///< |
| 219 | } Field; ///< |
| 220 | UINT32 Value; ///< |
| 221 | } D0F0x08_STRUCT; |
| 222 | |
| 223 | // **** D0F0x0C Register Definition **** |
| 224 | // Address |
| 225 | #define D0F0x0C_ADDRESS 0xc |
| 226 | |
| 227 | // Type |
| 228 | #define D0F0x0C_TYPE TYPE_D0F0 |
| 229 | // Field Data |
| 230 | #define D0F0x0C_CacheLineSize_OFFSET 0 |
| 231 | #define D0F0x0C_CacheLineSize_WIDTH 8 |
| 232 | #define D0F0x0C_CacheLineSize_MASK 0xff |
| 233 | #define D0F0x0C_LatencyTimer_OFFSET 8 |
| 234 | #define D0F0x0C_LatencyTimer_WIDTH 8 |
| 235 | #define D0F0x0C_LatencyTimer_MASK 0xff00 |
| 236 | #define D0F0x0C_HeaderTypeReg_OFFSET 16 |
| 237 | #define D0F0x0C_HeaderTypeReg_WIDTH 8 |
| 238 | #define D0F0x0C_HeaderTypeReg_MASK 0xff0000 |
| 239 | #define D0F0x0C_BIST_OFFSET 24 |
| 240 | #define D0F0x0C_BIST_WIDTH 8 |
| 241 | #define D0F0x0C_BIST_MASK 0xff000000 |
| 242 | |
| 243 | /// D0F0x0C |
| 244 | typedef union { |
| 245 | struct { ///< |
| 246 | UINT32 CacheLineSize:8 ; ///< |
| 247 | UINT32 LatencyTimer:8 ; ///< |
| 248 | UINT32 HeaderTypeReg:8 ; ///< |
| 249 | UINT32 BIST:8 ; ///< |
| 250 | } Field; ///< |
| 251 | UINT32 Value; ///< |
| 252 | } D0F0x0C_STRUCT; |
| 253 | |
| 254 | // **** D0F0x2C Register Definition **** |
| 255 | // Address |
| 256 | #define D0F0x2C_ADDRESS 0x2c |
| 257 | |
| 258 | // Type |
| 259 | #define D0F0x2C_TYPE TYPE_D0F0 |
| 260 | // Field Data |
| 261 | #define D0F0x2C_SubsystemVendorID_OFFSET 0 |
| 262 | #define D0F0x2C_SubsystemVendorID_WIDTH 16 |
| 263 | #define D0F0x2C_SubsystemVendorID_MASK 0xffff |
| 264 | #define D0F0x2C_SubsystemID_OFFSET 16 |
| 265 | #define D0F0x2C_SubsystemID_WIDTH 16 |
| 266 | #define D0F0x2C_SubsystemID_MASK 0xffff0000 |
| 267 | |
| 268 | /// D0F0x2C |
| 269 | typedef union { |
| 270 | struct { ///< |
| 271 | UINT32 SubsystemVendorID:16; ///< |
| 272 | UINT32 SubsystemID:16; ///< |
| 273 | } Field; ///< |
| 274 | UINT32 Value; ///< |
| 275 | } D0F0x2C_STRUCT; |
| 276 | |
| 277 | // **** D0F0x34 Register Definition **** |
| 278 | // Address |
| 279 | #define D0F0x34_ADDRESS 0x34 |
| 280 | |
| 281 | // Type |
| 282 | #define D0F0x34_TYPE TYPE_D0F0 |
| 283 | // Field Data |
| 284 | #define D0F0x34_CapPtr_OFFSET 0 |
| 285 | #define D0F0x34_CapPtr_WIDTH 8 |
| 286 | #define D0F0x34_CapPtr_MASK 0xff |
| 287 | #define D0F0x34_Reserved_31_8_OFFSET 8 |
| 288 | #define D0F0x34_Reserved_31_8_WIDTH 24 |
| 289 | #define D0F0x34_Reserved_31_8_MASK 0xffffff00 |
| 290 | |
| 291 | /// D0F0x34 |
| 292 | typedef union { |
| 293 | struct { ///< |
| 294 | UINT32 CapPtr:8 ; ///< |
| 295 | UINT32 Reserved_31_8:24; ///< |
| 296 | } Field; ///< |
| 297 | UINT32 Value; ///< |
| 298 | } D0F0x34_STRUCT; |
| 299 | |
| 300 | // **** D0F0x4C Register Definition **** |
| 301 | // Address |
| 302 | #define D0F0x4C_ADDRESS 0x4c |
| 303 | |
| 304 | // Type |
| 305 | #define D0F0x4C_TYPE TYPE_D0F0 |
| 306 | // Field Data |
| 307 | #define D0F0x4C_Function1Enable_OFFSET 0 |
| 308 | #define D0F0x4C_Function1Enable_WIDTH 1 |
| 309 | #define D0F0x4C_Function1Enable_MASK 0x1 |
| 310 | #define D0F0x4C_ApicEnable_OFFSET 1 |
| 311 | #define D0F0x4C_ApicEnable_WIDTH 1 |
| 312 | #define D0F0x4C_ApicEnable_MASK 0x2 |
| 313 | #define D0F0x4C_Reserved_2_2_OFFSET 2 |
| 314 | #define D0F0x4C_Reserved_2_2_WIDTH 1 |
| 315 | #define D0F0x4C_Reserved_2_2_MASK 0x4 |
| 316 | #define D0F0x4C_Cf8Dis_OFFSET 3 |
| 317 | #define D0F0x4C_Cf8Dis_WIDTH 1 |
| 318 | #define D0F0x4C_Cf8Dis_MASK 0x8 |
| 319 | #define D0F0x4C_PMEDis_OFFSET 4 |
| 320 | #define D0F0x4C_PMEDis_WIDTH 1 |
| 321 | #define D0F0x4C_PMEDis_MASK 0x10 |
| 322 | #define D0F0x4C_SerrDis_OFFSET 5 |
| 323 | #define D0F0x4C_SerrDis_WIDTH 1 |
| 324 | #define D0F0x4C_SerrDis_MASK 0x20 |
| 325 | #define D0F0x4C_Reserved_10_6_OFFSET 6 |
| 326 | #define D0F0x4C_Reserved_10_6_WIDTH 5 |
| 327 | #define D0F0x4C_Reserved_10_6_MASK 0x7c0 |
| 328 | #define D0F0x4C_CRS_OFFSET 11 |
| 329 | #define D0F0x4C_CRS_WIDTH 1 |
| 330 | #define D0F0x4C_CRS_MASK 0x800 |
| 331 | #define D0F0x4C_CfgRdTime_OFFSET 12 |
| 332 | #define D0F0x4C_CfgRdTime_WIDTH 3 |
| 333 | #define D0F0x4C_CfgRdTime_MASK 0x7000 |
| 334 | #define D0F0x4C_Reserved_22_15_OFFSET 15 |
| 335 | #define D0F0x4C_Reserved_22_15_WIDTH 8 |
| 336 | #define D0F0x4C_Reserved_22_15_MASK 0x7f8000 |
| 337 | #define D0F0x4C_MMIOEnable_OFFSET 23 |
| 338 | #define D0F0x4C_MMIOEnable_WIDTH 1 |
| 339 | #define D0F0x4C_MMIOEnable_MASK 0x800000 |
| 340 | #define D0F0x4C_Reserved_25_24_OFFSET 24 |
| 341 | #define D0F0x4C_Reserved_25_24_WIDTH 2 |
| 342 | #define D0F0x4C_Reserved_25_24_MASK 0x3000000 |
| 343 | #define D0F0x4C_HPDis_OFFSET 26 |
| 344 | #define D0F0x4C_HPDis_WIDTH 1 |
| 345 | #define D0F0x4C_HPDis_MASK 0x4000000 |
| 346 | #define D0F0x4C_Reserved_31_27_OFFSET 27 |
| 347 | #define D0F0x4C_Reserved_31_27_WIDTH 5 |
| 348 | #define D0F0x4C_Reserved_31_27_MASK 0xf8000000 |
| 349 | |
| 350 | /// D0F0x4C |
| 351 | typedef union { |
| 352 | struct { ///< |
| 353 | UINT32 Function1Enable:1 ; ///< |
| 354 | UINT32 ApicEnable:1 ; ///< |
| 355 | UINT32 Reserved_2_2:1 ; ///< |
| 356 | UINT32 Cf8Dis:1 ; ///< |
| 357 | UINT32 PMEDis:1 ; ///< |
| 358 | UINT32 SerrDis:1 ; ///< |
| 359 | UINT32 Reserved_10_6:5 ; ///< |
| 360 | UINT32 CRS:1 ; ///< |
| 361 | UINT32 CfgRdTime:3 ; ///< |
| 362 | UINT32 Reserved_22_15:8 ; ///< |
| 363 | UINT32 MMIOEnable:1 ; ///< |
| 364 | UINT32 Reserved_25_24:2 ; ///< |
| 365 | UINT32 HPDis:1 ; ///< |
| 366 | UINT32 Reserved_31_27:5 ; ///< |
| 367 | } Field; ///< |
| 368 | UINT32 Value; ///< |
| 369 | } D0F0x4C_STRUCT; |
| 370 | |
| 371 | // **** D0F0x60 Register Definition **** |
| 372 | // Address |
| 373 | #define D0F0x60_ADDRESS 0x60 |
| 374 | |
| 375 | // Type |
| 376 | #define D0F0x60_TYPE TYPE_D0F0 |
| 377 | // Field Data |
| 378 | #define D0F0x60_MiscIndAddr_OFFSET 0 |
| 379 | #define D0F0x60_MiscIndAddr_WIDTH 7 |
| 380 | #define D0F0x60_MiscIndAddr_MASK 0x7f |
| 381 | #define D0F0x60_MiscIndWrEn_OFFSET 7 |
| 382 | #define D0F0x60_MiscIndWrEn_WIDTH 1 |
| 383 | #define D0F0x60_MiscIndWrEn_MASK 0x80 |
| 384 | #define D0F0x60_Reserved_31_8_OFFSET 8 |
| 385 | #define D0F0x60_Reserved_31_8_WIDTH 24 |
| 386 | #define D0F0x60_Reserved_31_8_MASK 0xffffff00 |
| 387 | |
| 388 | /// D0F0x60 |
| 389 | typedef union { |
| 390 | struct { ///< |
| 391 | UINT32 MiscIndAddr:7 ; ///< |
| 392 | UINT32 MiscIndWrEn:1 ; ///< |
| 393 | UINT32 Reserved_31_8:24; ///< |
| 394 | } Field; ///< |
| 395 | UINT32 Value; ///< |
| 396 | } D0F0x60_STRUCT; |
| 397 | |
| 398 | // **** D0F0x64 Register Definition **** |
| 399 | // Address |
| 400 | #define D0F0x64_ADDRESS 0x64 |
| 401 | |
| 402 | // Type |
| 403 | #define D0F0x64_TYPE TYPE_D0F0 |
| 404 | // Field Data |
| 405 | #define D0F0x64_MiscIndData_OFFSET 0 |
| 406 | #define D0F0x64_MiscIndData_WIDTH 32 |
| 407 | #define D0F0x64_MiscIndData_MASK 0xffffffff |
| 408 | |
| 409 | /// D0F0x64 |
| 410 | typedef union { |
| 411 | struct { ///< |
| 412 | UINT32 MiscIndData:32; ///< |
| 413 | } Field; ///< |
| 414 | UINT32 Value; ///< |
| 415 | } D0F0x64_STRUCT; |
| 416 | |
| 417 | |
| 418 | /// D0F0x78 |
| 419 | typedef union { |
| 420 | struct { ///< |
| 421 | UINT32 Scratch:32; ///< |
| 422 | } Field; ///< |
| 423 | UINT32 Value; ///< |
| 424 | } D0F0x78_STRUCT; |
| 425 | |
| 426 | // **** D0F0x7C Register Definition **** |
| 427 | // Address |
| 428 | #define D0F0x7C_ADDRESS 0x7c |
| 429 | |
| 430 | // Type |
| 431 | #define D0F0x7C_TYPE TYPE_D0F0 |
| 432 | // Field Data |
| 433 | #define D0F0x7C_ForceIntGFXDisable_OFFSET 0 |
| 434 | #define D0F0x7C_ForceIntGFXDisable_WIDTH 1 |
| 435 | #define D0F0x7C_ForceIntGFXDisable_MASK 0x1 |
| 436 | #define D0F0x7C_Reserved_31_1_OFFSET 1 |
| 437 | #define D0F0x7C_Reserved_31_1_WIDTH 31 |
| 438 | #define D0F0x7C_Reserved_31_1_MASK 0xfffffffe |
| 439 | |
| 440 | /// D0F0x7C |
| 441 | typedef union { |
| 442 | struct { ///< |
| 443 | UINT32 ForceIntGFXDisable:1 ; ///< |
| 444 | UINT32 Reserved_31_1:31; ///< |
| 445 | } Field; ///< |
| 446 | UINT32 Value; ///< |
| 447 | } D0F0x7C_STRUCT; |
| 448 | |
| 449 | // **** D0F0x84 Register Definition **** |
| 450 | // Address |
| 451 | #define D0F0x84_ADDRESS 0x84 |
| 452 | |
| 453 | // Type |
| 454 | #define D0F0x84_TYPE TYPE_D0F0 |
| 455 | // Field Data |
| 456 | #define D0F0x84_Reserved_3_0_OFFSET 0 |
| 457 | #define D0F0x84_Reserved_3_0_WIDTH 4 |
| 458 | #define D0F0x84_Reserved_3_0_MASK 0xf |
| 459 | #define D0F0x84_Ev6Mode_OFFSET 4 |
| 460 | #define D0F0x84_Ev6Mode_WIDTH 1 |
| 461 | #define D0F0x84_Ev6Mode_MASK 0x10 |
| 462 | #define D0F0x84_Reserved_7_5_OFFSET 5 |
| 463 | #define D0F0x84_Reserved_7_5_WIDTH 3 |
| 464 | #define D0F0x84_Reserved_7_5_MASK 0xe0 |
| 465 | #define D0F0x84_PmeMode_OFFSET 8 |
| 466 | #define D0F0x84_PmeMode_WIDTH 1 |
| 467 | #define D0F0x84_PmeMode_MASK 0x100 |
| 468 | #define D0F0x84_PmeTurnOff_OFFSET 9 |
| 469 | #define D0F0x84_PmeTurnOff_WIDTH 1 |
| 470 | #define D0F0x84_PmeTurnOff_MASK 0x200 |
| 471 | #define D0F0x84_Reserved_31_10_OFFSET 10 |
| 472 | #define D0F0x84_Reserved_31_10_WIDTH 22 |
| 473 | #define D0F0x84_Reserved_31_10_MASK 0xfffffc00 |
| 474 | |
| 475 | /// D0F0x84 |
| 476 | typedef union { |
| 477 | struct { ///< |
| 478 | UINT32 Reserved_3_0:4 ; ///< |
| 479 | UINT32 Ev6Mode:1 ; ///< |
| 480 | UINT32 Reserved_7_5:3 ; ///< |
| 481 | UINT32 PmeMode:1 ; ///< |
| 482 | UINT32 PmeTurnOff:1 ; ///< |
| 483 | UINT32 Reserved_31_10:22; ///< |
| 484 | } Field; ///< |
| 485 | UINT32 Value; ///< |
| 486 | } D0F0x84_STRUCT; |
| 487 | |
| 488 | // **** D0F0x90 Register Definition **** |
| 489 | // Address |
| 490 | #define D0F0x90_ADDRESS 0x90 |
| 491 | |
| 492 | // Type |
| 493 | #define D0F0x90_TYPE TYPE_D0F0 |
| 494 | // Field Data |
| 495 | #define D0F0x90_Reserved_22_0_OFFSET 0 |
| 496 | #define D0F0x90_Reserved_22_0_WIDTH 23 |
| 497 | #define D0F0x90_Reserved_22_0_MASK 0x7fffff |
| 498 | #define D0F0x90_TopOfDram_OFFSET 23 |
| 499 | #define D0F0x90_TopOfDram_WIDTH 9 |
| 500 | #define D0F0x90_TopOfDram_MASK 0xff800000 |
| 501 | |
| 502 | /// D0F0x90 |
| 503 | typedef union { |
| 504 | struct { ///< |
| 505 | UINT32 Reserved_22_0:23; ///< |
| 506 | UINT32 TopOfDram:9 ; ///< |
| 507 | } Field; ///< |
| 508 | UINT32 Value; ///< |
| 509 | } D0F0x90_STRUCT; |
| 510 | |
| 511 | // **** D0F0x94 Register Definition **** |
| 512 | // Address |
| 513 | #define D0F0x94_ADDRESS 0x94 |
| 514 | |
| 515 | // Type |
| 516 | #define D0F0x94_TYPE TYPE_D0F0 |
| 517 | // Field Data |
| 518 | #define D0F0x94_OrbIndAddr_OFFSET 0 |
| 519 | #define D0F0x94_OrbIndAddr_WIDTH 7 |
| 520 | #define D0F0x94_OrbIndAddr_MASK 0x7f |
| 521 | #define D0F0x94_Reserved_7_7_OFFSET 7 |
| 522 | #define D0F0x94_Reserved_7_7_WIDTH 1 |
| 523 | #define D0F0x94_Reserved_7_7_MASK 0x80 |
| 524 | #define D0F0x94_OrbIndWrEn_OFFSET 8 |
| 525 | #define D0F0x94_OrbIndWrEn_WIDTH 1 |
| 526 | #define D0F0x94_OrbIndWrEn_MASK 0x100 |
| 527 | #define D0F0x94_Reserved_31_9_OFFSET 9 |
| 528 | #define D0F0x94_Reserved_31_9_WIDTH 23 |
| 529 | #define D0F0x94_Reserved_31_9_MASK 0xfffffe00 |
| 530 | |
| 531 | /// D0F0x94 |
| 532 | typedef union { |
| 533 | struct { ///< |
| 534 | UINT32 OrbIndAddr:7 ; ///< |
| 535 | UINT32 Reserved_7_7:1 ; ///< |
| 536 | UINT32 OrbIndWrEn:1 ; ///< |
| 537 | UINT32 Reserved_31_9:23; ///< |
| 538 | } Field; ///< |
| 539 | UINT32 Value; ///< |
| 540 | } D0F0x94_STRUCT; |
| 541 | |
| 542 | // **** D0F0x98 Register Definition **** |
| 543 | // Address |
| 544 | #define D0F0x98_ADDRESS 0x98 |
| 545 | |
| 546 | // Type |
| 547 | #define D0F0x98_TYPE TYPE_D0F0 |
| 548 | // Field Data |
| 549 | #define D0F0x98_OrbIndData_OFFSET 0 |
| 550 | #define D0F0x98_OrbIndData_WIDTH 32 |
| 551 | #define D0F0x98_OrbIndData_MASK 0xffffffff |
| 552 | |
| 553 | /// D0F0x98 |
| 554 | typedef union { |
| 555 | struct { ///< |
| 556 | UINT32 OrbIndData:32; ///< |
| 557 | } Field; ///< |
| 558 | UINT32 Value; ///< |
| 559 | } D0F0x98_STRUCT; |
| 560 | |
| 561 | // **** D0F0xE0 Register Definition **** |
| 562 | // Address |
| 563 | #define D0F0xE0_ADDRESS 0xe0 |
| 564 | |
| 565 | // Type |
| 566 | #define D0F0xE0_TYPE TYPE_D0F0 |
| 567 | // Field Data |
| 568 | #define D0F0xE0_PcieIndxAddr_OFFSET 0 |
| 569 | #define D0F0xE0_PcieIndxAddr_WIDTH 16 |
| 570 | #define D0F0xE0_PcieIndxAddr_MASK 0xffff |
| 571 | #define D0F0xE0_FrameType_OFFSET 16 |
| 572 | #define D0F0xE0_FrameType_WIDTH 8 |
| 573 | #define D0F0xE0_FrameType_MASK 0xff0000 |
| 574 | #define D0F0xE0_BlockSelect_OFFSET 24 |
| 575 | #define D0F0xE0_BlockSelect_WIDTH 8 |
| 576 | #define D0F0xE0_BlockSelect_MASK 0xff000000 |
| 577 | |
| 578 | /// D0F0xE0 |
| 579 | typedef union { |
| 580 | struct { ///< |
| 581 | UINT32 PcieIndxAddr:16; ///< |
| 582 | UINT32 FrameType:8 ; ///< |
| 583 | UINT32 BlockSelect:8 ; ///< |
| 584 | } Field; ///< |
| 585 | UINT32 Value; ///< |
| 586 | } D0F0xE0_STRUCT; |
| 587 | |
| 588 | // **** D0F0xE4 Register Definition **** |
| 589 | // Address |
| 590 | #define D0F0xE4_ADDRESS 0xe4 |
| 591 | |
| 592 | // Type |
| 593 | #define D0F0xE4_TYPE TYPE_D0F0 |
| 594 | // Field Data |
| 595 | #define D0F0xE4_PcieIndxData_OFFSET 0 |
| 596 | #define D0F0xE4_PcieIndxData_WIDTH 32 |
| 597 | #define D0F0xE4_PcieIndxData_MASK 0xffffffff |
| 598 | |
| 599 | /// D0F0xE4 |
| 600 | typedef union { |
| 601 | struct { ///< |
| 602 | UINT32 PcieIndxData:32; ///< |
| 603 | } Field; ///< |
| 604 | UINT32 Value; ///< |
| 605 | } D0F0xE4_STRUCT; |
| 606 | |
| 607 | // **** D18F1xF0 Register Definition **** |
| 608 | // Address |
| 609 | #define D18F1xF0_ADDRESS 0xf0 |
| 610 | |
| 611 | // Type |
| 612 | #define D18F1xF0_TYPE TYPE_D18F1 |
| 613 | // Field Data |
| 614 | #define D18F1xF0_DramHoleValid_OFFSET 0 |
| 615 | #define D18F1xF0_DramHoleValid_WIDTH 1 |
| 616 | #define D18F1xF0_DramHoleValid_MASK 0x1 |
| 617 | #define D18F1xF0_Reserved_6_1_OFFSET 1 |
| 618 | #define D18F1xF0_Reserved_6_1_WIDTH 6 |
| 619 | #define D18F1xF0_Reserved_6_1_MASK 0x7e |
| 620 | #define D18F1xF0_DramHoleOffset_31_23__OFFSET 7 |
| 621 | #define D18F1xF0_DramHoleOffset_31_23__WIDTH 9 |
| 622 | #define D18F1xF0_DramHoleOffset_31_23__MASK 0xff80 |
| 623 | #define D18F1xF0_Reserved_23_16_OFFSET 16 |
| 624 | #define D18F1xF0_Reserved_23_16_WIDTH 8 |
| 625 | #define D18F1xF0_Reserved_23_16_MASK 0xff0000 |
| 626 | #define D18F1xF0_DramHoleBase_31_24__OFFSET 24 |
| 627 | #define D18F1xF0_DramHoleBase_31_24__WIDTH 8 |
| 628 | #define D18F1xF0_DramHoleBase_31_24__MASK 0xff000000 |
| 629 | |
| 630 | /// D18F1xF0 |
| 631 | typedef union { |
| 632 | struct { ///< |
| 633 | UINT32 DramHoleValid:1 ; ///< |
| 634 | UINT32 Reserved_6_1:6 ; ///< |
| 635 | UINT32 DramHoleOffset_31_23_:9 ; ///< |
| 636 | UINT32 Reserved_23_16:8 ; ///< |
| 637 | UINT32 DramHoleBase_31_24_:8 ; ///< |
| 638 | } Field; ///< |
| 639 | UINT32 Value; ///< |
| 640 | } D18F1xF0_STRUCT; |
| 641 | |
| 642 | // **** D18F2x00 Register Definition **** |
| 643 | // Address |
| 644 | #define D18F2x00_ADDRESS 0x0 |
| 645 | |
| 646 | // Type |
| 647 | #define D18F2x00_TYPE TYPE_D18F2 |
| 648 | // Field Data |
| 649 | #define D18F2x00_VendorID_OFFSET 0 |
| 650 | #define D18F2x00_VendorID_WIDTH 16 |
| 651 | #define D18F2x00_VendorID_MASK 0xffff |
| 652 | #define D18F2x00_DeviceID_OFFSET 16 |
| 653 | #define D18F2x00_DeviceID_WIDTH 16 |
| 654 | #define D18F2x00_DeviceID_MASK 0xffff0000 |
| 655 | |
| 656 | /// D18F2x00 |
| 657 | typedef union { |
| 658 | struct { ///< |
| 659 | UINT32 VendorID:16; ///< |
| 660 | UINT32 DeviceID:16; ///< |
| 661 | } Field; ///< |
| 662 | UINT32 Value; ///< |
| 663 | } D18F2x00_STRUCT; |
| 664 | |
| 665 | |
| 666 | // **** D18F2x08 Register Definition **** |
| 667 | // Address |
| 668 | #define D18F2x08_ADDRESS 0x8 |
| 669 | |
| 670 | // Type |
| 671 | #define D18F2x08_TYPE TYPE_D18F2 |
| 672 | // Field Data |
| 673 | #define D18F2x08_RevID_OFFSET 0 |
| 674 | #define D18F2x08_RevID_WIDTH 8 |
| 675 | #define D18F2x08_RevID_MASK 0xff |
| 676 | #define D18F2x08_ClassCode_OFFSET 8 |
| 677 | #define D18F2x08_ClassCode_WIDTH 24 |
| 678 | #define D18F2x08_ClassCode_MASK 0xffffff00 |
| 679 | |
| 680 | /// D18F2x08 |
| 681 | typedef union { |
| 682 | struct { ///< |
| 683 | UINT32 RevID:8 ; ///< |
| 684 | UINT32 ClassCode:24; ///< |
| 685 | } Field; ///< |
| 686 | UINT32 Value; ///< |
| 687 | } D18F2x08_STRUCT; |
| 688 | |
| 689 | // **** D18F2x0C Register Definition **** |
| 690 | // Address |
| 691 | #define D18F2x0C_ADDRESS 0xc |
| 692 | |
| 693 | // Type |
| 694 | #define D18F2x0C_TYPE TYPE_D18F2 |
| 695 | // Field Data |
| 696 | #define D18F2x0C_HeaderTypeReg_OFFSET 0 |
| 697 | #define D18F2x0C_HeaderTypeReg_WIDTH 32 |
| 698 | #define D18F2x0C_HeaderTypeReg_MASK 0xffffffff |
| 699 | |
| 700 | /// D18F2x0C |
| 701 | typedef union { |
| 702 | struct { ///< |
| 703 | UINT32 HeaderTypeReg:32; ///< |
| 704 | } Field; ///< |
| 705 | UINT32 Value; ///< |
| 706 | } D18F2x0C_STRUCT; |
| 707 | |
| 708 | |
| 709 | // **** D18F2x040 Register Definition **** |
| 710 | // Address |
| 711 | #define D18F2x040_ADDRESS 0x40 |
| 712 | |
| 713 | // Type |
| 714 | #define D18F2x040_TYPE TYPE_D18F2 |
| 715 | // Field Data |
| 716 | #define D18F2x040_CSEnable_OFFSET 0 |
| 717 | #define D18F2x040_CSEnable_WIDTH 1 |
| 718 | #define D18F2x040_CSEnable_MASK 0x1 |
| 719 | #define D18F2x040_Reserved_1_1_OFFSET 1 |
| 720 | #define D18F2x040_Reserved_1_1_WIDTH 1 |
| 721 | #define D18F2x040_Reserved_1_1_MASK 0x2 |
| 722 | #define D18F2x040_TestFail_OFFSET 2 |
| 723 | #define D18F2x040_TestFail_WIDTH 1 |
| 724 | #define D18F2x040_TestFail_MASK 0x4 |
| 725 | #define D18F2x040_OnDimmMirror_OFFSET 3 |
| 726 | #define D18F2x040_OnDimmMirror_WIDTH 1 |
| 727 | #define D18F2x040_OnDimmMirror_MASK 0x8 |
| 728 | #define D18F2x040_Reserved_4_4_OFFSET 4 |
| 729 | #define D18F2x040_Reserved_4_4_WIDTH 1 |
| 730 | #define D18F2x040_Reserved_4_4_MASK 0x10 |
| 731 | #define D18F2x040_Reserved_31_29_OFFSET 29 |
| 732 | #define D18F2x040_Reserved_31_29_WIDTH 3 |
| 733 | #define D18F2x040_Reserved_31_29_MASK 0xe0000000 |
| 734 | |
| 735 | /// D18F2x040 |
| 736 | typedef union { |
| 737 | struct { ///< |
| 738 | UINT32 CSEnable:1 ; ///< |
| 739 | UINT32 Reserved_1_1:1 ; ///< |
| 740 | UINT32 TestFail:1 ; ///< |
| 741 | UINT32 OnDimmMirror:1 ; ///< |
| 742 | UINT32 Reserved_4_4:1 ; ///< |
| 743 | UINT32 :9 ; ///< |
| 744 | UINT32 Reserved_18_14:5 ; ///< |
| 745 | UINT32 :10; ///< |
| 746 | UINT32 Reserved_31_29:3 ; ///< |
| 747 | } Field; ///< |
| 748 | UINT32 Value; ///< |
| 749 | } D18F2x040_STRUCT; |
| 750 | |
| 751 | // **** D18F2x044 Register Definition **** |
| 752 | // Address |
| 753 | #define D18F2x044_ADDRESS 0x44 |
| 754 | |
| 755 | // Type |
| 756 | #define D18F2x044_TYPE TYPE_D18F2 |
| 757 | // Field Data |
| 758 | #define D18F2x044_CSEnable_OFFSET 0 |
| 759 | #define D18F2x044_CSEnable_WIDTH 1 |
| 760 | #define D18F2x044_CSEnable_MASK 0x1 |
| 761 | #define D18F2x044_Reserved_1_1_OFFSET 1 |
| 762 | #define D18F2x044_Reserved_1_1_WIDTH 1 |
| 763 | #define D18F2x044_Reserved_1_1_MASK 0x2 |
| 764 | #define D18F2x044_TestFail_OFFSET 2 |
| 765 | #define D18F2x044_TestFail_WIDTH 1 |
| 766 | #define D18F2x044_TestFail_MASK 0x4 |
| 767 | #define D18F2x044_OnDimmMirror_OFFSET 3 |
| 768 | #define D18F2x044_OnDimmMirror_WIDTH 1 |
| 769 | #define D18F2x044_OnDimmMirror_MASK 0x8 |
| 770 | #define D18F2x044_Reserved_4_4_OFFSET 4 |
| 771 | #define D18F2x044_Reserved_4_4_WIDTH 1 |
| 772 | #define D18F2x044_Reserved_4_4_MASK 0x10 |
| 773 | #define D18F2x044_Reserved_31_29_OFFSET 29 |
| 774 | #define D18F2x044_Reserved_31_29_WIDTH 3 |
| 775 | #define D18F2x044_Reserved_31_29_MASK 0xe0000000 |
| 776 | |
| 777 | /// D18F2x044 |
| 778 | typedef union { |
| 779 | struct { ///< |
| 780 | UINT32 CSEnable:1 ; ///< |
| 781 | UINT32 Reserved_1_1:1 ; ///< |
| 782 | UINT32 TestFail:1 ; ///< |
| 783 | UINT32 OnDimmMirror:1 ; ///< |
| 784 | UINT32 Reserved_4_4:1 ; ///< |
| 785 | UINT32 :9 ; ///< |
| 786 | UINT32 Reserved_18_14:5 ; ///< |
| 787 | UINT32 :10; ///< |
| 788 | UINT32 Reserved_31_29:3 ; ///< |
| 789 | } Field; ///< |
| 790 | UINT32 Value; ///< |
| 791 | } D18F2x044_STRUCT; |
| 792 | |
| 793 | // **** D18F2x048 Register Definition **** |
| 794 | // Address |
| 795 | #define D18F2x048_ADDRESS 0x48 |
| 796 | |
| 797 | // Type |
| 798 | #define D18F2x048_TYPE TYPE_D18F2 |
| 799 | // Field Data |
| 800 | #define D18F2x048_CSEnable_OFFSET 0 |
| 801 | #define D18F2x048_CSEnable_WIDTH 1 |
| 802 | #define D18F2x048_CSEnable_MASK 0x1 |
| 803 | #define D18F2x048_Reserved_1_1_OFFSET 1 |
| 804 | #define D18F2x048_Reserved_1_1_WIDTH 1 |
| 805 | #define D18F2x048_Reserved_1_1_MASK 0x2 |
| 806 | #define D18F2x048_TestFail_OFFSET 2 |
| 807 | #define D18F2x048_TestFail_WIDTH 1 |
| 808 | #define D18F2x048_TestFail_MASK 0x4 |
| 809 | #define D18F2x048_OnDimmMirror_OFFSET 3 |
| 810 | #define D18F2x048_OnDimmMirror_WIDTH 1 |
| 811 | #define D18F2x048_OnDimmMirror_MASK 0x8 |
| 812 | #define D18F2x048_Reserved_4_4_OFFSET 4 |
| 813 | #define D18F2x048_Reserved_4_4_WIDTH 1 |
| 814 | #define D18F2x048_Reserved_4_4_MASK 0x10 |
| 815 | #define D18F2x048_Reserved_31_29_OFFSET 29 |
| 816 | #define D18F2x048_Reserved_31_29_WIDTH 3 |
| 817 | #define D18F2x048_Reserved_31_29_MASK 0xe0000000 |
| 818 | |
| 819 | /// D18F2x048 |
| 820 | typedef union { |
| 821 | struct { ///< |
| 822 | UINT32 CSEnable:1 ; ///< |
| 823 | UINT32 Reserved_1_1:1 ; ///< |
| 824 | UINT32 TestFail:1 ; ///< |
| 825 | UINT32 OnDimmMirror:1 ; ///< |
| 826 | UINT32 Reserved_4_4:1 ; ///< |
| 827 | UINT32 :9 ; ///< |
| 828 | UINT32 Reserved_18_14:5 ; ///< |
| 829 | UINT32 :10; ///< |
| 830 | UINT32 Reserved_31_29:3 ; ///< |
| 831 | } Field; ///< |
| 832 | UINT32 Value; ///< |
| 833 | } D18F2x048_STRUCT; |
| 834 | |
| 835 | // **** D18F2x04C Register Definition **** |
| 836 | // Address |
| 837 | #define D18F2x04C_ADDRESS 0x4c |
| 838 | |
| 839 | // Type |
| 840 | #define D18F2x04C_TYPE TYPE_D18F2 |
| 841 | // Field Data |
| 842 | #define D18F2x04C_CSEnable_OFFSET 0 |
| 843 | #define D18F2x04C_CSEnable_WIDTH 1 |
| 844 | #define D18F2x04C_CSEnable_MASK 0x1 |
| 845 | #define D18F2x04C_Reserved_1_1_OFFSET 1 |
| 846 | #define D18F2x04C_Reserved_1_1_WIDTH 1 |
| 847 | #define D18F2x04C_Reserved_1_1_MASK 0x2 |
| 848 | #define D18F2x04C_TestFail_OFFSET 2 |
| 849 | #define D18F2x04C_TestFail_WIDTH 1 |
| 850 | #define D18F2x04C_TestFail_MASK 0x4 |
| 851 | #define D18F2x04C_OnDimmMirror_OFFSET 3 |
| 852 | #define D18F2x04C_OnDimmMirror_WIDTH 1 |
| 853 | #define D18F2x04C_OnDimmMirror_MASK 0x8 |
| 854 | #define D18F2x04C_Reserved_4_4_OFFSET 4 |
| 855 | #define D18F2x04C_Reserved_4_4_WIDTH 1 |
| 856 | #define D18F2x04C_Reserved_4_4_MASK 0x10 |
| 857 | #define D18F2x04C_Reserved_31_29_OFFSET 29 |
| 858 | #define D18F2x04C_Reserved_31_29_WIDTH 3 |
| 859 | #define D18F2x04C_Reserved_31_29_MASK 0xe0000000 |
| 860 | |
| 861 | /// D18F2x04C |
| 862 | typedef union { |
| 863 | struct { ///< |
| 864 | UINT32 CSEnable:1 ; ///< |
| 865 | UINT32 Reserved_1_1:1 ; ///< |
| 866 | UINT32 TestFail:1 ; ///< |
| 867 | UINT32 OnDimmMirror:1 ; ///< |
| 868 | UINT32 Reserved_4_4:1 ; ///< |
| 869 | UINT32 :9 ; ///< |
| 870 | UINT32 Reserved_18_14:5 ; ///< |
| 871 | UINT32 :10; ///< |
| 872 | UINT32 Reserved_31_29:3 ; ///< |
| 873 | } Field; ///< |
| 874 | UINT32 Value; ///< |
| 875 | } D18F2x04C_STRUCT; |
| 876 | |
| 877 | // **** D18F2x060 Register Definition **** |
| 878 | // Address |
| 879 | #define D18F2x060_ADDRESS 0x60 |
| 880 | |
| 881 | // Type |
| 882 | #define D18F2x060_TYPE TYPE_D18F2 |
| 883 | // Field Data |
| 884 | #define D18F2x060_Reserved_4_0_OFFSET 0 |
| 885 | #define D18F2x060_Reserved_4_0_WIDTH 5 |
| 886 | #define D18F2x060_Reserved_4_0_MASK 0x1f |
| 887 | #define D18F2x060_Reserved_31_29_OFFSET 29 |
| 888 | #define D18F2x060_Reserved_31_29_WIDTH 3 |
| 889 | #define D18F2x060_Reserved_31_29_MASK 0xe0000000 |
| 890 | |
| 891 | /// D18F2x060 |
| 892 | typedef union { |
| 893 | struct { ///< |
| 894 | UINT32 Reserved_4_0:5 ; ///< |
| 895 | UINT32 :9 ; ///< |
| 896 | UINT32 Reserved_18_14:5 ; ///< |
| 897 | UINT32 :10; ///< |
| 898 | UINT32 Reserved_31_29:3 ; ///< |
| 899 | } Field; ///< |
| 900 | UINT32 Value; ///< |
| 901 | } D18F2x060_STRUCT; |
| 902 | |
| 903 | // **** D18F2x064 Register Definition **** |
| 904 | // Address |
| 905 | #define D18F2x064_ADDRESS 0x64 |
| 906 | |
| 907 | // Type |
| 908 | #define D18F2x064_TYPE TYPE_D18F2 |
| 909 | // Field Data |
| 910 | #define D18F2x064_Reserved_4_0_OFFSET 0 |
| 911 | #define D18F2x064_Reserved_4_0_WIDTH 5 |
| 912 | #define D18F2x064_Reserved_4_0_MASK 0x1f |
| 913 | #define D18F2x064_Reserved_31_29_OFFSET 29 |
| 914 | #define D18F2x064_Reserved_31_29_WIDTH 3 |
| 915 | #define D18F2x064_Reserved_31_29_MASK 0xe0000000 |
| 916 | |
| 917 | /// D18F2x064 |
| 918 | typedef union { |
| 919 | struct { ///< |
| 920 | UINT32 Reserved_4_0:5 ; ///< |
| 921 | UINT32 :9 ; ///< |
| 922 | UINT32 Reserved_18_14:5 ; ///< |
| 923 | UINT32 :10; ///< |
| 924 | UINT32 Reserved_31_29:3 ; ///< |
| 925 | } Field; ///< |
| 926 | UINT32 Value; ///< |
| 927 | } D18F2x064_STRUCT; |
| 928 | |
| 929 | // **** D18F2x078 Register Definition **** |
| 930 | // Address |
| 931 | #define D18F2x078_ADDRESS 0x78 |
| 932 | |
| 933 | // Type |
| 934 | #define D18F2x078_TYPE TYPE_D18F2 |
| 935 | // Field Data |
| 936 | #define D18F2x078_Reserved_14_14_OFFSET 14 |
| 937 | #define D18F2x078_Reserved_14_14_WIDTH 1 |
| 938 | #define D18F2x078_Reserved_14_14_MASK 0x4000 |
| 939 | #define D18F2x078_Reserved_15_15_OFFSET 15 |
| 940 | #define D18F2x078_Reserved_15_15_WIDTH 1 |
| 941 | #define D18F2x078_Reserved_15_15_MASK 0x8000 |
| 942 | #define D18F2x078_Reserved_16_16_OFFSET 16 |
| 943 | #define D18F2x078_Reserved_16_16_WIDTH 1 |
| 944 | #define D18F2x078_Reserved_16_16_MASK 0x10000 |
| 945 | #define D18F2x078_AddrCmdTriEn_OFFSET 17 |
| 946 | #define D18F2x078_AddrCmdTriEn_WIDTH 1 |
| 947 | #define D18F2x078_AddrCmdTriEn_MASK 0x20000 |
| 948 | #define D18F2x078_Reserved_18_18_OFFSET 18 |
| 949 | #define D18F2x078_Reserved_18_18_WIDTH 1 |
| 950 | #define D18F2x078_Reserved_18_18_MASK 0x40000 |
| 951 | #define D18F2x078_Reserved_19_19_OFFSET 19 |
| 952 | #define D18F2x078_Reserved_19_19_WIDTH 1 |
| 953 | #define D18F2x078_Reserved_19_19_MASK 0x80000 |
| 954 | |
| 955 | /// D18F2x078 |
| 956 | typedef union { |
| 957 | struct { ///< |
| 958 | UINT32 :4 ; ///< |
| 959 | UINT32 :2 ; ///< |
| 960 | UINT32 :1 ; ///< |
| 961 | UINT32 :1 ; ///< |
| 962 | UINT32 :2 ; ///< |
| 963 | UINT32 :2 ; ///< |
| 964 | UINT32 :2 ; ///< |
| 965 | UINT32 Reserved_14_14:1 ; ///< |
| 966 | UINT32 Reserved_15_15:1 ; ///< |
| 967 | UINT32 Reserved_16_16:1 ; ///< |
| 968 | UINT32 AddrCmdTriEn:1 ; ///< |
| 969 | UINT32 Reserved_18_18:1 ; ///< |
| 970 | UINT32 Reserved_19_19:1 ; ///< |
| 971 | UINT32 :1 ; ///< |
| 972 | UINT32 :1 ; ///< |
| 973 | UINT32 :10; ///< |
| 974 | } Field; ///< |
| 975 | UINT32 Value; ///< |
| 976 | } D18F2x078_STRUCT; |
| 977 | |
| 978 | |
| 979 | |
| 980 | // **** D18F2x084 Register Definition **** |
| 981 | // Address |
| 982 | #define D18F2x084_ADDRESS 0x84 |
| 983 | |
| 984 | // Type |
| 985 | #define D18F2x084_TYPE TYPE_D18F2 |
| 986 | // Field Data |
| 987 | #define D18F2x084_BurstCtrl_OFFSET 0 |
| 988 | #define D18F2x084_BurstCtrl_WIDTH 2 |
| 989 | #define D18F2x084_BurstCtrl_MASK 0x3 |
| 990 | #define D18F2x084_Reserved_3_2_OFFSET 2 |
| 991 | #define D18F2x084_Reserved_3_2_WIDTH 2 |
| 992 | #define D18F2x084_Reserved_3_2_MASK 0xc |
| 993 | #define D18F2x084_Reserved_19_7_OFFSET 7 |
| 994 | #define D18F2x084_Reserved_19_7_WIDTH 13 |
| 995 | #define D18F2x084_Reserved_19_7_MASK 0xfff80 |
| 996 | #define D18F2x084_PchgPDModeSel_OFFSET 23 |
| 997 | #define D18F2x084_PchgPDModeSel_WIDTH 1 |
| 998 | #define D18F2x084_PchgPDModeSel_MASK 0x800000 |
| 999 | #define D18F2x084_Reserved_31_24_OFFSET 24 |
| 1000 | #define D18F2x084_Reserved_31_24_WIDTH 8 |
| 1001 | #define D18F2x084_Reserved_31_24_MASK 0xff000000 |
| 1002 | |
| 1003 | /// D18F2x084 |
| 1004 | typedef union { |
| 1005 | struct { ///< |
| 1006 | UINT32 BurstCtrl:2 ; ///< |
| 1007 | UINT32 Reserved_3_2:2 ; ///< |
| 1008 | UINT32 :3 ; ///< |
| 1009 | UINT32 Reserved_19_7:13; ///< |
| 1010 | UINT32 :3 ; ///< |
| 1011 | UINT32 PchgPDModeSel:1 ; ///< |
| 1012 | UINT32 Reserved_31_24:8 ; ///< |
| 1013 | } Field; ///< |
| 1014 | UINT32 Value; ///< |
| 1015 | } D18F2x084_STRUCT; |
| 1016 | |
| 1017 | // **** D18F2x088 Register Definition **** |
| 1018 | // Address |
| 1019 | #define D18F2x088_ADDRESS 0x88 |
| 1020 | |
| 1021 | // Type |
| 1022 | #define D18F2x088_TYPE TYPE_D18F2 |
| 1023 | // Field Data |
| 1024 | #define D18F2x088_Reserved_23_4_OFFSET 4 |
| 1025 | #define D18F2x088_Reserved_23_4_WIDTH 20 |
| 1026 | #define D18F2x088_Reserved_23_4_MASK 0xfffff0 |
| 1027 | |
| 1028 | /// D18F2x088 |
| 1029 | typedef union { |
| 1030 | struct { ///< |
| 1031 | UINT32 :4 ; ///< |
| 1032 | UINT32 Reserved_23_4:20; ///< |
| 1033 | UINT32 :8 ; ///< |
| 1034 | } Field; ///< |
| 1035 | UINT32 Value; ///< |
| 1036 | } D18F2x088_STRUCT; |
| 1037 | |
| 1038 | |
| 1039 | |
| 1040 | |
| 1041 | // **** D18F2x098 Register Definition **** |
| 1042 | // Address |
| 1043 | #define D18F2x098_ADDRESS 0x98 |
| 1044 | |
| 1045 | // Type |
| 1046 | #define D18F2x098_TYPE TYPE_D18F2 |
| 1047 | // Field Data |
| 1048 | #define D18F2x098_DctOffset_OFFSET 0 |
| 1049 | #define D18F2x098_DctOffset_WIDTH 30 |
| 1050 | #define D18F2x098_DctOffset_MASK 0x3fffffff |
| 1051 | #define D18F2x098_DctAccessWrite_OFFSET 30 |
| 1052 | #define D18F2x098_DctAccessWrite_WIDTH 1 |
| 1053 | #define D18F2x098_DctAccessWrite_MASK 0x40000000 |
| 1054 | #define D18F2x098_Reserved_31_31_OFFSET 31 |
| 1055 | #define D18F2x098_Reserved_31_31_WIDTH 1 |
| 1056 | #define D18F2x098_Reserved_31_31_MASK 0x80000000 |
| 1057 | |
| 1058 | /// D18F2x098 |
| 1059 | typedef union { |
| 1060 | struct { ///< |
| 1061 | UINT32 DctOffset:30; ///< |
| 1062 | UINT32 DctAccessWrite:1 ; ///< |
| 1063 | UINT32 Reserved_31_31:1 ; ///< |
| 1064 | } Field; ///< |
| 1065 | UINT32 Value; ///< |
| 1066 | } D18F2x098_STRUCT; |
| 1067 | |
| 1068 | // **** D18F2x09C Register Definition **** |
| 1069 | // Address |
| 1070 | #define D18F2x09C_ADDRESS 0x9c |
| 1071 | |
| 1072 | // Type |
| 1073 | #define D18F2x09C_TYPE TYPE_D18F2 |
| 1074 | // Field Data |
| 1075 | #define D18F2x09C_DctDataPort_OFFSET 0 |
| 1076 | #define D18F2x09C_DctDataPort_WIDTH 32 |
| 1077 | #define D18F2x09C_DctDataPort_MASK 0xffffffff |
| 1078 | |
| 1079 | /// D18F2x09C |
| 1080 | typedef union { |
| 1081 | struct { ///< |
| 1082 | UINT32 DctDataPort:32; ///< |
| 1083 | } Field; ///< |
| 1084 | UINT32 Value; ///< |
| 1085 | } D18F2x09C_STRUCT; |
| 1086 | |
| 1087 | |
| 1088 | // **** D18F2xA4 Register Definition **** |
| 1089 | // Address |
| 1090 | #define D18F2xA4_ADDRESS 0xa4 |
| 1091 | |
| 1092 | // Type |
| 1093 | #define D18F2xA4_TYPE TYPE_D18F2 |
| 1094 | // Field Data |
| 1095 | #define D18F2xA4_DoubleTrefRateEn_OFFSET 0 |
| 1096 | #define D18F2xA4_DoubleTrefRateEn_WIDTH 1 |
| 1097 | |
| 1098 | |
| 1099 | // **** D18F2xAC Register Definition **** |
| 1100 | // Address |
| 1101 | #define D18F2xAC_ADDRESS 0xac |
| 1102 | |
| 1103 | // Type |
| 1104 | #define D18F2xAC_TYPE TYPE_D18F2 |
| 1105 | // Field Data |
| 1106 | #define D18F2xAC_Reserved_31_1_OFFSET 1 |
| 1107 | #define D18F2xAC_Reserved_31_1_WIDTH 31 |
| 1108 | #define D18F2xAC_Reserved_31_1_MASK 0xfffffffe |
| 1109 | |
| 1110 | /// D18F2xAC |
| 1111 | typedef union { |
| 1112 | struct { ///< |
| 1113 | UINT32 MemTempHot:1 ; ///< |
| 1114 | UINT32 Reserved_31_1:31; ///< |
| 1115 | } Field; ///< |
| 1116 | UINT32 Value; ///< |
| 1117 | } D18F2xAC_STRUCT; |
| 1118 | |
| 1119 | |
| 1120 | |
| 1121 | // **** D18F2x114 Register Definition **** |
| 1122 | // Address |
| 1123 | #define D18F2x114_ADDRESS 0x114 |
| 1124 | |
| 1125 | // Type |
| 1126 | #define D18F2x114_TYPE TYPE_D18F2 |
| 1127 | // Field Data |
| 1128 | #define D18F2x114_Reserved_8_0_OFFSET 0 |
| 1129 | #define D18F2x114_Reserved_8_0_WIDTH 9 |
| 1130 | #define D18F2x114_Reserved_8_0_MASK 0x1ff |
| 1131 | #define D18F2x114_DctSelIntLvAddr_2__OFFSET 9 |
| 1132 | #define D18F2x114_DctSelIntLvAddr_2__WIDTH 1 |
| 1133 | #define D18F2x114_DctSelIntLvAddr_2__MASK 0x200 |
| 1134 | |
| 1135 | /// D18F2x114 |
| 1136 | typedef union { |
| 1137 | struct { ///< |
| 1138 | UINT32 Reserved_8_0:9 ; ///< |
| 1139 | UINT32 DctSelIntLvAddr_2_:1 ; ///< |
| 1140 | UINT32 :14; ///< |
| 1141 | UINT32 :8 ; ///< |
| 1142 | } Field; ///< |
| 1143 | UINT32 Value; ///< |
| 1144 | } D18F2x114_STRUCT; |
| 1145 | |
| 1146 | |
| 1147 | // **** D18F3x00 Register Definition **** |
| 1148 | // Address |
| 1149 | #define D18F3x00_ADDRESS 0x0 |
| 1150 | |
| 1151 | // Type |
| 1152 | #define D18F3x00_TYPE TYPE_D18F3 |
| 1153 | // Field Data |
| 1154 | #define D18F3x00_VendorID_OFFSET 0 |
| 1155 | #define D18F3x00_VendorID_WIDTH 16 |
| 1156 | #define D18F3x00_VendorID_MASK 0xffff |
| 1157 | #define D18F3x00_DeviceID_OFFSET 16 |
| 1158 | #define D18F3x00_DeviceID_WIDTH 16 |
| 1159 | #define D18F3x00_DeviceID_MASK 0xffff0000 |
| 1160 | |
| 1161 | /// D18F3x00 |
| 1162 | typedef union { |
| 1163 | struct { ///< |
| 1164 | UINT32 VendorID:16; ///< |
| 1165 | UINT32 DeviceID:16; ///< |
| 1166 | } Field; ///< |
| 1167 | UINT32 Value; ///< |
| 1168 | } D18F3x00_STRUCT; |
| 1169 | |
| 1170 | // **** D18F3x04 Register Definition **** |
| 1171 | // Address |
| 1172 | #define D18F3x04_ADDRESS 0x4 |
| 1173 | |
| 1174 | // Type |
| 1175 | #define D18F3x04_TYPE TYPE_D18F3 |
| 1176 | // Field Data |
| 1177 | #define D18F3x04_Command_OFFSET 0 |
| 1178 | #define D18F3x04_Command_WIDTH 16 |
| 1179 | #define D18F3x04_Command_MASK 0xffff |
| 1180 | #define D18F3x04_Status_OFFSET 16 |
| 1181 | #define D18F3x04_Status_WIDTH 16 |
| 1182 | #define D18F3x04_Status_MASK 0xffff0000 |
| 1183 | |
| 1184 | /// D18F3x04 |
| 1185 | typedef union { |
| 1186 | struct { ///< |
| 1187 | UINT32 Command:16; ///< |
| 1188 | UINT32 Status:16; ///< |
| 1189 | } Field; ///< |
| 1190 | UINT32 Value; ///< |
| 1191 | } D18F3x04_STRUCT; |
| 1192 | |
| 1193 | // **** D18F3x08 Register Definition **** |
| 1194 | // Address |
| 1195 | #define D18F3x08_ADDRESS 0x8 |
| 1196 | |
| 1197 | // Type |
| 1198 | #define D18F3x08_TYPE TYPE_D18F3 |
| 1199 | // Field Data |
| 1200 | #define D18F3x08_RevID_OFFSET 0 |
| 1201 | #define D18F3x08_RevID_WIDTH 8 |
| 1202 | #define D18F3x08_RevID_MASK 0xff |
| 1203 | #define D18F3x08_ClassCode_OFFSET 8 |
| 1204 | #define D18F3x08_ClassCode_WIDTH 24 |
| 1205 | #define D18F3x08_ClassCode_MASK 0xffffff00 |
| 1206 | |
| 1207 | /// D18F3x08 |
| 1208 | typedef union { |
| 1209 | struct { ///< |
| 1210 | UINT32 RevID:8 ; ///< |
| 1211 | UINT32 ClassCode:24; ///< |
| 1212 | } Field; ///< |
| 1213 | UINT32 Value; ///< |
| 1214 | } D18F3x08_STRUCT; |
| 1215 | |
| 1216 | // **** D18F3x0C Register Definition **** |
| 1217 | // Address |
| 1218 | #define D18F3x0C_ADDRESS 0xc |
| 1219 | |
| 1220 | // Type |
| 1221 | #define D18F3x0C_TYPE TYPE_D18F3 |
| 1222 | // Field Data |
| 1223 | #define D18F3x0C_HeaderTypeReg_OFFSET 0 |
| 1224 | #define D18F3x0C_HeaderTypeReg_WIDTH 32 |
| 1225 | #define D18F3x0C_HeaderTypeReg_MASK 0xffffffff |
| 1226 | |
| 1227 | /// D18F3x0C |
| 1228 | typedef union { |
| 1229 | struct { ///< |
| 1230 | UINT32 HeaderTypeReg:32; ///< |
| 1231 | } Field; ///< |
| 1232 | UINT32 Value; ///< |
| 1233 | } D18F3x0C_STRUCT; |
| 1234 | |
| 1235 | // **** D18F3x34 Register Definition **** |
| 1236 | // Address |
| 1237 | #define D18F3x34_ADDRESS 0x34 |
| 1238 | |
| 1239 | // Type |
| 1240 | #define D18F3x34_TYPE TYPE_D18F3 |
| 1241 | // Field Data |
| 1242 | #define D18F3x34_CapPtr_OFFSET 0 |
| 1243 | #define D18F3x34_CapPtr_WIDTH 8 |
| 1244 | #define D18F3x34_CapPtr_MASK 0xff |
| 1245 | #define D18F3x34_Reserved_31_8_OFFSET 8 |
| 1246 | #define D18F3x34_Reserved_31_8_WIDTH 24 |
| 1247 | #define D18F3x34_Reserved_31_8_MASK 0xffffff00 |
| 1248 | |
| 1249 | /// D18F3x34 |
| 1250 | typedef union { |
| 1251 | struct { ///< |
| 1252 | UINT32 CapPtr:8 ; ///< |
| 1253 | UINT32 Reserved_31_8:24; ///< |
| 1254 | } Field; ///< |
| 1255 | UINT32 Value; ///< |
| 1256 | } D18F3x34_STRUCT; |
| 1257 | |
| 1258 | |
| 1259 | // **** D18F3x48 Register Definition **** |
| 1260 | // Address |
| 1261 | #define D18F3x48_ADDRESS 0x48 |
| 1262 | |
| 1263 | // Type |
| 1264 | #define D18F3x48_TYPE TYPE_D18F3 |
| 1265 | // Field Data |
| 1266 | #define D18F3x48_ErrorCode_OFFSET 0 |
| 1267 | #define D18F3x48_ErrorCode_WIDTH 16 |
| 1268 | #define D18F3x48_ErrorCode_MASK 0xffff |
| 1269 | #define D18F3x48_ErrorCodeExt_OFFSET 16 |
| 1270 | #define D18F3x48_ErrorCodeExt_WIDTH 5 |
| 1271 | #define D18F3x48_ErrorCodeExt_MASK 0x1f0000 |
| 1272 | #define D18F3x48_Reserved_31_21_OFFSET 21 |
| 1273 | #define D18F3x48_Reserved_31_21_WIDTH 11 |
| 1274 | #define D18F3x48_Reserved_31_21_MASK 0xffe00000 |
| 1275 | |
| 1276 | /// D18F3x48 |
| 1277 | typedef union { |
| 1278 | struct { ///< |
| 1279 | UINT32 ErrorCode:16; ///< |
| 1280 | UINT32 ErrorCodeExt:5 ; ///< |
| 1281 | UINT32 Reserved_31_21:11; ///< |
| 1282 | } Field; ///< |
| 1283 | UINT32 Value; ///< |
| 1284 | } D18F3x48_STRUCT; |
| 1285 | |
| 1286 | |
| 1287 | // **** D18F3x64 Register Definition **** |
| 1288 | // Address |
| 1289 | #define D18F3x64_ADDRESS 0x64 |
| 1290 | |
| 1291 | // Type |
| 1292 | #define D18F3x64_TYPE TYPE_D18F3 |
| 1293 | // Field Data |
| 1294 | #define D18F3x64_HtcEn_OFFSET 0 |
| 1295 | #define D18F3x64_HtcEn_WIDTH 1 |
| 1296 | #define D18F3x64_HtcEn_MASK 0x1 |
| 1297 | #define D18F3x64_Reserved_3_1_OFFSET 1 |
| 1298 | #define D18F3x64_Reserved_3_1_WIDTH 3 |
| 1299 | #define D18F3x64_Reserved_3_1_MASK 0xe |
| 1300 | #define D18F3x64_HtcAct_OFFSET 4 |
| 1301 | #define D18F3x64_HtcAct_WIDTH 1 |
| 1302 | #define D18F3x64_HtcAct_MASK 0x10 |
| 1303 | #define D18F3x64_HtcActSts_OFFSET 5 |
| 1304 | #define D18F3x64_HtcActSts_WIDTH 1 |
| 1305 | #define D18F3x64_HtcActSts_MASK 0x20 |
| 1306 | #define D18F3x64_PslApicHiEn_OFFSET 6 |
| 1307 | #define D18F3x64_PslApicHiEn_WIDTH 1 |
| 1308 | #define D18F3x64_PslApicHiEn_MASK 0x40 |
| 1309 | #define D18F3x64_PslApicLoEn_OFFSET 7 |
| 1310 | #define D18F3x64_PslApicLoEn_WIDTH 1 |
| 1311 | #define D18F3x64_PslApicLoEn_MASK 0x80 |
| 1312 | #define D18F3x64_Reserved_15_8_OFFSET 8 |
| 1313 | #define D18F3x64_Reserved_15_8_WIDTH 8 |
| 1314 | #define D18F3x64_Reserved_15_8_MASK 0xff00 |
| 1315 | #define D18F3x64_HtcTmpLmt_OFFSET 16 |
| 1316 | #define D18F3x64_HtcTmpLmt_WIDTH 7 |
| 1317 | #define D18F3x64_HtcTmpLmt_MASK 0x7f0000 |
| 1318 | #define D18F3x64_HtcSlewSel_OFFSET 23 |
| 1319 | #define D18F3x64_HtcSlewSel_WIDTH 1 |
| 1320 | #define D18F3x64_HtcSlewSel_MASK 0x800000 |
| 1321 | #define D18F3x64_HtcHystLmt_OFFSET 24 |
| 1322 | #define D18F3x64_HtcHystLmt_WIDTH 4 |
| 1323 | #define D18F3x64_HtcHystLmt_MASK 0xf000000 |
| 1324 | #define D18F3x64_HtcPstateLimit_OFFSET 28 |
| 1325 | #define D18F3x64_HtcPstateLimit_WIDTH 3 |
| 1326 | #define D18F3x64_HtcPstateLimit_MASK 0x70000000 |
| 1327 | |
| 1328 | /// D18F3x64 |
| 1329 | typedef union { |
| 1330 | struct { ///< |
| 1331 | UINT32 HtcEn:1 ; ///< |
| 1332 | UINT32 Reserved_3_1:3 ; ///< |
| 1333 | UINT32 HtcAct:1 ; ///< |
| 1334 | UINT32 HtcActSts:1 ; ///< |
| 1335 | UINT32 PslApicHiEn:1 ; ///< |
| 1336 | UINT32 PslApicLoEn:1 ; ///< |
| 1337 | UINT32 Reserved_15_8:8 ; ///< |
| 1338 | UINT32 HtcTmpLmt:7 ; ///< |
| 1339 | UINT32 HtcSlewSel:1 ; ///< |
| 1340 | UINT32 HtcHystLmt:4 ; ///< |
| 1341 | UINT32 HtcPstateLimit:3 ; ///< |
| 1342 | UINT32 :1 ; ///< |
| 1343 | } Field; ///< |
| 1344 | UINT32 Value; ///< |
| 1345 | } D18F3x64_STRUCT; |
| 1346 | |
| 1347 | |
| 1348 | // **** D18F3x88 Register Definition **** |
| 1349 | // Address |
| 1350 | #define D18F3x88_ADDRESS 0x88 |
| 1351 | |
| 1352 | // Type |
| 1353 | #define D18F3x88_TYPE TYPE_D18F3 |
| 1354 | // Field Data |
| 1355 | #define D18F3x88_Reserved_31_0_OFFSET 0 |
| 1356 | #define D18F3x88_Reserved_31_0_WIDTH 32 |
| 1357 | #define D18F3x88_Reserved_31_0_MASK 0xffffffff |
| 1358 | |
| 1359 | /// D18F3x88 |
| 1360 | typedef union { |
| 1361 | struct { ///< |
| 1362 | UINT32 Reserved_31_0:32; ///< |
| 1363 | } Field; ///< |
| 1364 | UINT32 Value; ///< |
| 1365 | } D18F3x88_STRUCT; |
| 1366 | |
| 1367 | |
| 1368 | // **** D18F3xE4 Register Definition **** |
| 1369 | // Address |
| 1370 | #define D18F3xE4_ADDRESS 0xe4 |
| 1371 | |
| 1372 | // Type |
| 1373 | #define D18F3xE4_TYPE TYPE_D18F3 |
| 1374 | // Field Data |
| 1375 | #define D18F3xE4_Reserved_0_0_OFFSET 0 |
| 1376 | #define D18F3xE4_Reserved_0_0_WIDTH 1 |
| 1377 | #define D18F3xE4_Reserved_0_0_MASK 0x1 |
| 1378 | #define D18F3xE4_Thermtp_OFFSET 1 |
| 1379 | #define D18F3xE4_Thermtp_WIDTH 1 |
| 1380 | #define D18F3xE4_Thermtp_MASK 0x2 |
| 1381 | #define D18F3xE4_Reserved_2_2_OFFSET 2 |
| 1382 | #define D18F3xE4_Reserved_2_2_WIDTH 1 |
| 1383 | #define D18F3xE4_Reserved_2_2_MASK 0x4 |
| 1384 | #define D18F3xE4_ThermtpSense_OFFSET 3 |
| 1385 | #define D18F3xE4_ThermtpSense_WIDTH 1 |
| 1386 | #define D18F3xE4_ThermtpSense_MASK 0x8 |
| 1387 | #define D18F3xE4_Reserved_4_4_OFFSET 4 |
| 1388 | #define D18F3xE4_Reserved_4_4_WIDTH 1 |
| 1389 | #define D18F3xE4_Reserved_4_4_MASK 0x10 |
| 1390 | #define D18F3xE4_ThermtpEn_OFFSET 5 |
| 1391 | #define D18F3xE4_ThermtpEn_WIDTH 1 |
| 1392 | #define D18F3xE4_ThermtpEn_MASK 0x20 |
| 1393 | #define D18F3xE4_Reserved_7_6_OFFSET 6 |
| 1394 | #define D18F3xE4_Reserved_7_6_WIDTH 2 |
| 1395 | #define D18F3xE4_Reserved_7_6_MASK 0xc0 |
| 1396 | #define D18F3xE4_Reserved_30_8_OFFSET 8 |
| 1397 | #define D18F3xE4_Reserved_30_8_WIDTH 23 |
| 1398 | #define D18F3xE4_Reserved_30_8_MASK 0x7fffff00 |
| 1399 | #define D18F3xE4_SwThermtp_OFFSET 31 |
| 1400 | #define D18F3xE4_SwThermtp_WIDTH 1 |
| 1401 | #define D18F3xE4_SwThermtp_MASK 0x80000000 |
| 1402 | |
| 1403 | /// D18F3xE4 |
| 1404 | typedef union { |
| 1405 | struct { ///< |
| 1406 | UINT32 Reserved_0_0:1 ; ///< |
| 1407 | UINT32 Thermtp:1 ; ///< |
| 1408 | UINT32 Reserved_2_2:1 ; ///< |
| 1409 | UINT32 ThermtpSense:1 ; ///< |
| 1410 | UINT32 Reserved_4_4:1 ; ///< |
| 1411 | UINT32 ThermtpEn:1 ; ///< |
| 1412 | UINT32 Reserved_7_6:2 ; ///< |
| 1413 | UINT32 Reserved_30_8:23; ///< |
| 1414 | UINT32 SwThermtp:1 ; ///< |
| 1415 | } Field; ///< |
| 1416 | UINT32 Value; ///< |
| 1417 | } D18F3xE4_STRUCT; |
| 1418 | |
| 1419 | |
| 1420 | // **** D18F3xF0 Register Definition **** |
| 1421 | // Address |
| 1422 | #define D18F3xF0_ADDRESS 0xf0 |
| 1423 | |
| 1424 | // Type |
| 1425 | #define D18F3xF0_TYPE TYPE_D18F3 |
| 1426 | // Field Data |
| 1427 | #define D18F3xF0_Reserved_31_0_OFFSET 0 |
| 1428 | #define D18F3xF0_Reserved_31_0_WIDTH 32 |
| 1429 | #define D18F3xF0_Reserved_31_0_MASK 0xffffffff |
| 1430 | |
| 1431 | /// D18F3xF0 |
| 1432 | typedef union { |
| 1433 | struct { ///< |
| 1434 | UINT32 Reserved_31_0:32; ///< |
| 1435 | } Field; ///< |
| 1436 | UINT32 Value; ///< |
| 1437 | } D18F3xF0_STRUCT; |
| 1438 | |
| 1439 | // **** D18F3xF4 Register Definition **** |
| 1440 | // Address |
| 1441 | #define D18F3xF4_ADDRESS 0xf4 |
| 1442 | |
| 1443 | // Type |
| 1444 | #define D18F3xF4_TYPE TYPE_D18F3 |
| 1445 | // Field Data |
| 1446 | #define D18F3xF4_Reserved_31_0_OFFSET 0 |
| 1447 | #define D18F3xF4_Reserved_31_0_WIDTH 32 |
| 1448 | #define D18F3xF4_Reserved_31_0_MASK 0xffffffff |
| 1449 | |
| 1450 | /// D18F3xF4 |
| 1451 | typedef union { |
| 1452 | struct { ///< |
| 1453 | UINT32 Reserved_31_0:32; ///< |
| 1454 | } Field; ///< |
| 1455 | UINT32 Value; ///< |
| 1456 | } D18F3xF4_STRUCT; |
| 1457 | |
| 1458 | // **** D18F3xF8 Register Definition **** |
| 1459 | // Address |
| 1460 | #define D18F3xF8_ADDRESS 0xf8 |
| 1461 | |
| 1462 | // Type |
| 1463 | #define D18F3xF8_TYPE TYPE_D18F3 |
| 1464 | // Field Data |
| 1465 | #define D18F3xF8_Reserved_31_0_OFFSET 0 |
| 1466 | #define D18F3xF8_Reserved_31_0_WIDTH 32 |
| 1467 | #define D18F3xF8_Reserved_31_0_MASK 0xffffffff |
| 1468 | |
| 1469 | /// D18F3xF8 |
| 1470 | typedef union { |
| 1471 | struct { ///< |
| 1472 | UINT32 Reserved_31_0:32; ///< |
| 1473 | } Field; ///< |
| 1474 | UINT32 Value; ///< |
| 1475 | } D18F3xF8_STRUCT; |
| 1476 | |
| 1477 | // **** D18F3xFC Register Definition **** |
| 1478 | // Address |
| 1479 | #define D18F3xFC_ADDRESS 0xfc |
| 1480 | |
| 1481 | // Type |
| 1482 | #define D18F3xFC_TYPE TYPE_D18F3 |
| 1483 | // Field Data |
| 1484 | #define D18F3xFC_Stepping_OFFSET 0 |
| 1485 | #define D18F3xFC_Stepping_WIDTH 4 |
| 1486 | #define D18F3xFC_Stepping_MASK 0xf |
| 1487 | #define D18F3xFC_BaseModel_OFFSET 4 |
| 1488 | #define D18F3xFC_BaseModel_WIDTH 4 |
| 1489 | #define D18F3xFC_BaseModel_MASK 0xf0 |
| 1490 | #define D18F3xFC_BaseFamily_OFFSET 8 |
| 1491 | #define D18F3xFC_BaseFamily_WIDTH 4 |
| 1492 | #define D18F3xFC_BaseFamily_MASK 0xf00 |
| 1493 | #define D18F3xFC_Reserved_15_12_OFFSET 12 |
| 1494 | #define D18F3xFC_Reserved_15_12_WIDTH 4 |
| 1495 | #define D18F3xFC_Reserved_15_12_MASK 0xf000 |
| 1496 | #define D18F3xFC_ExtModel_OFFSET 16 |
| 1497 | #define D18F3xFC_ExtModel_WIDTH 4 |
| 1498 | #define D18F3xFC_ExtModel_MASK 0xf0000 |
| 1499 | #define D18F3xFC_ExtFamily_OFFSET 20 |
| 1500 | #define D18F3xFC_ExtFamily_WIDTH 8 |
| 1501 | #define D18F3xFC_ExtFamily_MASK 0xff00000 |
| 1502 | #define D18F3xFC_Reserved_31_28_OFFSET 28 |
| 1503 | #define D18F3xFC_Reserved_31_28_WIDTH 4 |
| 1504 | #define D18F3xFC_Reserved_31_28_MASK 0xf0000000 |
| 1505 | |
| 1506 | /// D18F3xFC |
| 1507 | typedef union { |
| 1508 | struct { ///< |
| 1509 | UINT32 Stepping:4 ; ///< |
| 1510 | UINT32 BaseModel:4 ; ///< |
| 1511 | UINT32 BaseFamily:4 ; ///< |
| 1512 | UINT32 Reserved_15_12:4 ; ///< |
| 1513 | UINT32 ExtModel:4 ; ///< |
| 1514 | UINT32 ExtFamily:8 ; ///< |
| 1515 | UINT32 Reserved_31_28:4 ; ///< |
| 1516 | } Field; ///< |
| 1517 | UINT32 Value; ///< |
| 1518 | } D18F3xFC_STRUCT; |
| 1519 | |
| 1520 | |
| 1521 | |
| 1522 | |
| 1523 | |
| 1524 | |
| 1525 | |
| 1526 | // **** D18F3x1CC Register Definition **** |
| 1527 | // Address |
| 1528 | #define D18F3x1CC_ADDRESS 0x1cc |
| 1529 | |
| 1530 | // Type |
| 1531 | #define D18F3x1CC_TYPE TYPE_D18F3 |
| 1532 | // Field Data |
| 1533 | #define D18F3x1CC_LvtOffset_OFFSET 0 |
| 1534 | #define D18F3x1CC_LvtOffset_WIDTH 4 |
| 1535 | #define D18F3x1CC_LvtOffset_MASK 0xf |
| 1536 | #define D18F3x1CC_Reserved_7_4_OFFSET 4 |
| 1537 | #define D18F3x1CC_Reserved_7_4_WIDTH 4 |
| 1538 | #define D18F3x1CC_Reserved_7_4_MASK 0xf0 |
| 1539 | #define D18F3x1CC_LvtOffsetVal_OFFSET 8 |
| 1540 | #define D18F3x1CC_LvtOffsetVal_WIDTH 1 |
| 1541 | #define D18F3x1CC_LvtOffsetVal_MASK 0x100 |
| 1542 | #define D18F3x1CC_Reserved_31_9_OFFSET 9 |
| 1543 | #define D18F3x1CC_Reserved_31_9_WIDTH 23 |
| 1544 | #define D18F3x1CC_Reserved_31_9_MASK 0xfffffe00 |
| 1545 | |
| 1546 | /// D18F3x1CC |
| 1547 | typedef union { |
| 1548 | struct { ///< |
| 1549 | UINT32 LvtOffset:4 ; ///< |
| 1550 | UINT32 Reserved_7_4:4 ; ///< |
| 1551 | UINT32 LvtOffsetVal:1 ; ///< |
| 1552 | UINT32 Reserved_31_9:23; ///< |
| 1553 | } Field; ///< |
| 1554 | UINT32 Value; ///< |
| 1555 | } D18F3x1CC_STRUCT; |
| 1556 | |
| 1557 | |
| 1558 | |
| 1559 | |
| 1560 | |
| 1561 | |
| 1562 | |
| 1563 | |
| 1564 | |
| 1565 | |
| 1566 | |
| 1567 | // **** DxF0x00 Register Definition **** |
| 1568 | // Address |
| 1569 | #define DxF0x00_ADDRESS 0x0 |
| 1570 | |
| 1571 | // Type |
| 1572 | #define DxF0x00_TYPE TYPE_D4F0 |
| 1573 | // Field Data |
| 1574 | #define DxF0x00_VendorID_OFFSET 0 |
| 1575 | #define DxF0x00_VendorID_WIDTH 16 |
| 1576 | #define DxF0x00_VendorID_MASK 0xffff |
| 1577 | #define DxF0x00_DeviceID_OFFSET 16 |
| 1578 | #define DxF0x00_DeviceID_WIDTH 16 |
| 1579 | #define DxF0x00_DeviceID_MASK 0xffff0000 |
| 1580 | |
| 1581 | /// DxF0x00 |
| 1582 | typedef union { |
| 1583 | struct { ///< |
| 1584 | UINT32 VendorID:16; ///< |
| 1585 | UINT32 DeviceID:16; ///< |
| 1586 | } Field; ///< |
| 1587 | UINT32 Value; ///< |
| 1588 | } DxF0x00_STRUCT; |
| 1589 | |
| 1590 | |
| 1591 | // **** DxF0x08 Register Definition **** |
| 1592 | // Address |
| 1593 | #define DxF0x08_ADDRESS 0x8 |
| 1594 | |
| 1595 | // Type |
| 1596 | #define DxF0x08_TYPE TYPE_D4F0 |
| 1597 | // Field Data |
| 1598 | #define DxF0x08_RevID_OFFSET 0 |
| 1599 | #define DxF0x08_RevID_WIDTH 8 |
| 1600 | #define DxF0x08_RevID_MASK 0xff |
| 1601 | #define DxF0x08_ClassCode_OFFSET 8 |
| 1602 | #define DxF0x08_ClassCode_WIDTH 24 |
| 1603 | #define DxF0x08_ClassCode_MASK 0xffffff00 |
| 1604 | |
| 1605 | /// DxF0x08 |
| 1606 | typedef union { |
| 1607 | struct { ///< |
| 1608 | UINT32 RevID:8 ; ///< |
| 1609 | UINT32 ClassCode:24; ///< |
| 1610 | } Field; ///< |
| 1611 | UINT32 Value; ///< |
| 1612 | } DxF0x08_STRUCT; |
| 1613 | |
| 1614 | // **** DxF0x0C Register Definition **** |
| 1615 | // Address |
| 1616 | #define DxF0x0C_ADDRESS 0xc |
| 1617 | |
| 1618 | // Type |
| 1619 | #define DxF0x0C_TYPE TYPE_D4F0 |
| 1620 | // Field Data |
| 1621 | #define DxF0x0C_CacheLineSize_OFFSET 0 |
| 1622 | #define DxF0x0C_CacheLineSize_WIDTH 8 |
| 1623 | #define DxF0x0C_CacheLineSize_MASK 0xff |
| 1624 | #define DxF0x0C_LatencyTimer_OFFSET 8 |
| 1625 | #define DxF0x0C_LatencyTimer_WIDTH 8 |
| 1626 | #define DxF0x0C_LatencyTimer_MASK 0xff00 |
| 1627 | #define DxF0x0C_HeaderTypeReg_OFFSET 16 |
| 1628 | #define DxF0x0C_HeaderTypeReg_WIDTH 8 |
| 1629 | #define DxF0x0C_HeaderTypeReg_MASK 0xff0000 |
| 1630 | #define DxF0x0C_BIST_OFFSET 24 |
| 1631 | #define DxF0x0C_BIST_WIDTH 8 |
| 1632 | #define DxF0x0C_BIST_MASK 0xff000000 |
| 1633 | |
| 1634 | /// DxF0x0C |
| 1635 | typedef union { |
| 1636 | struct { ///< |
| 1637 | UINT32 CacheLineSize:8 ; ///< |
| 1638 | UINT32 LatencyTimer:8 ; ///< |
| 1639 | UINT32 HeaderTypeReg:8 ; ///< |
| 1640 | UINT32 BIST:8 ; ///< |
| 1641 | } Field; ///< |
| 1642 | UINT32 Value; ///< |
| 1643 | } DxF0x0C_STRUCT; |
| 1644 | |
| 1645 | // **** DxF0x18 Register Definition **** |
| 1646 | // Address |
| 1647 | #define DxF0x18_ADDRESS 0x18 |
| 1648 | |
| 1649 | // Type |
| 1650 | #define DxF0x18_TYPE TYPE_D4F0 |
| 1651 | // Field Data |
| 1652 | #define DxF0x18_PrimaryBus_OFFSET 0 |
| 1653 | #define DxF0x18_PrimaryBus_WIDTH 8 |
| 1654 | #define DxF0x18_PrimaryBus_MASK 0xff |
| 1655 | #define DxF0x18_SecondaryBus_OFFSET 8 |
| 1656 | #define DxF0x18_SecondaryBus_WIDTH 8 |
| 1657 | #define DxF0x18_SecondaryBus_MASK 0xff00 |
| 1658 | #define DxF0x18_SubBusNumber_OFFSET 16 |
| 1659 | #define DxF0x18_SubBusNumber_WIDTH 8 |
| 1660 | #define DxF0x18_SubBusNumber_MASK 0xff0000 |
| 1661 | #define DxF0x18_SecondaryLatencyTimer_OFFSET 24 |
| 1662 | #define DxF0x18_SecondaryLatencyTimer_WIDTH 8 |
| 1663 | #define DxF0x18_SecondaryLatencyTimer_MASK 0xff000000 |
| 1664 | |
| 1665 | /// DxF0x18 |
| 1666 | typedef union { |
| 1667 | struct { ///< |
| 1668 | UINT32 PrimaryBus:8 ; ///< |
| 1669 | UINT32 SecondaryBus:8 ; ///< |
| 1670 | UINT32 SubBusNumber:8 ; ///< |
| 1671 | UINT32 SecondaryLatencyTimer:8 ; ///< |
| 1672 | } Field; ///< |
| 1673 | UINT32 Value; ///< |
| 1674 | } DxF0x18_STRUCT; |
| 1675 | |
| 1676 | |
| 1677 | // **** DxF0x20 Register Definition **** |
| 1678 | // Address |
| 1679 | #define DxF0x20_ADDRESS 0x20 |
| 1680 | |
| 1681 | // Type |
| 1682 | #define DxF0x20_TYPE TYPE_D4F0 |
| 1683 | // Field Data |
| 1684 | #define DxF0x20_Reserved_3_0_OFFSET 0 |
| 1685 | #define DxF0x20_Reserved_3_0_WIDTH 4 |
| 1686 | #define DxF0x20_Reserved_3_0_MASK 0xf |
| 1687 | #define DxF0x20_MemBase_OFFSET 4 |
| 1688 | #define DxF0x20_MemBase_WIDTH 12 |
| 1689 | #define DxF0x20_MemBase_MASK 0xfff0 |
| 1690 | #define DxF0x20_Reserved_19_16_OFFSET 16 |
| 1691 | #define DxF0x20_Reserved_19_16_WIDTH 4 |
| 1692 | #define DxF0x20_Reserved_19_16_MASK 0xf0000 |
| 1693 | #define DxF0x20_MemLimit_OFFSET 20 |
| 1694 | #define DxF0x20_MemLimit_WIDTH 12 |
| 1695 | #define DxF0x20_MemLimit_MASK 0xfff00000 |
| 1696 | |
| 1697 | /// DxF0x20 |
| 1698 | typedef union { |
| 1699 | struct { ///< |
| 1700 | UINT32 Reserved_3_0:4 ; ///< |
| 1701 | UINT32 MemBase:12; ///< |
| 1702 | UINT32 Reserved_19_16:4 ; ///< |
| 1703 | UINT32 MemLimit:12; ///< |
| 1704 | } Field; ///< |
| 1705 | UINT32 Value; ///< |
| 1706 | } DxF0x20_STRUCT; |
| 1707 | |
| 1708 | // **** DxF0x24 Register Definition **** |
| 1709 | // Address |
| 1710 | #define DxF0x24_ADDRESS 0x24 |
| 1711 | |
| 1712 | // Type |
| 1713 | #define DxF0x24_TYPE TYPE_D4F0 |
| 1714 | // Field Data |
| 1715 | #define DxF0x24_PrefMemBaseR_OFFSET 0 |
| 1716 | #define DxF0x24_PrefMemBaseR_WIDTH 4 |
| 1717 | #define DxF0x24_PrefMemBaseR_MASK 0xf |
| 1718 | #define DxF0x24_PrefMemBase_31_20__OFFSET 4 |
| 1719 | #define DxF0x24_PrefMemBase_31_20__WIDTH 12 |
| 1720 | #define DxF0x24_PrefMemBase_31_20__MASK 0xfff0 |
| 1721 | #define DxF0x24_PrefMemLimitR_OFFSET 16 |
| 1722 | #define DxF0x24_PrefMemLimitR_WIDTH 4 |
| 1723 | #define DxF0x24_PrefMemLimitR_MASK 0xf0000 |
| 1724 | #define DxF0x24_PrefMemLimit_OFFSET 20 |
| 1725 | #define DxF0x24_PrefMemLimit_WIDTH 12 |
| 1726 | #define DxF0x24_PrefMemLimit_MASK 0xfff00000 |
| 1727 | |
| 1728 | /// DxF0x24 |
| 1729 | typedef union { |
| 1730 | struct { ///< |
| 1731 | UINT32 PrefMemBaseR:4 ; ///< |
| 1732 | UINT32 PrefMemBase_31_20_:12; ///< |
| 1733 | UINT32 PrefMemLimitR:4 ; ///< |
| 1734 | UINT32 PrefMemLimit:12; ///< |
| 1735 | } Field; ///< |
| 1736 | UINT32 Value; ///< |
| 1737 | } DxF0x24_STRUCT; |
| 1738 | |
| 1739 | // **** DxF0x28 Register Definition **** |
| 1740 | // Address |
| 1741 | #define DxF0x28_ADDRESS 0x28 |
| 1742 | |
| 1743 | // Type |
| 1744 | #define DxF0x28_TYPE TYPE_D4F0 |
| 1745 | // Field Data |
| 1746 | #define DxF0x28_PrefMemBase_63_32__OFFSET 0 |
| 1747 | #define DxF0x28_PrefMemBase_63_32__WIDTH 32 |
| 1748 | #define DxF0x28_PrefMemBase_63_32__MASK 0xffffffff |
| 1749 | |
| 1750 | /// DxF0x28 |
| 1751 | typedef union { |
| 1752 | struct { ///< |
| 1753 | UINT32 PrefMemBase_63_32_:32; ///< |
| 1754 | } Field; ///< |
| 1755 | UINT32 Value; ///< |
| 1756 | } DxF0x28_STRUCT; |
| 1757 | |
| 1758 | // **** DxF0x2C Register Definition **** |
| 1759 | // Address |
| 1760 | #define DxF0x2C_ADDRESS 0x2c |
| 1761 | |
| 1762 | // Type |
| 1763 | #define DxF0x2C_TYPE TYPE_D4F0 |
| 1764 | // Field Data |
| 1765 | #define DxF0x2C_PrefMemLimit_63_32__OFFSET 0 |
| 1766 | #define DxF0x2C_PrefMemLimit_63_32__WIDTH 32 |
| 1767 | #define DxF0x2C_PrefMemLimit_63_32__MASK 0xffffffff |
| 1768 | |
| 1769 | /// DxF0x2C |
| 1770 | typedef union { |
| 1771 | struct { ///< |
| 1772 | UINT32 PrefMemLimit_63_32_:32; ///< |
| 1773 | } Field; ///< |
| 1774 | UINT32 Value; ///< |
| 1775 | } DxF0x2C_STRUCT; |
| 1776 | |
| 1777 | // **** DxF0x30 Register Definition **** |
| 1778 | // Address |
| 1779 | #define DxF0x30_ADDRESS 0x30 |
| 1780 | |
| 1781 | // Type |
| 1782 | #define DxF0x30_TYPE TYPE_D4F0 |
| 1783 | // Field Data |
| 1784 | #define DxF0x30_IOBase_31_16__OFFSET 0 |
| 1785 | #define DxF0x30_IOBase_31_16__WIDTH 16 |
| 1786 | #define DxF0x30_IOBase_31_16__MASK 0xffff |
| 1787 | #define DxF0x30_IOLimit_31_16__OFFSET 16 |
| 1788 | #define DxF0x30_IOLimit_31_16__WIDTH 16 |
| 1789 | #define DxF0x30_IOLimit_31_16__MASK 0xffff0000 |
| 1790 | |
| 1791 | /// DxF0x30 |
| 1792 | typedef union { |
| 1793 | struct { ///< |
| 1794 | UINT32 IOBase_31_16_:16; ///< |
| 1795 | UINT32 IOLimit_31_16_:16; ///< |
| 1796 | } Field; ///< |
| 1797 | UINT32 Value; ///< |
| 1798 | } DxF0x30_STRUCT; |
| 1799 | |
| 1800 | // **** DxF0x34 Register Definition **** |
| 1801 | // Address |
| 1802 | #define DxF0x34_ADDRESS 0x34 |
| 1803 | |
| 1804 | // Type |
| 1805 | #define DxF0x34_TYPE TYPE_D4F0 |
| 1806 | // Field Data |
| 1807 | #define DxF0x34_CapPtr_OFFSET 0 |
| 1808 | #define DxF0x34_CapPtr_WIDTH 8 |
| 1809 | #define DxF0x34_CapPtr_MASK 0xff |
| 1810 | #define DxF0x34_Reserved_31_8_OFFSET 8 |
| 1811 | #define DxF0x34_Reserved_31_8_WIDTH 24 |
| 1812 | #define DxF0x34_Reserved_31_8_MASK 0xffffff00 |
| 1813 | |
| 1814 | /// DxF0x34 |
| 1815 | typedef union { |
| 1816 | struct { ///< |
| 1817 | UINT32 CapPtr:8 ; ///< |
| 1818 | UINT32 Reserved_31_8:24; ///< |
| 1819 | } Field; ///< |
| 1820 | UINT32 Value; ///< |
| 1821 | } DxF0x34_STRUCT; |
| 1822 | |
| 1823 | // **** DxF0x3C Register Definition **** |
| 1824 | // Address |
| 1825 | #define DxF0x3C_ADDRESS 0x3c |
| 1826 | |
| 1827 | // Type |
| 1828 | #define DxF0x3C_TYPE TYPE_D4F0 |
| 1829 | // Field Data |
| 1830 | #define DxF0x3C_IntLine_OFFSET 0 |
| 1831 | #define DxF0x3C_IntLine_WIDTH 8 |
| 1832 | #define DxF0x3C_IntLine_MASK 0xff |
| 1833 | #define DxF0x3C_IntPin_OFFSET 8 |
| 1834 | #define DxF0x3C_IntPin_WIDTH 3 |
| 1835 | #define DxF0x3C_IntPin_MASK 0x700 |
| 1836 | #define DxF0x3C_IntPinR_OFFSET 11 |
| 1837 | #define DxF0x3C_IntPinR_WIDTH 5 |
| 1838 | #define DxF0x3C_IntPinR_MASK 0xf800 |
| 1839 | #define DxF0x3C_ParityResponseEn_OFFSET 16 |
| 1840 | #define DxF0x3C_ParityResponseEn_WIDTH 1 |
| 1841 | #define DxF0x3C_ParityResponseEn_MASK 0x10000 |
| 1842 | #define DxF0x3C_SerrEn_OFFSET 17 |
| 1843 | #define DxF0x3C_SerrEn_WIDTH 1 |
| 1844 | #define DxF0x3C_SerrEn_MASK 0x20000 |
| 1845 | #define DxF0x3C_IsaEn_OFFSET 18 |
| 1846 | #define DxF0x3C_IsaEn_WIDTH 1 |
| 1847 | #define DxF0x3C_IsaEn_MASK 0x40000 |
| 1848 | #define DxF0x3C_VgaEn_OFFSET 19 |
| 1849 | #define DxF0x3C_VgaEn_WIDTH 1 |
| 1850 | #define DxF0x3C_VgaEn_MASK 0x80000 |
| 1851 | #define DxF0x3C_Vga16En_OFFSET 20 |
| 1852 | #define DxF0x3C_Vga16En_WIDTH 1 |
| 1853 | #define DxF0x3C_Vga16En_MASK 0x100000 |
| 1854 | #define DxF0x3C_MasterAbortMode_OFFSET 21 |
| 1855 | #define DxF0x3C_MasterAbortMode_WIDTH 1 |
| 1856 | #define DxF0x3C_MasterAbortMode_MASK 0x200000 |
| 1857 | #define DxF0x3C_SecondaryBusReset_OFFSET 22 |
| 1858 | #define DxF0x3C_SecondaryBusReset_WIDTH 1 |
| 1859 | #define DxF0x3C_SecondaryBusReset_MASK 0x400000 |
| 1860 | #define DxF0x3C_FastB2BCap_OFFSET 23 |
| 1861 | #define DxF0x3C_FastB2BCap_WIDTH 1 |
| 1862 | #define DxF0x3C_FastB2BCap_MASK 0x800000 |
| 1863 | #define DxF0x3C_Reserved_31_24_OFFSET 24 |
| 1864 | #define DxF0x3C_Reserved_31_24_WIDTH 8 |
| 1865 | #define DxF0x3C_Reserved_31_24_MASK 0xff000000 |
| 1866 | |
| 1867 | /// DxF0x3C |
| 1868 | typedef union { |
| 1869 | struct { ///< |
| 1870 | UINT32 IntLine:8 ; ///< |
| 1871 | UINT32 IntPin:3 ; ///< |
| 1872 | UINT32 IntPinR:5 ; ///< |
| 1873 | UINT32 ParityResponseEn:1 ; ///< |
| 1874 | UINT32 SerrEn:1 ; ///< |
| 1875 | UINT32 IsaEn:1 ; ///< |
| 1876 | UINT32 VgaEn:1 ; ///< |
| 1877 | UINT32 Vga16En:1 ; ///< |
| 1878 | UINT32 MasterAbortMode:1 ; ///< |
| 1879 | UINT32 SecondaryBusReset:1 ; ///< |
| 1880 | UINT32 FastB2BCap:1 ; ///< |
| 1881 | UINT32 Reserved_31_24:8 ; ///< |
| 1882 | } Field; ///< |
| 1883 | UINT32 Value; ///< |
| 1884 | } DxF0x3C_STRUCT; |
| 1885 | |
| 1886 | // **** DxF0x50 Register Definition **** |
| 1887 | // Address |
| 1888 | #define DxF0x50_ADDRESS 0x50 |
| 1889 | |
| 1890 | // Type |
| 1891 | #define DxF0x50_TYPE TYPE_D4F0 |
| 1892 | // Field Data |
| 1893 | #define DxF0x50_CapID_OFFSET 0 |
| 1894 | #define DxF0x50_CapID_WIDTH 8 |
| 1895 | #define DxF0x50_CapID_MASK 0xff |
| 1896 | #define DxF0x50_NextPtr_OFFSET 8 |
| 1897 | #define DxF0x50_NextPtr_WIDTH 8 |
| 1898 | #define DxF0x50_NextPtr_MASK 0xff00 |
| 1899 | #define DxF0x50_Version_OFFSET 16 |
| 1900 | #define DxF0x50_Version_WIDTH 3 |
| 1901 | #define DxF0x50_Version_MASK 0x70000 |
| 1902 | #define DxF0x50_PmeClock_OFFSET 19 |
| 1903 | #define DxF0x50_PmeClock_WIDTH 1 |
| 1904 | #define DxF0x50_PmeClock_MASK 0x80000 |
| 1905 | #define DxF0x50_Reserved_20_20_OFFSET 20 |
| 1906 | #define DxF0x50_Reserved_20_20_WIDTH 1 |
| 1907 | #define DxF0x50_Reserved_20_20_MASK 0x100000 |
| 1908 | #define DxF0x50_DevSpecificInit_OFFSET 21 |
| 1909 | #define DxF0x50_DevSpecificInit_WIDTH 1 |
| 1910 | #define DxF0x50_DevSpecificInit_MASK 0x200000 |
| 1911 | #define DxF0x50_AuxCurrent_OFFSET 22 |
| 1912 | #define DxF0x50_AuxCurrent_WIDTH 3 |
| 1913 | #define DxF0x50_AuxCurrent_MASK 0x1c00000 |
| 1914 | #define DxF0x50_D1Support_OFFSET 25 |
| 1915 | #define DxF0x50_D1Support_WIDTH 1 |
| 1916 | #define DxF0x50_D1Support_MASK 0x2000000 |
| 1917 | #define DxF0x50_D2Support_OFFSET 26 |
| 1918 | #define DxF0x50_D2Support_WIDTH 1 |
| 1919 | #define DxF0x50_D2Support_MASK 0x4000000 |
| 1920 | #define DxF0x50_PmeSupport_OFFSET 27 |
| 1921 | #define DxF0x50_PmeSupport_WIDTH 5 |
| 1922 | #define DxF0x50_PmeSupport_MASK 0xf8000000 |
| 1923 | |
| 1924 | /// DxF0x50 |
| 1925 | typedef union { |
| 1926 | struct { ///< |
| 1927 | UINT32 CapID:8 ; ///< |
| 1928 | UINT32 NextPtr:8 ; ///< |
| 1929 | UINT32 Version:3 ; ///< |
| 1930 | UINT32 PmeClock:1 ; ///< |
| 1931 | UINT32 Reserved_20_20:1 ; ///< |
| 1932 | UINT32 DevSpecificInit:1 ; ///< |
| 1933 | UINT32 AuxCurrent:3 ; ///< |
| 1934 | UINT32 D1Support:1 ; ///< |
| 1935 | UINT32 D2Support:1 ; ///< |
| 1936 | UINT32 PmeSupport:5 ; ///< |
| 1937 | } Field; ///< |
| 1938 | UINT32 Value; ///< |
| 1939 | } DxF0x50_STRUCT; |
| 1940 | |
| 1941 | // **** DxF0x54 Register Definition **** |
| 1942 | // Address |
| 1943 | #define DxF0x54_ADDRESS 0x54 |
| 1944 | |
| 1945 | // Type |
| 1946 | #define DxF0x54_TYPE TYPE_D4F0 |
| 1947 | // Field Data |
| 1948 | #define DxF0x54_PowerState_OFFSET 0 |
| 1949 | #define DxF0x54_PowerState_WIDTH 2 |
| 1950 | #define DxF0x54_PowerState_MASK 0x3 |
| 1951 | #define DxF0x54_Reserved_2_2_OFFSET 2 |
| 1952 | #define DxF0x54_Reserved_2_2_WIDTH 1 |
| 1953 | #define DxF0x54_Reserved_2_2_MASK 0x4 |
| 1954 | #define DxF0x54_NoSoftReset_OFFSET 3 |
| 1955 | #define DxF0x54_NoSoftReset_WIDTH 1 |
| 1956 | #define DxF0x54_NoSoftReset_MASK 0x8 |
| 1957 | #define DxF0x54_Reserved_7_4_OFFSET 4 |
| 1958 | #define DxF0x54_Reserved_7_4_WIDTH 4 |
| 1959 | #define DxF0x54_Reserved_7_4_MASK 0xf0 |
| 1960 | #define DxF0x54_PmeEn_OFFSET 8 |
| 1961 | #define DxF0x54_PmeEn_WIDTH 1 |
| 1962 | #define DxF0x54_PmeEn_MASK 0x100 |
| 1963 | #define DxF0x54_DataSelect_OFFSET 9 |
| 1964 | #define DxF0x54_DataSelect_WIDTH 4 |
| 1965 | #define DxF0x54_DataSelect_MASK 0x1e00 |
| 1966 | #define DxF0x54_DataScale_OFFSET 13 |
| 1967 | #define DxF0x54_DataScale_WIDTH 2 |
| 1968 | #define DxF0x54_DataScale_MASK 0x6000 |
| 1969 | #define DxF0x54_PmeStatus_OFFSET 15 |
| 1970 | #define DxF0x54_PmeStatus_WIDTH 1 |
| 1971 | #define DxF0x54_PmeStatus_MASK 0x8000 |
| 1972 | #define DxF0x54_Reserved_21_16_OFFSET 16 |
| 1973 | #define DxF0x54_Reserved_21_16_WIDTH 6 |
| 1974 | #define DxF0x54_Reserved_21_16_MASK 0x3f0000 |
| 1975 | #define DxF0x54_B2B3Support_OFFSET 22 |
| 1976 | #define DxF0x54_B2B3Support_WIDTH 1 |
| 1977 | #define DxF0x54_B2B3Support_MASK 0x400000 |
| 1978 | #define DxF0x54_BusPwrEn_OFFSET 23 |
| 1979 | #define DxF0x54_BusPwrEn_WIDTH 1 |
| 1980 | #define DxF0x54_BusPwrEn_MASK 0x800000 |
| 1981 | #define DxF0x54_PmeData_OFFSET 24 |
| 1982 | #define DxF0x54_PmeData_WIDTH 8 |
| 1983 | #define DxF0x54_PmeData_MASK 0xff000000 |
| 1984 | |
| 1985 | /// DxF0x54 |
| 1986 | typedef union { |
| 1987 | struct { ///< |
| 1988 | UINT32 PowerState:2 ; ///< |
| 1989 | UINT32 Reserved_2_2:1 ; ///< |
| 1990 | UINT32 NoSoftReset:1 ; ///< |
| 1991 | UINT32 Reserved_7_4:4 ; ///< |
| 1992 | UINT32 PmeEn:1 ; ///< |
| 1993 | UINT32 DataSelect:4 ; ///< |
| 1994 | UINT32 DataScale:2 ; ///< |
| 1995 | UINT32 PmeStatus:1 ; ///< |
| 1996 | UINT32 Reserved_21_16:6 ; ///< |
| 1997 | UINT32 B2B3Support:1 ; ///< |
| 1998 | UINT32 BusPwrEn:1 ; ///< |
| 1999 | UINT32 PmeData:8 ; ///< |
| 2000 | } Field; ///< |
| 2001 | UINT32 Value; ///< |
| 2002 | } DxF0x54_STRUCT; |
| 2003 | |
| 2004 | // **** DxF0x58 Register Definition **** |
| 2005 | // Address |
| 2006 | #define DxF0x58_ADDRESS 0x58 |
| 2007 | |
| 2008 | // Type |
| 2009 | #define DxF0x58_TYPE TYPE_D4F0 |
| 2010 | // Field Data |
| 2011 | #define DxF0x58_CapID_OFFSET 0 |
| 2012 | #define DxF0x58_CapID_WIDTH 8 |
| 2013 | #define DxF0x58_CapID_MASK 0xff |
| 2014 | #define DxF0x58_NextPtr_OFFSET 8 |
| 2015 | #define DxF0x58_NextPtr_WIDTH 8 |
| 2016 | #define DxF0x58_NextPtr_MASK 0xff00 |
| 2017 | #define DxF0x58_Version_OFFSET 16 |
| 2018 | #define DxF0x58_Version_WIDTH 4 |
| 2019 | #define DxF0x58_Version_MASK 0xf0000 |
| 2020 | #define DxF0x58_DeviceType_OFFSET 20 |
| 2021 | #define DxF0x58_DeviceType_WIDTH 4 |
| 2022 | #define DxF0x58_DeviceType_MASK 0xf00000 |
| 2023 | #define DxF0x58_SlotImplemented_OFFSET 24 |
| 2024 | #define DxF0x58_SlotImplemented_WIDTH 1 |
| 2025 | #define DxF0x58_SlotImplemented_MASK 0x1000000 |
| 2026 | #define DxF0x58_IntMessageNum_OFFSET 25 |
| 2027 | #define DxF0x58_IntMessageNum_WIDTH 5 |
| 2028 | #define DxF0x58_IntMessageNum_MASK 0x3e000000 |
| 2029 | #define DxF0x58_Reserved_31_30_OFFSET 30 |
| 2030 | #define DxF0x58_Reserved_31_30_WIDTH 2 |
| 2031 | #define DxF0x58_Reserved_31_30_MASK 0xc0000000 |
| 2032 | |
| 2033 | /// DxF0x58 |
| 2034 | typedef union { |
| 2035 | struct { ///< |
| 2036 | UINT32 CapID:8 ; ///< |
| 2037 | UINT32 NextPtr:8 ; ///< |
| 2038 | UINT32 Version:4 ; ///< |
| 2039 | UINT32 DeviceType:4 ; ///< |
| 2040 | UINT32 SlotImplemented:1 ; ///< |
| 2041 | UINT32 IntMessageNum:5 ; ///< |
| 2042 | UINT32 Reserved_31_30:2 ; ///< |
| 2043 | } Field; ///< |
| 2044 | UINT32 Value; ///< |
| 2045 | } DxF0x58_STRUCT; |
| 2046 | |
| 2047 | // **** DxF0x5C Register Definition **** |
| 2048 | // Address |
| 2049 | #define DxF0x5C_ADDRESS 0x5c |
| 2050 | |
| 2051 | // Type |
| 2052 | #define DxF0x5C_TYPE TYPE_D4F0 |
| 2053 | // Field Data |
| 2054 | #define DxF0x5C_MaxPayloadSupport_OFFSET 0 |
| 2055 | #define DxF0x5C_MaxPayloadSupport_WIDTH 3 |
| 2056 | #define DxF0x5C_MaxPayloadSupport_MASK 0x7 |
| 2057 | #define DxF0x5C_PhantomFunc_OFFSET 3 |
| 2058 | #define DxF0x5C_PhantomFunc_WIDTH 2 |
| 2059 | #define DxF0x5C_PhantomFunc_MASK 0x18 |
| 2060 | #define DxF0x5C_ExtendedTag_OFFSET 5 |
| 2061 | #define DxF0x5C_ExtendedTag_WIDTH 1 |
| 2062 | #define DxF0x5C_ExtendedTag_MASK 0x20 |
| 2063 | #define DxF0x5C_L0SAcceptableLatency_OFFSET 6 |
| 2064 | #define DxF0x5C_L0SAcceptableLatency_WIDTH 3 |
| 2065 | #define DxF0x5C_L0SAcceptableLatency_MASK 0x1c0 |
| 2066 | #define DxF0x5C_L1AcceptableLatency_OFFSET 9 |
| 2067 | #define DxF0x5C_L1AcceptableLatency_WIDTH 3 |
| 2068 | #define DxF0x5C_L1AcceptableLatency_MASK 0xe00 |
| 2069 | #define DxF0x5C_Reserved_14_12_OFFSET 12 |
| 2070 | #define DxF0x5C_Reserved_14_12_WIDTH 3 |
| 2071 | #define DxF0x5C_Reserved_14_12_MASK 0x7000 |
| 2072 | #define DxF0x5C_RoleBasedErrReporting_OFFSET 15 |
| 2073 | #define DxF0x5C_RoleBasedErrReporting_WIDTH 1 |
| 2074 | #define DxF0x5C_RoleBasedErrReporting_MASK 0x8000 |
| 2075 | #define DxF0x5C_Reserved_17_16_OFFSET 16 |
| 2076 | #define DxF0x5C_Reserved_17_16_WIDTH 2 |
| 2077 | #define DxF0x5C_Reserved_17_16_MASK 0x30000 |
| 2078 | #define DxF0x5C_CapturedSlotPowerLimit_OFFSET 18 |
| 2079 | #define DxF0x5C_CapturedSlotPowerLimit_WIDTH 8 |
| 2080 | #define DxF0x5C_CapturedSlotPowerLimit_MASK 0x3fc0000 |
| 2081 | #define DxF0x5C_CapturedSlotPowerScale_OFFSET 26 |
| 2082 | #define DxF0x5C_CapturedSlotPowerScale_WIDTH 2 |
| 2083 | #define DxF0x5C_CapturedSlotPowerScale_MASK 0xc000000 |
| 2084 | #define DxF0x5C_FlrCapable_OFFSET 28 |
| 2085 | #define DxF0x5C_FlrCapable_WIDTH 1 |
| 2086 | #define DxF0x5C_FlrCapable_MASK 0x10000000 |
| 2087 | #define DxF0x5C_Reserved_31_29_OFFSET 29 |
| 2088 | #define DxF0x5C_Reserved_31_29_WIDTH 3 |
| 2089 | #define DxF0x5C_Reserved_31_29_MASK 0xe0000000 |
| 2090 | |
| 2091 | /// DxF0x5C |
| 2092 | typedef union { |
| 2093 | struct { ///< |
| 2094 | UINT32 MaxPayloadSupport:3 ; ///< |
| 2095 | UINT32 PhantomFunc:2 ; ///< |
| 2096 | UINT32 ExtendedTag:1 ; ///< |
| 2097 | UINT32 L0SAcceptableLatency:3 ; ///< |
| 2098 | UINT32 L1AcceptableLatency:3 ; ///< |
| 2099 | UINT32 Reserved_14_12:3 ; ///< |
| 2100 | UINT32 RoleBasedErrReporting:1 ; ///< |
| 2101 | UINT32 Reserved_17_16:2 ; ///< |
| 2102 | UINT32 CapturedSlotPowerLimit:8 ; ///< |
| 2103 | UINT32 CapturedSlotPowerScale:2 ; ///< |
| 2104 | UINT32 FlrCapable:1 ; ///< |
| 2105 | UINT32 Reserved_31_29:3 ; ///< |
| 2106 | } Field; ///< |
| 2107 | UINT32 Value; ///< |
| 2108 | } DxF0x5C_STRUCT; |
| 2109 | |
| 2110 | // **** DxF0x60 Register Definition **** |
| 2111 | // Address |
| 2112 | #define DxF0x60_ADDRESS 0x60 |
| 2113 | |
| 2114 | // Type |
| 2115 | #define DxF0x60_TYPE TYPE_D4F0 |
| 2116 | // Field Data |
| 2117 | #define DxF0x60_CorrErrEn_OFFSET 0 |
| 2118 | #define DxF0x60_CorrErrEn_WIDTH 1 |
| 2119 | #define DxF0x60_CorrErrEn_MASK 0x1 |
| 2120 | #define DxF0x60_NonFatalErrEn_OFFSET 1 |
| 2121 | #define DxF0x60_NonFatalErrEn_WIDTH 1 |
| 2122 | #define DxF0x60_NonFatalErrEn_MASK 0x2 |
| 2123 | #define DxF0x60_FatalErrEn_OFFSET 2 |
| 2124 | #define DxF0x60_FatalErrEn_WIDTH 1 |
| 2125 | #define DxF0x60_FatalErrEn_MASK 0x4 |
| 2126 | #define DxF0x60_UsrReportEn_OFFSET 3 |
| 2127 | #define DxF0x60_UsrReportEn_WIDTH 1 |
| 2128 | #define DxF0x60_UsrReportEn_MASK 0x8 |
| 2129 | #define DxF0x60_RelaxedOrdEn_OFFSET 4 |
| 2130 | #define DxF0x60_RelaxedOrdEn_WIDTH 1 |
| 2131 | #define DxF0x60_RelaxedOrdEn_MASK 0x10 |
| 2132 | #define DxF0x60_MaxPayloadSize_OFFSET 5 |
| 2133 | #define DxF0x60_MaxPayloadSize_WIDTH 3 |
| 2134 | #define DxF0x60_MaxPayloadSize_MASK 0xe0 |
| 2135 | #define DxF0x60_ExtendedTagEn_OFFSET 8 |
| 2136 | #define DxF0x60_ExtendedTagEn_WIDTH 1 |
| 2137 | #define DxF0x60_ExtendedTagEn_MASK 0x100 |
| 2138 | #define DxF0x60_PhantomFuncEn_OFFSET 9 |
| 2139 | #define DxF0x60_PhantomFuncEn_WIDTH 1 |
| 2140 | #define DxF0x60_PhantomFuncEn_MASK 0x200 |
| 2141 | #define DxF0x60_AuxPowerPmEn_OFFSET 10 |
| 2142 | #define DxF0x60_AuxPowerPmEn_WIDTH 1 |
| 2143 | #define DxF0x60_AuxPowerPmEn_MASK 0x400 |
| 2144 | #define DxF0x60_NoSnoopEnable_OFFSET 11 |
| 2145 | #define DxF0x60_NoSnoopEnable_WIDTH 1 |
| 2146 | #define DxF0x60_NoSnoopEnable_MASK 0x800 |
| 2147 | #define DxF0x60_MaxRequestSize_OFFSET 12 |
| 2148 | #define DxF0x60_MaxRequestSize_WIDTH 3 |
| 2149 | #define DxF0x60_MaxRequestSize_MASK 0x7000 |
| 2150 | #define DxF0x60_BridgeCfgRetryEn_OFFSET 15 |
| 2151 | #define DxF0x60_BridgeCfgRetryEn_WIDTH 1 |
| 2152 | #define DxF0x60_BridgeCfgRetryEn_MASK 0x8000 |
| 2153 | #define DxF0x60_CorrErr_OFFSET 16 |
| 2154 | #define DxF0x60_CorrErr_WIDTH 1 |
| 2155 | #define DxF0x60_CorrErr_MASK 0x10000 |
| 2156 | #define DxF0x60_NonFatalErr_OFFSET 17 |
| 2157 | #define DxF0x60_NonFatalErr_WIDTH 1 |
| 2158 | #define DxF0x60_NonFatalErr_MASK 0x20000 |
| 2159 | #define DxF0x60_FatalErr_OFFSET 18 |
| 2160 | #define DxF0x60_FatalErr_WIDTH 1 |
| 2161 | #define DxF0x60_FatalErr_MASK 0x40000 |
| 2162 | #define DxF0x60_UsrDetected_OFFSET 19 |
| 2163 | #define DxF0x60_UsrDetected_WIDTH 1 |
| 2164 | #define DxF0x60_UsrDetected_MASK 0x80000 |
| 2165 | #define DxF0x60_AuxPwr_OFFSET 20 |
| 2166 | #define DxF0x60_AuxPwr_WIDTH 1 |
| 2167 | #define DxF0x60_AuxPwr_MASK 0x100000 |
| 2168 | #define DxF0x60_TransactionsPending_OFFSET 21 |
| 2169 | #define DxF0x60_TransactionsPending_WIDTH 1 |
| 2170 | #define DxF0x60_TransactionsPending_MASK 0x200000 |
| 2171 | #define DxF0x60_Reserved_31_22_OFFSET 22 |
| 2172 | #define DxF0x60_Reserved_31_22_WIDTH 10 |
| 2173 | #define DxF0x60_Reserved_31_22_MASK 0xffc00000 |
| 2174 | |
| 2175 | /// DxF0x60 |
| 2176 | typedef union { |
| 2177 | struct { ///< |
| 2178 | UINT32 CorrErrEn:1 ; ///< |
| 2179 | UINT32 NonFatalErrEn:1 ; ///< |
| 2180 | UINT32 FatalErrEn:1 ; ///< |
| 2181 | UINT32 UsrReportEn:1 ; ///< |
| 2182 | UINT32 RelaxedOrdEn:1 ; ///< |
| 2183 | UINT32 MaxPayloadSize:3 ; ///< |
| 2184 | UINT32 ExtendedTagEn:1 ; ///< |
| 2185 | UINT32 PhantomFuncEn:1 ; ///< |
| 2186 | UINT32 AuxPowerPmEn:1 ; ///< |
| 2187 | UINT32 NoSnoopEnable:1 ; ///< |
| 2188 | UINT32 MaxRequestSize:3 ; ///< |
| 2189 | UINT32 BridgeCfgRetryEn:1 ; ///< |
| 2190 | UINT32 CorrErr:1 ; ///< |
| 2191 | UINT32 NonFatalErr:1 ; ///< |
| 2192 | UINT32 FatalErr:1 ; ///< |
| 2193 | UINT32 UsrDetected:1 ; ///< |
| 2194 | UINT32 AuxPwr:1 ; ///< |
| 2195 | UINT32 TransactionsPending:1 ; ///< |
| 2196 | UINT32 Reserved_31_22:10; ///< |
| 2197 | } Field; ///< |
| 2198 | UINT32 Value; ///< |
| 2199 | } DxF0x60_STRUCT; |
| 2200 | |
| 2201 | |
| 2202 | // **** DxF0x68 Register Definition **** |
| 2203 | // Address |
| 2204 | #define DxF0x68_ADDRESS 0x68 |
| 2205 | |
| 2206 | // Type |
| 2207 | #define DxF0x68_TYPE TYPE_D4F0 |
| 2208 | // Field Data |
| 2209 | #define DxF0x68_PmControl_OFFSET 0 |
| 2210 | #define DxF0x68_PmControl_WIDTH 2 |
| 2211 | #define DxF0x68_PmControl_MASK 0x3 |
| 2212 | #define DxF0x68_Reserved_2_2_OFFSET 2 |
| 2213 | #define DxF0x68_Reserved_2_2_WIDTH 1 |
| 2214 | #define DxF0x68_Reserved_2_2_MASK 0x4 |
| 2215 | #define DxF0x68_ReadCplBoundary_OFFSET 3 |
| 2216 | #define DxF0x68_ReadCplBoundary_WIDTH 1 |
| 2217 | #define DxF0x68_ReadCplBoundary_MASK 0x8 |
| 2218 | #define DxF0x68_LinkDis_OFFSET 4 |
| 2219 | #define DxF0x68_LinkDis_WIDTH 1 |
| 2220 | #define DxF0x68_LinkDis_MASK 0x10 |
| 2221 | #define DxF0x68_RetrainLink_OFFSET 5 |
| 2222 | #define DxF0x68_RetrainLink_WIDTH 1 |
| 2223 | #define DxF0x68_RetrainLink_MASK 0x20 |
| 2224 | #define DxF0x68_CommonClockCfg_OFFSET 6 |
| 2225 | #define DxF0x68_CommonClockCfg_WIDTH 1 |
| 2226 | #define DxF0x68_CommonClockCfg_MASK 0x40 |
| 2227 | #define DxF0x68_ExtendedSync_OFFSET 7 |
| 2228 | #define DxF0x68_ExtendedSync_WIDTH 1 |
| 2229 | #define DxF0x68_ExtendedSync_MASK 0x80 |
| 2230 | #define DxF0x68_ClockPowerManagementEn_OFFSET 8 |
| 2231 | #define DxF0x68_ClockPowerManagementEn_WIDTH 1 |
| 2232 | #define DxF0x68_ClockPowerManagementEn_MASK 0x100 |
| 2233 | #define DxF0x68_HWAutonomousWidthDisable_OFFSET 9 |
| 2234 | #define DxF0x68_HWAutonomousWidthDisable_WIDTH 1 |
| 2235 | #define DxF0x68_HWAutonomousWidthDisable_MASK 0x200 |
| 2236 | #define DxF0x68_LinkBWManagementEn_OFFSET 10 |
| 2237 | #define DxF0x68_LinkBWManagementEn_WIDTH 1 |
| 2238 | #define DxF0x68_LinkBWManagementEn_MASK 0x400 |
| 2239 | #define DxF0x68_LinkAutonomousBWIntEn_OFFSET 11 |
| 2240 | #define DxF0x68_LinkAutonomousBWIntEn_WIDTH 1 |
| 2241 | #define DxF0x68_LinkAutonomousBWIntEn_MASK 0x800 |
| 2242 | #define DxF0x68_Reserved_15_12_OFFSET 12 |
| 2243 | #define DxF0x68_Reserved_15_12_WIDTH 4 |
| 2244 | #define DxF0x68_Reserved_15_12_MASK 0xf000 |
| 2245 | #define DxF0x68_LinkSpeed_OFFSET 16 |
| 2246 | #define DxF0x68_LinkSpeed_WIDTH 4 |
| 2247 | #define DxF0x68_LinkSpeed_MASK 0xf0000 |
| 2248 | #define DxF0x68_NegotiatedLinkWidth_OFFSET 20 |
| 2249 | #define DxF0x68_NegotiatedLinkWidth_WIDTH 6 |
| 2250 | #define DxF0x68_NegotiatedLinkWidth_MASK 0x3f00000 |
| 2251 | #define DxF0x68_Reserved_26_26_OFFSET 26 |
| 2252 | #define DxF0x68_Reserved_26_26_WIDTH 1 |
| 2253 | #define DxF0x68_Reserved_26_26_MASK 0x4000000 |
| 2254 | #define DxF0x68_LinkTraining_OFFSET 27 |
| 2255 | #define DxF0x68_LinkTraining_WIDTH 1 |
| 2256 | #define DxF0x68_LinkTraining_MASK 0x8000000 |
| 2257 | #define DxF0x68_SlotClockCfg_OFFSET 28 |
| 2258 | #define DxF0x68_SlotClockCfg_WIDTH 1 |
| 2259 | #define DxF0x68_SlotClockCfg_MASK 0x10000000 |
| 2260 | #define DxF0x68_DlActive_OFFSET 29 |
| 2261 | #define DxF0x68_DlActive_WIDTH 1 |
| 2262 | #define DxF0x68_DlActive_MASK 0x20000000 |
| 2263 | #define DxF0x68_LinkBWManagementStatus_OFFSET 30 |
| 2264 | #define DxF0x68_LinkBWManagementStatus_WIDTH 1 |
| 2265 | #define DxF0x68_LinkBWManagementStatus_MASK 0x40000000 |
| 2266 | #define DxF0x68_LinkAutonomousBWStatus_OFFSET 31 |
| 2267 | #define DxF0x68_LinkAutonomousBWStatus_WIDTH 1 |
| 2268 | #define DxF0x68_LinkAutonomousBWStatus_MASK 0x80000000 |
| 2269 | |
| 2270 | /// DxF0x68 |
| 2271 | typedef union { |
| 2272 | struct { ///< |
| 2273 | UINT32 PmControl:2 ; ///< |
| 2274 | UINT32 Reserved_2_2:1 ; ///< |
| 2275 | UINT32 ReadCplBoundary:1 ; ///< |
| 2276 | UINT32 LinkDis:1 ; ///< |
| 2277 | UINT32 RetrainLink:1 ; ///< |
| 2278 | UINT32 CommonClockCfg:1 ; ///< |
| 2279 | UINT32 ExtendedSync:1 ; ///< |
| 2280 | UINT32 ClockPowerManagementEn:1 ; ///< |
| 2281 | UINT32 HWAutonomousWidthDisable:1 ; ///< |
| 2282 | UINT32 LinkBWManagementEn:1 ; ///< |
| 2283 | UINT32 LinkAutonomousBWIntEn:1 ; ///< |
| 2284 | UINT32 Reserved_15_12:4 ; ///< |
| 2285 | UINT32 LinkSpeed:4 ; ///< |
| 2286 | UINT32 NegotiatedLinkWidth:6 ; ///< |
| 2287 | UINT32 Reserved_26_26:1 ; ///< |
| 2288 | UINT32 LinkTraining:1 ; ///< |
| 2289 | UINT32 SlotClockCfg:1 ; ///< |
| 2290 | UINT32 DlActive:1 ; ///< |
| 2291 | UINT32 LinkBWManagementStatus:1 ; ///< |
| 2292 | UINT32 LinkAutonomousBWStatus:1 ; ///< |
| 2293 | } Field; ///< |
| 2294 | UINT32 Value; ///< |
| 2295 | } DxF0x68_STRUCT; |
| 2296 | |
| 2297 | // **** DxF0x6C Register Definition **** |
| 2298 | // Address |
| 2299 | #define DxF0x6C_ADDRESS 0x6c |
| 2300 | |
| 2301 | // Type |
| 2302 | #define DxF0x6C_TYPE TYPE_D4F0 |
| 2303 | // Field Data |
| 2304 | #define DxF0x6C_AttnButtonPresent_OFFSET 0 |
| 2305 | #define DxF0x6C_AttnButtonPresent_WIDTH 1 |
| 2306 | #define DxF0x6C_AttnButtonPresent_MASK 0x1 |
| 2307 | #define DxF0x6C_PwrControllerPresent_OFFSET 1 |
| 2308 | #define DxF0x6C_PwrControllerPresent_WIDTH 1 |
| 2309 | #define DxF0x6C_PwrControllerPresent_MASK 0x2 |
| 2310 | #define DxF0x6C_MrlSensorPresent_OFFSET 2 |
| 2311 | #define DxF0x6C_MrlSensorPresent_WIDTH 1 |
| 2312 | #define DxF0x6C_MrlSensorPresent_MASK 0x4 |
| 2313 | #define DxF0x6C_AttnIndicatorPresent_OFFSET 3 |
| 2314 | #define DxF0x6C_AttnIndicatorPresent_WIDTH 1 |
| 2315 | #define DxF0x6C_AttnIndicatorPresent_MASK 0x8 |
| 2316 | #define DxF0x6C_PwrIndicatorPresent_OFFSET 4 |
| 2317 | #define DxF0x6C_PwrIndicatorPresent_WIDTH 1 |
| 2318 | #define DxF0x6C_PwrIndicatorPresent_MASK 0x10 |
| 2319 | #define DxF0x6C_HotplugSurprise_OFFSET 5 |
| 2320 | #define DxF0x6C_HotplugSurprise_WIDTH 1 |
| 2321 | #define DxF0x6C_HotplugSurprise_MASK 0x20 |
| 2322 | #define DxF0x6C_HotplugCapable_OFFSET 6 |
| 2323 | #define DxF0x6C_HotplugCapable_WIDTH 1 |
| 2324 | #define DxF0x6C_HotplugCapable_MASK 0x40 |
| 2325 | #define DxF0x6C_SlotPwrLimitValue_OFFSET 7 |
| 2326 | #define DxF0x6C_SlotPwrLimitValue_WIDTH 8 |
| 2327 | #define DxF0x6C_SlotPwrLimitValue_MASK 0x7f80 |
| 2328 | #define DxF0x6C_SlotPwrLimitScale_OFFSET 15 |
| 2329 | #define DxF0x6C_SlotPwrLimitScale_WIDTH 2 |
| 2330 | #define DxF0x6C_SlotPwrLimitScale_MASK 0x18000 |
| 2331 | #define DxF0x6C_ElecMechIlPresent_OFFSET 17 |
| 2332 | #define DxF0x6C_ElecMechIlPresent_WIDTH 1 |
| 2333 | #define DxF0x6C_ElecMechIlPresent_MASK 0x20000 |
| 2334 | #define DxF0x6C_NoCmdCplSupport_OFFSET 18 |
| 2335 | #define DxF0x6C_NoCmdCplSupport_WIDTH 1 |
| 2336 | #define DxF0x6C_NoCmdCplSupport_MASK 0x40000 |
| 2337 | #define DxF0x6C_PhysicalSlotNumber_OFFSET 19 |
| 2338 | #define DxF0x6C_PhysicalSlotNumber_WIDTH 13 |
| 2339 | #define DxF0x6C_PhysicalSlotNumber_MASK 0xfff80000 |
| 2340 | |
| 2341 | /// DxF0x6C |
| 2342 | typedef union { |
| 2343 | struct { ///< |
| 2344 | UINT32 AttnButtonPresent:1 ; ///< |
| 2345 | UINT32 PwrControllerPresent:1 ; ///< |
| 2346 | UINT32 MrlSensorPresent:1 ; ///< |
| 2347 | UINT32 AttnIndicatorPresent:1 ; ///< |
| 2348 | UINT32 PwrIndicatorPresent:1 ; ///< |
| 2349 | UINT32 HotplugSurprise:1 ; ///< |
| 2350 | UINT32 HotplugCapable:1 ; ///< |
| 2351 | UINT32 SlotPwrLimitValue:8 ; ///< |
| 2352 | UINT32 SlotPwrLimitScale:2 ; ///< |
| 2353 | UINT32 ElecMechIlPresent:1 ; ///< |
| 2354 | UINT32 NoCmdCplSupport:1 ; ///< |
| 2355 | UINT32 PhysicalSlotNumber:13; ///< |
| 2356 | } Field; ///< |
| 2357 | UINT32 Value; ///< |
| 2358 | } DxF0x6C_STRUCT; |
| 2359 | |
| 2360 | // **** DxF0x70 Register Definition **** |
| 2361 | // Address |
| 2362 | #define DxF0x70_ADDRESS 0x70 |
| 2363 | |
| 2364 | // Type |
| 2365 | #define DxF0x70_TYPE TYPE_D4F0 |
| 2366 | // Field Data |
| 2367 | #define DxF0x70_AttnButtonPressedEn_OFFSET 0 |
| 2368 | #define DxF0x70_AttnButtonPressedEn_WIDTH 1 |
| 2369 | #define DxF0x70_AttnButtonPressedEn_MASK 0x1 |
| 2370 | #define DxF0x70_PwrFaultDetectedEn_OFFSET 1 |
| 2371 | #define DxF0x70_PwrFaultDetectedEn_WIDTH 1 |
| 2372 | #define DxF0x70_PwrFaultDetectedEn_MASK 0x2 |
| 2373 | #define DxF0x70_MrlSensorChangedEn_OFFSET 2 |
| 2374 | #define DxF0x70_MrlSensorChangedEn_WIDTH 1 |
| 2375 | #define DxF0x70_MrlSensorChangedEn_MASK 0x4 |
| 2376 | #define DxF0x70_PresenceDetectChangedEn_OFFSET 3 |
| 2377 | #define DxF0x70_PresenceDetectChangedEn_WIDTH 1 |
| 2378 | #define DxF0x70_PresenceDetectChangedEn_MASK 0x8 |
| 2379 | #define DxF0x70_CmdCplIntrEn_OFFSET 4 |
| 2380 | #define DxF0x70_CmdCplIntrEn_WIDTH 1 |
| 2381 | #define DxF0x70_CmdCplIntrEn_MASK 0x10 |
| 2382 | #define DxF0x70_HotplugIntrEn_OFFSET 5 |
| 2383 | #define DxF0x70_HotplugIntrEn_WIDTH 1 |
| 2384 | #define DxF0x70_HotplugIntrEn_MASK 0x20 |
| 2385 | #define DxF0x70_AttnIndicatorControl_OFFSET 6 |
| 2386 | #define DxF0x70_AttnIndicatorControl_WIDTH 2 |
| 2387 | #define DxF0x70_AttnIndicatorControl_MASK 0xc0 |
| 2388 | #define DxF0x70_PwrIndicatorCntl_OFFSET 8 |
| 2389 | #define DxF0x70_PwrIndicatorCntl_WIDTH 2 |
| 2390 | #define DxF0x70_PwrIndicatorCntl_MASK 0x300 |
| 2391 | #define DxF0x70_PwrControllerCntl_OFFSET 10 |
| 2392 | #define DxF0x70_PwrControllerCntl_WIDTH 1 |
| 2393 | #define DxF0x70_PwrControllerCntl_MASK 0x400 |
| 2394 | #define DxF0x70_ElecMechIlCntl_OFFSET 11 |
| 2395 | #define DxF0x70_ElecMechIlCntl_WIDTH 1 |
| 2396 | #define DxF0x70_ElecMechIlCntl_MASK 0x800 |
| 2397 | #define DxF0x70_DlStateChangedEn_OFFSET 12 |
| 2398 | #define DxF0x70_DlStateChangedEn_WIDTH 1 |
| 2399 | #define DxF0x70_DlStateChangedEn_MASK 0x1000 |
| 2400 | #define DxF0x70_Reserved_15_13_OFFSET 13 |
| 2401 | #define DxF0x70_Reserved_15_13_WIDTH 3 |
| 2402 | #define DxF0x70_Reserved_15_13_MASK 0xe000 |
| 2403 | #define DxF0x70_AttnButtonPressed_OFFSET 16 |
| 2404 | #define DxF0x70_AttnButtonPressed_WIDTH 1 |
| 2405 | #define DxF0x70_AttnButtonPressed_MASK 0x10000 |
| 2406 | #define DxF0x70_PwrFaultDetected_OFFSET 17 |
| 2407 | #define DxF0x70_PwrFaultDetected_WIDTH 1 |
| 2408 | #define DxF0x70_PwrFaultDetected_MASK 0x20000 |
| 2409 | #define DxF0x70_MrlSensorChanged_OFFSET 18 |
| 2410 | #define DxF0x70_MrlSensorChanged_WIDTH 1 |
| 2411 | #define DxF0x70_MrlSensorChanged_MASK 0x40000 |
| 2412 | #define DxF0x70_PresenceDetectChanged_OFFSET 19 |
| 2413 | #define DxF0x70_PresenceDetectChanged_WIDTH 1 |
| 2414 | #define DxF0x70_PresenceDetectChanged_MASK 0x80000 |
| 2415 | #define DxF0x70_CmdCpl_OFFSET 20 |
| 2416 | #define DxF0x70_CmdCpl_WIDTH 1 |
| 2417 | #define DxF0x70_CmdCpl_MASK 0x100000 |
| 2418 | #define DxF0x70_MrlSensorState_OFFSET 21 |
| 2419 | #define DxF0x70_MrlSensorState_WIDTH 1 |
| 2420 | #define DxF0x70_MrlSensorState_MASK 0x200000 |
| 2421 | #define DxF0x70_PresenceDetectState_OFFSET 22 |
| 2422 | #define DxF0x70_PresenceDetectState_WIDTH 1 |
| 2423 | #define DxF0x70_PresenceDetectState_MASK 0x400000 |
| 2424 | #define DxF0x70_ElecMechIlSts_OFFSET 23 |
| 2425 | #define DxF0x70_ElecMechIlSts_WIDTH 1 |
| 2426 | #define DxF0x70_ElecMechIlSts_MASK 0x800000 |
| 2427 | #define DxF0x70_DlStateChanged_OFFSET 24 |
| 2428 | #define DxF0x70_DlStateChanged_WIDTH 1 |
| 2429 | #define DxF0x70_DlStateChanged_MASK 0x1000000 |
| 2430 | #define DxF0x70_Reserved_31_25_OFFSET 25 |
| 2431 | #define DxF0x70_Reserved_31_25_WIDTH 7 |
| 2432 | #define DxF0x70_Reserved_31_25_MASK 0xfe000000 |
| 2433 | |
| 2434 | /// DxF0x70 |
| 2435 | typedef union { |
| 2436 | struct { ///< |
| 2437 | UINT32 AttnButtonPressedEn:1 ; ///< |
| 2438 | UINT32 PwrFaultDetectedEn:1 ; ///< |
| 2439 | UINT32 MrlSensorChangedEn:1 ; ///< |
| 2440 | UINT32 PresenceDetectChangedEn:1 ; ///< |
| 2441 | UINT32 CmdCplIntrEn:1 ; ///< |
| 2442 | UINT32 HotplugIntrEn:1 ; ///< |
| 2443 | UINT32 AttnIndicatorControl:2 ; ///< |
| 2444 | UINT32 PwrIndicatorCntl:2 ; ///< |
| 2445 | UINT32 PwrControllerCntl:1 ; ///< |
| 2446 | UINT32 ElecMechIlCntl:1 ; ///< |
| 2447 | UINT32 DlStateChangedEn:1 ; ///< |
| 2448 | UINT32 Reserved_15_13:3 ; ///< |
| 2449 | UINT32 AttnButtonPressed:1 ; ///< |
| 2450 | UINT32 PwrFaultDetected:1 ; ///< |
| 2451 | UINT32 MrlSensorChanged:1 ; ///< |
| 2452 | UINT32 PresenceDetectChanged:1 ; ///< |
| 2453 | UINT32 CmdCpl:1 ; ///< |
| 2454 | UINT32 MrlSensorState:1 ; ///< |
| 2455 | UINT32 PresenceDetectState:1 ; ///< |
| 2456 | UINT32 ElecMechIlSts:1 ; ///< |
| 2457 | UINT32 DlStateChanged:1 ; ///< |
| 2458 | UINT32 Reserved_31_25:7 ; ///< |
| 2459 | } Field; ///< |
| 2460 | UINT32 Value; ///< |
| 2461 | } DxF0x70_STRUCT; |
| 2462 | |
| 2463 | // **** DxF0x74 Register Definition **** |
| 2464 | // Address |
| 2465 | #define DxF0x74_ADDRESS 0x74 |
| 2466 | |
| 2467 | // Type |
| 2468 | #define DxF0x74_TYPE TYPE_D4F0 |
| 2469 | // Field Data |
| 2470 | #define DxF0x74_SerrOnCorrErrEn_OFFSET 0 |
| 2471 | #define DxF0x74_SerrOnCorrErrEn_WIDTH 1 |
| 2472 | #define DxF0x74_SerrOnCorrErrEn_MASK 0x1 |
| 2473 | #define DxF0x74_SerrOnNonFatalErrEn_OFFSET 1 |
| 2474 | #define DxF0x74_SerrOnNonFatalErrEn_WIDTH 1 |
| 2475 | #define DxF0x74_SerrOnNonFatalErrEn_MASK 0x2 |
| 2476 | #define DxF0x74_SerrOnFatalErrEn_OFFSET 2 |
| 2477 | #define DxF0x74_SerrOnFatalErrEn_WIDTH 1 |
| 2478 | #define DxF0x74_SerrOnFatalErrEn_MASK 0x4 |
| 2479 | #define DxF0x74_PmIntEn_OFFSET 3 |
| 2480 | #define DxF0x74_PmIntEn_WIDTH 1 |
| 2481 | #define DxF0x74_PmIntEn_MASK 0x8 |
| 2482 | #define DxF0x74_CrsSoftVisibilityEn_OFFSET 4 |
| 2483 | #define DxF0x74_CrsSoftVisibilityEn_WIDTH 1 |
| 2484 | #define DxF0x74_CrsSoftVisibilityEn_MASK 0x10 |
| 2485 | #define DxF0x74_Reserved_15_5_OFFSET 5 |
| 2486 | #define DxF0x74_Reserved_15_5_WIDTH 11 |
| 2487 | #define DxF0x74_Reserved_15_5_MASK 0xffe0 |
| 2488 | #define DxF0x74_CrsSoftVisibility_OFFSET 16 |
| 2489 | #define DxF0x74_CrsSoftVisibility_WIDTH 1 |
| 2490 | #define DxF0x74_CrsSoftVisibility_MASK 0x10000 |
| 2491 | #define DxF0x74_Reserved_31_17_OFFSET 17 |
| 2492 | #define DxF0x74_Reserved_31_17_WIDTH 15 |
| 2493 | #define DxF0x74_Reserved_31_17_MASK 0xfffe0000 |
| 2494 | |
| 2495 | /// DxF0x74 |
| 2496 | typedef union { |
| 2497 | struct { ///< |
| 2498 | UINT32 SerrOnCorrErrEn:1 ; ///< |
| 2499 | UINT32 SerrOnNonFatalErrEn:1 ; ///< |
| 2500 | UINT32 SerrOnFatalErrEn:1 ; ///< |
| 2501 | UINT32 PmIntEn:1 ; ///< |
| 2502 | UINT32 CrsSoftVisibilityEn:1 ; ///< |
| 2503 | UINT32 Reserved_15_5:11; ///< |
| 2504 | UINT32 CrsSoftVisibility:1 ; ///< |
| 2505 | UINT32 Reserved_31_17:15; ///< |
| 2506 | } Field; ///< |
| 2507 | UINT32 Value; ///< |
| 2508 | } DxF0x74_STRUCT; |
| 2509 | |
| 2510 | // **** DxF0x78 Register Definition **** |
| 2511 | // Address |
| 2512 | #define DxF0x78_ADDRESS 0x78 |
| 2513 | |
| 2514 | // Type |
| 2515 | #define DxF0x78_TYPE TYPE_D4F0 |
| 2516 | // Field Data |
| 2517 | #define DxF0x78_PmeRequestorId_OFFSET 0 |
| 2518 | #define DxF0x78_PmeRequestorId_WIDTH 16 |
| 2519 | #define DxF0x78_PmeRequestorId_MASK 0xffff |
| 2520 | #define DxF0x78_PmeStatus_OFFSET 16 |
| 2521 | #define DxF0x78_PmeStatus_WIDTH 1 |
| 2522 | #define DxF0x78_PmeStatus_MASK 0x10000 |
| 2523 | #define DxF0x78_PmePending_OFFSET 17 |
| 2524 | #define DxF0x78_PmePending_WIDTH 1 |
| 2525 | #define DxF0x78_PmePending_MASK 0x20000 |
| 2526 | #define DxF0x78_Reserved_31_18_OFFSET 18 |
| 2527 | #define DxF0x78_Reserved_31_18_WIDTH 14 |
| 2528 | #define DxF0x78_Reserved_31_18_MASK 0xfffc0000 |
| 2529 | |
| 2530 | /// DxF0x78 |
| 2531 | typedef union { |
| 2532 | struct { ///< |
| 2533 | UINT32 PmeRequestorId:16; ///< |
| 2534 | UINT32 PmeStatus:1 ; ///< |
| 2535 | UINT32 PmePending:1 ; ///< |
| 2536 | UINT32 Reserved_31_18:14; ///< |
| 2537 | } Field; ///< |
| 2538 | UINT32 Value; ///< |
| 2539 | } DxF0x78_STRUCT; |
| 2540 | |
| 2541 | // **** DxF0x7C Register Definition **** |
| 2542 | // Address |
| 2543 | #define DxF0x7C_ADDRESS 0x7c |
| 2544 | |
| 2545 | // Type |
| 2546 | #define DxF0x7C_TYPE TYPE_D4F0 |
| 2547 | // Field Data |
| 2548 | #define DxF0x7C_CplTimeoutRangeSup_OFFSET 0 |
| 2549 | #define DxF0x7C_CplTimeoutRangeSup_WIDTH 4 |
| 2550 | #define DxF0x7C_CplTimeoutRangeSup_MASK 0xf |
| 2551 | #define DxF0x7C_CplTimeoutDisSup_OFFSET 4 |
| 2552 | #define DxF0x7C_CplTimeoutDisSup_WIDTH 1 |
| 2553 | #define DxF0x7C_CplTimeoutDisSup_MASK 0x10 |
| 2554 | #define DxF0x7C_AriForwardingSupported_OFFSET 5 |
| 2555 | #define DxF0x7C_AriForwardingSupported_WIDTH 1 |
| 2556 | #define DxF0x7C_AriForwardingSupported_MASK 0x20 |
| 2557 | #define DxF0x7C_Reserved_31_6_OFFSET 6 |
| 2558 | #define DxF0x7C_Reserved_31_6_WIDTH 26 |
| 2559 | #define DxF0x7C_Reserved_31_6_MASK 0xffffffc0 |
| 2560 | |
| 2561 | /// DxF0x7C |
| 2562 | typedef union { |
| 2563 | struct { ///< |
| 2564 | UINT32 CplTimeoutRangeSup:4 ; ///< |
| 2565 | UINT32 CplTimeoutDisSup:1 ; ///< |
| 2566 | UINT32 AriForwardingSupported:1 ; ///< |
| 2567 | UINT32 Reserved_31_6:26; ///< |
| 2568 | } Field; ///< |
| 2569 | UINT32 Value; ///< |
| 2570 | } DxF0x7C_STRUCT; |
| 2571 | |
| 2572 | // **** DxF0x80 Register Definition **** |
| 2573 | // Address |
| 2574 | #define DxF0x80_ADDRESS 0x80 |
| 2575 | |
| 2576 | // Type |
| 2577 | #define DxF0x80_TYPE TYPE_D4F0 |
| 2578 | // Field Data |
| 2579 | #define DxF0x80_CplTimeoutValue_OFFSET 0 |
| 2580 | #define DxF0x80_CplTimeoutValue_WIDTH 4 |
| 2581 | #define DxF0x80_CplTimeoutValue_MASK 0xf |
| 2582 | #define DxF0x80_CplTimeoutDis_OFFSET 4 |
| 2583 | #define DxF0x80_CplTimeoutDis_WIDTH 1 |
| 2584 | #define DxF0x80_CplTimeoutDis_MASK 0x10 |
| 2585 | #define DxF0x80_AriForwardingEn_OFFSET 5 |
| 2586 | #define DxF0x80_AriForwardingEn_WIDTH 1 |
| 2587 | #define DxF0x80_AriForwardingEn_MASK 0x20 |
| 2588 | #define DxF0x80_Reserved_31_6_OFFSET 6 |
| 2589 | #define DxF0x80_Reserved_31_6_WIDTH 26 |
| 2590 | #define DxF0x80_Reserved_31_6_MASK 0xffffffc0 |
| 2591 | |
| 2592 | /// DxF0x80 |
| 2593 | typedef union { |
| 2594 | struct { ///< |
| 2595 | UINT32 CplTimeoutValue:4 ; ///< |
| 2596 | UINT32 CplTimeoutDis:1 ; ///< |
| 2597 | UINT32 AriForwardingEn:1 ; ///< |
| 2598 | UINT32 Reserved_31_6:26; ///< |
| 2599 | } Field; ///< |
| 2600 | UINT32 Value; ///< |
| 2601 | } DxF0x80_STRUCT; |
| 2602 | |
| 2603 | // **** DxF0x84 Register Definition **** |
| 2604 | // Address |
| 2605 | #define DxF0x84_ADDRESS 0x84 |
| 2606 | |
| 2607 | // Type |
| 2608 | #define DxF0x84_TYPE TYPE_D4F0 |
| 2609 | // Field Data |
| 2610 | #define DxF0x84_Reserved_31_0_OFFSET 0 |
| 2611 | #define DxF0x84_Reserved_31_0_WIDTH 32 |
| 2612 | #define DxF0x84_Reserved_31_0_MASK 0xffffffff |
| 2613 | |
| 2614 | /// DxF0x84 |
| 2615 | typedef union { |
| 2616 | struct { ///< |
| 2617 | UINT32 Reserved_31_0:32; ///< |
| 2618 | } Field; ///< |
| 2619 | UINT32 Value; ///< |
| 2620 | } DxF0x84_STRUCT; |
| 2621 | |
| 2622 | // **** DxF0x88 Register Definition **** |
| 2623 | // Address |
| 2624 | #define DxF0x88_ADDRESS 0x88 |
| 2625 | |
| 2626 | // Type |
| 2627 | #define DxF0x88_TYPE TYPE_D4F0 |
| 2628 | // Field Data |
| 2629 | #define DxF0x88_TargetLinkSpeed_OFFSET 0 |
| 2630 | #define DxF0x88_TargetLinkSpeed_WIDTH 4 |
| 2631 | #define DxF0x88_TargetLinkSpeed_MASK 0xf |
| 2632 | #define DxF0x88_EnterCompliance_OFFSET 4 |
| 2633 | #define DxF0x88_EnterCompliance_WIDTH 1 |
| 2634 | #define DxF0x88_EnterCompliance_MASK 0x10 |
| 2635 | #define DxF0x88_HwAutonomousSpeedDisable_OFFSET 5 |
| 2636 | #define DxF0x88_HwAutonomousSpeedDisable_WIDTH 1 |
| 2637 | #define DxF0x88_HwAutonomousSpeedDisable_MASK 0x20 |
| 2638 | #define DxF0x88_SelectableDeemphasis_OFFSET 6 |
| 2639 | #define DxF0x88_SelectableDeemphasis_WIDTH 1 |
| 2640 | #define DxF0x88_SelectableDeemphasis_MASK 0x40 |
| 2641 | #define DxF0x88_XmitMargin_OFFSET 7 |
| 2642 | #define DxF0x88_XmitMargin_WIDTH 3 |
| 2643 | #define DxF0x88_XmitMargin_MASK 0x380 |
| 2644 | #define DxF0x88_EnterModCompliance_OFFSET 10 |
| 2645 | #define DxF0x88_EnterModCompliance_WIDTH 1 |
| 2646 | #define DxF0x88_EnterModCompliance_MASK 0x400 |
| 2647 | #define DxF0x88_ComplianceSOS_OFFSET 11 |
| 2648 | #define DxF0x88_ComplianceSOS_WIDTH 1 |
| 2649 | #define DxF0x88_ComplianceSOS_MASK 0x800 |
| 2650 | #define DxF0x88_ComplianceDeemphasis_OFFSET 12 |
| 2651 | #define DxF0x88_ComplianceDeemphasis_WIDTH 1 |
| 2652 | #define DxF0x88_ComplianceDeemphasis_MASK 0x1000 |
| 2653 | #define DxF0x88_Reserved_15_13_OFFSET 13 |
| 2654 | #define DxF0x88_Reserved_15_13_WIDTH 3 |
| 2655 | #define DxF0x88_Reserved_15_13_MASK 0xe000 |
| 2656 | #define DxF0x88_CurDeemphasisLevel_OFFSET 16 |
| 2657 | #define DxF0x88_CurDeemphasisLevel_WIDTH 1 |
| 2658 | #define DxF0x88_CurDeemphasisLevel_MASK 0x10000 |
| 2659 | #define DxF0x88_Reserved_31_17_OFFSET 17 |
| 2660 | #define DxF0x88_Reserved_31_17_WIDTH 15 |
| 2661 | #define DxF0x88_Reserved_31_17_MASK 0xfffe0000 |
| 2662 | |
| 2663 | /// DxF0x88 |
| 2664 | typedef union { |
| 2665 | struct { ///< |
| 2666 | UINT32 TargetLinkSpeed:4 ; ///< |
| 2667 | UINT32 EnterCompliance:1 ; ///< |
| 2668 | UINT32 HwAutonomousSpeedDisable:1 ; ///< |
| 2669 | UINT32 SelectableDeemphasis:1 ; ///< |
| 2670 | UINT32 XmitMargin:3 ; ///< |
| 2671 | UINT32 EnterModCompliance:1 ; ///< |
| 2672 | UINT32 ComplianceSOS:1 ; ///< |
| 2673 | UINT32 ComplianceDeemphasis:1 ; ///< |
| 2674 | UINT32 Reserved_15_13:3 ; ///< |
| 2675 | UINT32 CurDeemphasisLevel:1 ; ///< |
| 2676 | UINT32 Reserved_31_17:15; ///< |
| 2677 | } Field; ///< |
| 2678 | UINT32 Value; ///< |
| 2679 | } DxF0x88_STRUCT; |
| 2680 | |
| 2681 | // **** DxF0x8C Register Definition **** |
| 2682 | // Address |
| 2683 | #define DxF0x8C_ADDRESS 0x8c |
| 2684 | |
| 2685 | // Type |
| 2686 | #define DxF0x8C_TYPE TYPE_D4F0 |
| 2687 | // Field Data |
| 2688 | #define DxF0x8C_Reserved_31_0_OFFSET 0 |
| 2689 | #define DxF0x8C_Reserved_31_0_WIDTH 32 |
| 2690 | #define DxF0x8C_Reserved_31_0_MASK 0xffffffff |
| 2691 | |
| 2692 | /// DxF0x8C |
| 2693 | typedef union { |
| 2694 | struct { ///< |
| 2695 | UINT32 Reserved_31_0:32; ///< |
| 2696 | } Field; ///< |
| 2697 | UINT32 Value; ///< |
| 2698 | } DxF0x8C_STRUCT; |
| 2699 | |
| 2700 | // **** DxF0x90 Register Definition **** |
| 2701 | // Address |
| 2702 | #define DxF0x90_ADDRESS 0x90 |
| 2703 | |
| 2704 | // Type |
| 2705 | #define DxF0x90_TYPE TYPE_D4F0 |
| 2706 | // Field Data |
| 2707 | #define DxF0x90_Reserved_31_0_OFFSET 0 |
| 2708 | #define DxF0x90_Reserved_31_0_WIDTH 32 |
| 2709 | #define DxF0x90_Reserved_31_0_MASK 0xffffffff |
| 2710 | |
| 2711 | /// DxF0x90 |
| 2712 | typedef union { |
| 2713 | struct { ///< |
| 2714 | UINT32 Reserved_31_0:32; ///< |
| 2715 | } Field; ///< |
| 2716 | UINT32 Value; ///< |
| 2717 | } DxF0x90_STRUCT; |
| 2718 | |
| 2719 | // **** DxF0x128 Register Definition **** |
| 2720 | // Address |
| 2721 | #define DxF0x128_ADDRESS 0x128 |
| 2722 | |
| 2723 | // Type |
| 2724 | #define DxF0x128_TYPE TYPE_D4F0 |
| 2725 | // Field Data |
| 2726 | #define DxF0x128_Reserved_15_0_OFFSET 0 |
| 2727 | #define DxF0x128_Reserved_15_0_WIDTH 16 |
| 2728 | #define DxF0x128_Reserved_15_0_MASK 0xffff |
| 2729 | #define DxF0x128_PortArbTableStatus_OFFSET 16 |
| 2730 | #define DxF0x128_PortArbTableStatus_WIDTH 1 |
| 2731 | #define DxF0x128_PortArbTableStatus_MASK 0x10000 |
| 2732 | #define DxF0x128_VcNegotiationPending_OFFSET 17 |
| 2733 | #define DxF0x128_VcNegotiationPending_WIDTH 1 |
| 2734 | #define DxF0x128_VcNegotiationPending_MASK 0x20000 |
| 2735 | #define DxF0x128_Reserved_31_18_OFFSET 18 |
| 2736 | #define DxF0x128_Reserved_31_18_WIDTH 14 |
| 2737 | #define DxF0x128_Reserved_31_18_MASK 0xfffc0000 |
| 2738 | |
| 2739 | /// DxF0x128 |
| 2740 | typedef union { |
| 2741 | struct { ///< |
| 2742 | UINT32 Reserved_15_0:16; ///< |
| 2743 | UINT32 PortArbTableStatus:1 ; ///< |
| 2744 | UINT32 VcNegotiationPending:1 ; ///< |
| 2745 | UINT32 Reserved_31_18:14; ///< |
| 2746 | } Field; ///< |
| 2747 | UINT32 Value; ///< |
| 2748 | } DxF0x128_STRUCT; |
| 2749 | |
| 2750 | |
| 2751 | |
| 2752 | |
| 2753 | |
| 2754 | |
| 2755 | |
| 2756 | |
| 2757 | |
| 2758 | |
| 2759 | |
| 2760 | |
| 2761 | |
| 2762 | |
| 2763 | |
| 2764 | |
| 2765 | // **** D0F0x64_x00 Register Definition **** |
| 2766 | // Address |
| 2767 | #define D0F0x64_x00_ADDRESS 0x0 |
| 2768 | |
| 2769 | // Type |
| 2770 | #define D0F0x64_x00_TYPE TYPE_D0F0x64 |
| 2771 | // Field Data |
| 2772 | #define D0F0x64_x00_Reserved_5_0_OFFSET 0 |
| 2773 | #define D0F0x64_x00_Reserved_5_0_WIDTH 6 |
| 2774 | #define D0F0x64_x00_Reserved_5_0_MASK 0x3f |
| 2775 | #define D0F0x64_x00_NbFchCfgEn_OFFSET 6 |
| 2776 | #define D0F0x64_x00_NbFchCfgEn_WIDTH 1 |
| 2777 | #define D0F0x64_x00_NbFchCfgEn_MASK 0x40 |
| 2778 | #define D0F0x64_x00_HwInitWrLock_OFFSET 7 |
| 2779 | #define D0F0x64_x00_HwInitWrLock_WIDTH 1 |
| 2780 | #define D0F0x64_x00_HwInitWrLock_MASK 0x80 |
| 2781 | #define D0F0x64_x00_Reserved_31_8_OFFSET 8 |
| 2782 | #define D0F0x64_x00_Reserved_31_8_WIDTH 24 |
| 2783 | #define D0F0x64_x00_Reserved_31_8_MASK 0xffffff00 |
| 2784 | |
| 2785 | /// D0F0x64_x00 |
| 2786 | typedef union { |
| 2787 | struct { ///< |
| 2788 | UINT32 Reserved_5_0:6 ; ///< |
| 2789 | UINT32 NbFchCfgEn:1 ; ///< |
| 2790 | UINT32 HwInitWrLock:1 ; ///< |
| 2791 | UINT32 Reserved_31_8:24; ///< |
| 2792 | } Field; ///< |
| 2793 | UINT32 Value; ///< |
| 2794 | } D0F0x64_x00_STRUCT; |
| 2795 | |
| 2796 | // **** D0F0x64_x0B Register Definition **** |
| 2797 | // Address |
| 2798 | #define D0F0x64_x0B_ADDRESS 0xb |
| 2799 | |
| 2800 | // Type |
| 2801 | #define D0F0x64_x0B_TYPE TYPE_D0F0x64 |
| 2802 | // Field Data |
| 2803 | #define D0F0x64_x0B_Reserved_19_0_OFFSET 0 |
| 2804 | #define D0F0x64_x0B_Reserved_19_0_WIDTH 20 |
| 2805 | #define D0F0x64_x0B_Reserved_19_0_MASK 0xfffff |
| 2806 | #define D0F0x64_x0B_SetPowEn_OFFSET 20 |
| 2807 | #define D0F0x64_x0B_SetPowEn_WIDTH 1 |
| 2808 | #define D0F0x64_x0B_SetPowEn_MASK 0x100000 |
| 2809 | #define D0F0x64_x0B_IocFchSetPowEn_OFFSET 21 |
| 2810 | #define D0F0x64_x0B_IocFchSetPowEn_WIDTH 1 |
| 2811 | #define D0F0x64_x0B_IocFchSetPowEn_MASK 0x200000 |
| 2812 | #define D0F0x64_x0B_Reserved_22_22_OFFSET 22 |
| 2813 | #define D0F0x64_x0B_Reserved_22_22_WIDTH 1 |
| 2814 | #define D0F0x64_x0B_Reserved_22_22_MASK 0x400000 |
| 2815 | #define D0F0x64_x0B_IocFchSetPmeTurnOffEn_OFFSET 23 |
| 2816 | #define D0F0x64_x0B_IocFchSetPmeTurnOffEn_WIDTH 1 |
| 2817 | #define D0F0x64_x0B_IocFchSetPmeTurnOffEn_MASK 0x800000 |
| 2818 | #define D0F0x64_x0B_Reserved_31_24_OFFSET 24 |
| 2819 | #define D0F0x64_x0B_Reserved_31_24_WIDTH 8 |
| 2820 | #define D0F0x64_x0B_Reserved_31_24_MASK 0xff000000 |
| 2821 | |
| 2822 | /// D0F0x64_x0B |
| 2823 | typedef union { |
| 2824 | struct { ///< |
| 2825 | UINT32 Reserved_19_0:20; ///< |
| 2826 | UINT32 SetPowEn:1 ; ///< |
| 2827 | UINT32 IocFchSetPowEn:1 ; ///< |
| 2828 | UINT32 Reserved_22_22:1 ; ///< |
| 2829 | UINT32 IocFchSetPmeTurnOffEn:1 ; ///< |
| 2830 | UINT32 Reserved_31_24:8 ; ///< |
| 2831 | } Field; ///< |
| 2832 | UINT32 Value; ///< |
| 2833 | } D0F0x64_x0B_STRUCT; |
| 2834 | |
| 2835 | // **** D0F0x64_x0C Register Definition **** |
| 2836 | // Address |
| 2837 | #define D0F0x64_x0C_ADDRESS 0xc |
| 2838 | |
| 2839 | // Type |
| 2840 | #define D0F0x64_x0C_TYPE TYPE_D0F0x64 |
| 2841 | // Field Data |
| 2842 | #define D0F0x64_x0C_Reserved_1_0_OFFSET 0 |
| 2843 | #define D0F0x64_x0C_Reserved_1_0_WIDTH 2 |
| 2844 | #define D0F0x64_x0C_Reserved_1_0_MASK 0x3 |
| 2845 | #define D0F0x64_x0C_Dev2BridgeDis_OFFSET 2 |
| 2846 | #define D0F0x64_x0C_Dev2BridgeDis_WIDTH 1 |
| 2847 | #define D0F0x64_x0C_Dev2BridgeDis_MASK 0x4 |
| 2848 | #define D0F0x64_x0C_Dev3BridgeDis_OFFSET 3 |
| 2849 | #define D0F0x64_x0C_Dev3BridgeDis_WIDTH 1 |
| 2850 | #define D0F0x64_x0C_Dev3BridgeDis_MASK 0x8 |
| 2851 | #define D0F0x64_x0C_Dev4BridgeDis_OFFSET 4 |
| 2852 | #define D0F0x64_x0C_Dev4BridgeDis_WIDTH 1 |
| 2853 | #define D0F0x64_x0C_Dev4BridgeDis_MASK 0x10 |
| 2854 | #define D0F0x64_x0C_Dev5BridgeDis_OFFSET 5 |
| 2855 | #define D0F0x64_x0C_Dev5BridgeDis_WIDTH 1 |
| 2856 | #define D0F0x64_x0C_Dev5BridgeDis_MASK 0x20 |
| 2857 | #define D0F0x64_x0C_Dev6BridgeDis_OFFSET 6 |
| 2858 | #define D0F0x64_x0C_Dev6BridgeDis_WIDTH 1 |
| 2859 | #define D0F0x64_x0C_Dev6BridgeDis_MASK 0x40 |
| 2860 | #define D0F0x64_x0C_Dev7BridgeDis_OFFSET 7 |
| 2861 | #define D0F0x64_x0C_Dev7BridgeDis_WIDTH 1 |
| 2862 | #define D0F0x64_x0C_Dev7BridgeDis_MASK 0x80 |
| 2863 | #define D0F0x64_x0C_Reserved_31_8_OFFSET 8 |
| 2864 | #define D0F0x64_x0C_Reserved_31_8_WIDTH 24 |
| 2865 | #define D0F0x64_x0C_Reserved_31_8_MASK 0xffffff00 |
| 2866 | |
| 2867 | /// D0F0x64_x0C |
| 2868 | typedef union { |
| 2869 | struct { ///< |
| 2870 | UINT32 Reserved_1_0:2 ; ///< |
| 2871 | UINT32 Dev2BridgeDis:1 ; ///< |
| 2872 | UINT32 Dev3BridgeDis:1 ; ///< |
| 2873 | UINT32 Dev4BridgeDis:1 ; ///< |
| 2874 | UINT32 Dev5BridgeDis:1 ; ///< |
| 2875 | UINT32 Dev6BridgeDis:1 ; ///< |
| 2876 | UINT32 Dev7BridgeDis:1 ; ///< |
| 2877 | UINT32 Reserved_31_8:24; ///< |
| 2878 | } Field; ///< |
| 2879 | UINT32 Value; ///< |
| 2880 | } D0F0x64_x0C_STRUCT; |
| 2881 | |
| 2882 | // **** D0F0x64_x19 Register Definition **** |
| 2883 | // Address |
| 2884 | #define D0F0x64_x19_ADDRESS 0x19 |
| 2885 | |
| 2886 | // Type |
| 2887 | #define D0F0x64_x19_TYPE TYPE_D0F0x64 |
| 2888 | // Field Data |
| 2889 | #define D0F0x64_x19_TomEn_OFFSET 0 |
| 2890 | #define D0F0x64_x19_TomEn_WIDTH 1 |
| 2891 | #define D0F0x64_x19_TomEn_MASK 0x1 |
| 2892 | #define D0F0x64_x19_Reserved_22_1_OFFSET 1 |
| 2893 | #define D0F0x64_x19_Reserved_22_1_WIDTH 22 |
| 2894 | #define D0F0x64_x19_Reserved_22_1_MASK 0x7ffffe |
| 2895 | #define D0F0x64_x19_Tom2_31_23__OFFSET 23 |
| 2896 | #define D0F0x64_x19_Tom2_31_23__WIDTH 9 |
| 2897 | #define D0F0x64_x19_Tom2_31_23__MASK 0xff800000 |
| 2898 | |
| 2899 | /// D0F0x64_x19 |
| 2900 | typedef union { |
| 2901 | struct { ///< |
| 2902 | UINT32 TomEn:1 ; ///< |
| 2903 | UINT32 Reserved_22_1:22; ///< |
| 2904 | UINT32 Tom2_31_23_:9 ; ///< |
| 2905 | } Field; ///< |
| 2906 | UINT32 Value; ///< |
| 2907 | } D0F0x64_x19_STRUCT; |
| 2908 | |
| 2909 | // **** D0F0x64_x1A Register Definition **** |
| 2910 | // Address |
| 2911 | #define D0F0x64_x1A_ADDRESS 0x1a |
| 2912 | |
| 2913 | // Type |
| 2914 | #define D0F0x64_x1A_TYPE TYPE_D0F0x64 |
| 2915 | // Field Data |
| 2916 | #define D0F0x64_x1A_Tom2_39_32__OFFSET 0 |
| 2917 | #define D0F0x64_x1A_Tom2_39_32__WIDTH 8 |
| 2918 | #define D0F0x64_x1A_Tom2_39_32__MASK 0xff |
| 2919 | #define D0F0x64_x1A_Reserved_31_8_OFFSET 8 |
| 2920 | #define D0F0x64_x1A_Reserved_31_8_WIDTH 24 |
| 2921 | #define D0F0x64_x1A_Reserved_31_8_MASK 0xffffff00 |
| 2922 | |
| 2923 | /// D0F0x64_x1A |
| 2924 | typedef union { |
| 2925 | struct { ///< |
| 2926 | UINT32 Tom2_39_32_:8 ; ///< |
| 2927 | UINT32 Reserved_31_8:24; ///< |
| 2928 | } Field; ///< |
| 2929 | UINT32 Value; ///< |
| 2930 | } D0F0x64_x1A_STRUCT; |
| 2931 | |
| 2932 | // **** D0F0x64_x1D Register Definition **** |
| 2933 | // Address |
| 2934 | #define D0F0x64_x1D_ADDRESS 0x1d |
| 2935 | |
| 2936 | // Type |
| 2937 | #define D0F0x64_x1D_TYPE TYPE_D0F0x64 |
| 2938 | // Field Data |
| 2939 | #define D0F0x64_x1D_IntGfxAsPcieEn_OFFSET 0 |
| 2940 | #define D0F0x64_x1D_IntGfxAsPcieEn_WIDTH 1 |
| 2941 | #define D0F0x64_x1D_IntGfxAsPcieEn_MASK 0x1 |
| 2942 | #define D0F0x64_x1D_VgaEn_OFFSET 1 |
| 2943 | #define D0F0x64_x1D_VgaEn_WIDTH 1 |
| 2944 | #define D0F0x64_x1D_VgaEn_MASK 0x2 |
| 2945 | #define D0F0x64_x1D_Reserved_2_2_OFFSET 2 |
| 2946 | #define D0F0x64_x1D_Reserved_2_2_WIDTH 1 |
| 2947 | #define D0F0x64_x1D_Reserved_2_2_MASK 0x4 |
| 2948 | #define D0F0x64_x1D_Vga16En_OFFSET 3 |
| 2949 | #define D0F0x64_x1D_Vga16En_WIDTH 1 |
| 2950 | #define D0F0x64_x1D_Vga16En_MASK 0x8 |
| 2951 | #define D0F0x64_x1D_Reserved_31_4_OFFSET 4 |
| 2952 | #define D0F0x64_x1D_Reserved_31_4_WIDTH 28 |
| 2953 | #define D0F0x64_x1D_Reserved_31_4_MASK 0xfffffff0 |
| 2954 | |
| 2955 | /// D0F0x64_x1D |
| 2956 | typedef union { |
| 2957 | struct { ///< |
| 2958 | UINT32 IntGfxAsPcieEn:1 ; ///< |
| 2959 | UINT32 VgaEn:1 ; ///< |
| 2960 | UINT32 Reserved_2_2:1 ; ///< |
| 2961 | UINT32 Vga16En:1 ; ///< |
| 2962 | UINT32 Reserved_31_4:28; ///< |
| 2963 | } Field; ///< |
| 2964 | UINT32 Value; ///< |
| 2965 | } D0F0x64_x1D_STRUCT; |
| 2966 | |
| 2967 | |
| 2968 | |
| 2969 | |
| 2970 | |
| 2971 | |
| 2972 | |
| 2973 | |
| 2974 | // **** D0F0x64_x53 Register Definition **** |
| 2975 | // Address |
| 2976 | #define D0F0x64_x53_ADDRESS 0x53 |
| 2977 | |
| 2978 | // Type |
| 2979 | #define D0F0x64_x53_TYPE TYPE_D0F0x64 |
| 2980 | // Field Data |
| 2981 | #define D0F0x64_x53_Reserved_19_0_OFFSET 0 |
| 2982 | #define D0F0x64_x53_Reserved_19_0_WIDTH 20 |
| 2983 | #define D0F0x64_x53_Reserved_19_0_MASK 0xfffff |
| 2984 | #define D0F0x64_x53_SetPowEn_OFFSET 20 |
| 2985 | #define D0F0x64_x53_SetPowEn_WIDTH 1 |
| 2986 | #define D0F0x64_x53_SetPowEn_MASK 0x100000 |
| 2987 | #define D0F0x64_x53_Reserved_31_21_OFFSET 21 |
| 2988 | #define D0F0x64_x53_Reserved_31_21_WIDTH 11 |
| 2989 | #define D0F0x64_x53_Reserved_31_21_MASK 0xffe00000 |
| 2990 | |
| 2991 | /// D0F0x64_x53 |
| 2992 | typedef union { |
| 2993 | struct { ///< |
| 2994 | UINT32 Reserved_19_0:20; ///< |
| 2995 | UINT32 SetPowEn:1 ; ///< |
| 2996 | UINT32 Reserved_31_21:11; ///< |
| 2997 | } Field; ///< |
| 2998 | UINT32 Value; ///< |
| 2999 | } D0F0x64_x53_STRUCT; |
| 3000 | |
| 3001 | // **** D0F0x64_x55 Register Definition **** |
| 3002 | // Address |
| 3003 | #define D0F0x64_x55_ADDRESS 0x55 |
| 3004 | |
| 3005 | // Type |
| 3006 | #define D0F0x64_x55_TYPE TYPE_D0F0x64 |
| 3007 | // Field Data |
| 3008 | #define D0F0x64_x55_Reserved_19_0_OFFSET 0 |
| 3009 | #define D0F0x64_x55_Reserved_19_0_WIDTH 20 |
| 3010 | #define D0F0x64_x55_Reserved_19_0_MASK 0xfffff |
| 3011 | #define D0F0x64_x55_SetPowEn_OFFSET 20 |
| 3012 | #define D0F0x64_x55_SetPowEn_WIDTH 1 |
| 3013 | #define D0F0x64_x55_SetPowEn_MASK 0x100000 |
| 3014 | #define D0F0x64_x55_Reserved_31_21_OFFSET 21 |
| 3015 | #define D0F0x64_x55_Reserved_31_21_WIDTH 11 |
| 3016 | #define D0F0x64_x55_Reserved_31_21_MASK 0xffe00000 |
| 3017 | |
| 3018 | /// D0F0x64_x55 |
| 3019 | typedef union { |
| 3020 | struct { ///< |
| 3021 | UINT32 Reserved_19_0:20; ///< |
| 3022 | UINT32 SetPowEn:1 ; ///< |
| 3023 | UINT32 Reserved_31_21:11; ///< |
| 3024 | } Field; ///< |
| 3025 | UINT32 Value; ///< |
| 3026 | } D0F0x64_x55_STRUCT; |
| 3027 | |
| 3028 | // **** D0F0x64_x57 Register Definition **** |
| 3029 | // Address |
| 3030 | #define D0F0x64_x57_ADDRESS 0x57 |
| 3031 | |
| 3032 | // Type |
| 3033 | #define D0F0x64_x57_TYPE TYPE_D0F0x64 |
| 3034 | // Field Data |
| 3035 | #define D0F0x64_x57_Reserved_19_0_OFFSET 0 |
| 3036 | #define D0F0x64_x57_Reserved_19_0_WIDTH 20 |
| 3037 | #define D0F0x64_x57_Reserved_19_0_MASK 0xfffff |
| 3038 | #define D0F0x64_x57_SetPowEn_OFFSET 20 |
| 3039 | #define D0F0x64_x57_SetPowEn_WIDTH 1 |
| 3040 | #define D0F0x64_x57_SetPowEn_MASK 0x100000 |
| 3041 | #define D0F0x64_x57_Reserved_31_21_OFFSET 21 |
| 3042 | #define D0F0x64_x57_Reserved_31_21_WIDTH 11 |
| 3043 | #define D0F0x64_x57_Reserved_31_21_MASK 0xffe00000 |
| 3044 | |
| 3045 | /// D0F0x64_x57 |
| 3046 | typedef union { |
| 3047 | struct { ///< |
| 3048 | UINT32 Reserved_19_0:20; ///< |
| 3049 | UINT32 SetPowEn:1 ; ///< |
| 3050 | UINT32 Reserved_31_21:11; ///< |
| 3051 | } Field; ///< |
| 3052 | UINT32 Value; ///< |
| 3053 | } D0F0x64_x57_STRUCT; |
| 3054 | |
| 3055 | // **** D0F0x64_x59 Register Definition **** |
| 3056 | // Address |
| 3057 | #define D0F0x64_x59_ADDRESS 0x59 |
| 3058 | |
| 3059 | // Type |
| 3060 | #define D0F0x64_x59_TYPE TYPE_D0F0x64 |
| 3061 | // Field Data |
| 3062 | #define D0F0x64_x59_Reserved_19_0_OFFSET 0 |
| 3063 | #define D0F0x64_x59_Reserved_19_0_WIDTH 20 |
| 3064 | #define D0F0x64_x59_Reserved_19_0_MASK 0xfffff |
| 3065 | #define D0F0x64_x59_SetPowEn_OFFSET 20 |
| 3066 | #define D0F0x64_x59_SetPowEn_WIDTH 1 |
| 3067 | #define D0F0x64_x59_SetPowEn_MASK 0x100000 |
| 3068 | #define D0F0x64_x59_Reserved_31_21_OFFSET 21 |
| 3069 | #define D0F0x64_x59_Reserved_31_21_WIDTH 11 |
| 3070 | #define D0F0x64_x59_Reserved_31_21_MASK 0xffe00000 |
| 3071 | |
| 3072 | /// D0F0x64_x59 |
| 3073 | typedef union { |
| 3074 | struct { ///< |
| 3075 | UINT32 Reserved_19_0:20; ///< |
| 3076 | UINT32 SetPowEn:1 ; ///< |
| 3077 | UINT32 Reserved_31_21:11; ///< |
| 3078 | } Field; ///< |
| 3079 | UINT32 Value; ///< |
| 3080 | } D0F0x64_x59_STRUCT; |
| 3081 | |
| 3082 | // **** D0F0x64_x5B Register Definition **** |
| 3083 | // Address |
| 3084 | #define D0F0x64_x5B_ADDRESS 0x5b |
| 3085 | |
| 3086 | // Type |
| 3087 | #define D0F0x64_x5B_TYPE TYPE_D0F0x64 |
| 3088 | // Field Data |
| 3089 | #define D0F0x64_x5B_Reserved_19_0_OFFSET 0 |
| 3090 | #define D0F0x64_x5B_Reserved_19_0_WIDTH 20 |
| 3091 | #define D0F0x64_x5B_Reserved_19_0_MASK 0xfffff |
| 3092 | #define D0F0x64_x5B_SetPowEn_OFFSET 20 |
| 3093 | #define D0F0x64_x5B_SetPowEn_WIDTH 1 |
| 3094 | #define D0F0x64_x5B_SetPowEn_MASK 0x100000 |
| 3095 | #define D0F0x64_x5B_Reserved_31_21_OFFSET 21 |
| 3096 | #define D0F0x64_x5B_Reserved_31_21_WIDTH 11 |
| 3097 | #define D0F0x64_x5B_Reserved_31_21_MASK 0xffe00000 |
| 3098 | |
| 3099 | /// D0F0x64_x5B |
| 3100 | typedef union { |
| 3101 | struct { ///< |
| 3102 | UINT32 Reserved_19_0:20; ///< |
| 3103 | UINT32 SetPowEn:1 ; ///< |
| 3104 | UINT32 Reserved_31_21:11; ///< |
| 3105 | } Field; ///< |
| 3106 | UINT32 Value; ///< |
| 3107 | } D0F0x64_x5B_STRUCT; |
| 3108 | |
| 3109 | /// D0F0x64_x6A |
| 3110 | typedef union { |
| 3111 | struct { ///< |
| 3112 | UINT32 VoltageForceEn:1 ; ///< |
| 3113 | UINT32 VoltageChangeEn:1 ; ///< |
| 3114 | UINT32 VoltageChangeReq:1 ; ///< |
| 3115 | UINT32 VoltageLevel:2 ; ///< |
| 3116 | UINT32 Reserved_31_5:27; ///< |
| 3117 | } Field; ///< |
| 3118 | UINT32 Value; ///< |
| 3119 | } ex488_STRUCT; |
| 3120 | |
| 3121 | /// D0F0x64_x6B |
| 3122 | typedef union { |
| 3123 | struct { ///< |
| 3124 | UINT32 VoltageChangeAck:1 ; ///< |
| 3125 | UINT32 CurrentVoltageLevel:2 ; ///< |
| 3126 | UINT32 Reserved_31_3:29; ///< |
| 3127 | } Field; ///< |
| 3128 | UINT32 Value; ///< |
| 3129 | } ex489_STRUCT; |
| 3130 | |
| 3131 | // **** D0F0x98_x06 Register Definition **** |
| 3132 | // Address |
| 3133 | #define D0F0x98_x06_ADDRESS 0x6 |
| 3134 | |
| 3135 | // Type |
| 3136 | #define D0F0x98_x06_TYPE TYPE_D0F0x98 |
| 3137 | // Field Data |
| 3138 | #define D0F0x98_x06_Reserved_25_0_OFFSET 0 |
| 3139 | #define D0F0x98_x06_Reserved_25_0_WIDTH 26 |
| 3140 | #define D0F0x98_x06_Reserved_25_0_MASK 0x3ffffff |
| 3141 | #define D0F0x98_x06_UmiNpMemWrEn_OFFSET 26 |
| 3142 | #define D0F0x98_x06_UmiNpMemWrEn_WIDTH 1 |
| 3143 | #define D0F0x98_x06_UmiNpMemWrEn_MASK 0x4000000 |
| 3144 | #define D0F0x98_x06_Reserved_31_27_OFFSET 27 |
| 3145 | #define D0F0x98_x06_Reserved_31_27_WIDTH 5 |
| 3146 | #define D0F0x98_x06_Reserved_31_27_MASK 0xf8000000 |
| 3147 | |
| 3148 | /// D0F0x98_x06 |
| 3149 | typedef union { |
| 3150 | struct { ///< |
| 3151 | UINT32 Reserved_25_0:26; ///< |
| 3152 | UINT32 UmiNpMemWrEn:1 ; ///< |
| 3153 | UINT32 Reserved_31_27:5 ; ///< |
| 3154 | } Field; ///< |
| 3155 | UINT32 Value; ///< |
| 3156 | } D0F0x98_x06_STRUCT; |
| 3157 | |
| 3158 | |
| 3159 | |
| 3160 | |
| 3161 | |
| 3162 | // **** D0F0x98_x1E Register Definition **** |
| 3163 | // Address |
| 3164 | #define D0F0x98_x1E_ADDRESS 0x1e |
| 3165 | |
| 3166 | // Type |
| 3167 | #define D0F0x98_x1E_TYPE TYPE_D0F0x98 |
| 3168 | // Field Data |
| 3169 | #define D0F0x98_x1E_Reserved_0_0_OFFSET 0 |
| 3170 | #define D0F0x98_x1E_Reserved_0_0_WIDTH 1 |
| 3171 | #define D0F0x98_x1E_Reserved_0_0_MASK 0x1 |
| 3172 | #define D0F0x98_x1E_HiPriEn_OFFSET 1 |
| 3173 | #define D0F0x98_x1E_HiPriEn_WIDTH 1 |
| 3174 | #define D0F0x98_x1E_HiPriEn_MASK 0x2 |
| 3175 | #define D0F0x98_x1E_Reserved_31_2_OFFSET 2 |
| 3176 | #define D0F0x98_x1E_Reserved_31_2_WIDTH 30 |
| 3177 | #define D0F0x98_x1E_Reserved_31_2_MASK 0xfffffffc |
| 3178 | |
| 3179 | /// D0F0x98_x1E |
| 3180 | typedef union { |
| 3181 | struct { ///< |
| 3182 | UINT32 Reserved_0_0:1 ; ///< |
| 3183 | UINT32 HiPriEn:1 ; ///< |
| 3184 | UINT32 Reserved_31_2:30; ///< |
| 3185 | } Field; ///< |
| 3186 | UINT32 Value; ///< |
| 3187 | } D0F0x98_x1E_STRUCT; |
| 3188 | |
| 3189 | |
| 3190 | /// D0F0x98_x2C |
| 3191 | typedef union { |
| 3192 | struct { ///< |
| 3193 | UINT32 Reserved_0_0:1 ; ///< |
| 3194 | UINT32 ex495_1:1; |
| 3195 | UINT32 Reserved_15_2:14; ///< |
| 3196 | UINT32 ex495_3:16; |
| 3197 | } Field; ///< |
| 3198 | UINT32 Value; ///< |
| 3199 | } ex495_STRUCT; |
| 3200 | |
| 3201 | |
| 3202 | // **** D0F0x98_x49 Register Definition **** |
| 3203 | // Address |
| 3204 | #define D0F0x98_x49_ADDRESS 0x49 |
| 3205 | |
| 3206 | // Type |
| 3207 | #define D0F0x98_x49_TYPE TYPE_D0F0x98 |
| 3208 | // Field Data |
| 3209 | #define D0F0x98_x49_Reserved_3_0_OFFSET 0 |
| 3210 | #define D0F0x98_x49_Reserved_3_0_WIDTH 4 |
| 3211 | #define D0F0x98_x49_Reserved_3_0_MASK 0xf |
| 3212 | #define D0F0x98_x49_Reserved_23_12_OFFSET 12 |
| 3213 | #define D0F0x98_x49_Reserved_23_12_WIDTH 12 |
| 3214 | #define D0F0x98_x49_Reserved_23_12_MASK 0xfff000 |
| 3215 | #define D0F0x98_x49_SoftOverrideClk6_OFFSET 24 |
| 3216 | #define D0F0x98_x49_SoftOverrideClk6_WIDTH 1 |
| 3217 | #define D0F0x98_x49_SoftOverrideClk6_MASK 0x1000000 |
| 3218 | #define D0F0x98_x49_SoftOverrideClk5_OFFSET 25 |
| 3219 | #define D0F0x98_x49_SoftOverrideClk5_WIDTH 1 |
| 3220 | #define D0F0x98_x49_SoftOverrideClk5_MASK 0x2000000 |
| 3221 | #define D0F0x98_x49_SoftOverrideClk4_OFFSET 26 |
| 3222 | #define D0F0x98_x49_SoftOverrideClk4_WIDTH 1 |
| 3223 | #define D0F0x98_x49_SoftOverrideClk4_MASK 0x4000000 |
| 3224 | #define D0F0x98_x49_SoftOverrideClk3_OFFSET 27 |
| 3225 | #define D0F0x98_x49_SoftOverrideClk3_WIDTH 1 |
| 3226 | #define D0F0x98_x49_SoftOverrideClk3_MASK 0x8000000 |
| 3227 | #define D0F0x98_x49_SoftOverrideClk2_OFFSET 28 |
| 3228 | #define D0F0x98_x49_SoftOverrideClk2_WIDTH 1 |
| 3229 | #define D0F0x98_x49_SoftOverrideClk2_MASK 0x10000000 |
| 3230 | #define D0F0x98_x49_SoftOverrideClk1_OFFSET 29 |
| 3231 | #define D0F0x98_x49_SoftOverrideClk1_WIDTH 1 |
| 3232 | #define D0F0x98_x49_SoftOverrideClk1_MASK 0x20000000 |
| 3233 | #define D0F0x98_x49_SoftOverrideClk0_OFFSET 30 |
| 3234 | #define D0F0x98_x49_SoftOverrideClk0_WIDTH 1 |
| 3235 | #define D0F0x98_x49_SoftOverrideClk0_MASK 0x40000000 |
| 3236 | #define D0F0x98_x49_Reserved_31_31_OFFSET 31 |
| 3237 | #define D0F0x98_x49_Reserved_31_31_WIDTH 1 |
| 3238 | #define D0F0x98_x49_Reserved_31_31_MASK 0x80000000 |
| 3239 | |
| 3240 | /// D0F0x98_x49 |
| 3241 | typedef union { |
| 3242 | struct { ///< |
| 3243 | UINT32 Reserved_3_0:4 ; ///< |
| 3244 | UINT32 :8 ; ///< |
| 3245 | UINT32 Reserved_23_12:12; ///< |
| 3246 | UINT32 SoftOverrideClk6:1 ; ///< |
| 3247 | UINT32 SoftOverrideClk5:1 ; ///< |
| 3248 | UINT32 SoftOverrideClk4:1 ; ///< |
| 3249 | UINT32 SoftOverrideClk3:1 ; ///< |
| 3250 | UINT32 SoftOverrideClk2:1 ; ///< |
| 3251 | UINT32 SoftOverrideClk1:1 ; ///< |
| 3252 | UINT32 SoftOverrideClk0:1 ; ///< |
| 3253 | UINT32 Reserved_31_31:1 ; ///< |
| 3254 | } Field; ///< |
| 3255 | UINT32 Value; ///< |
| 3256 | } D0F0x98_x49_STRUCT; |
| 3257 | |
| 3258 | // **** D0F0x98_x4A Register Definition **** |
| 3259 | // Address |
| 3260 | #define D0F0x98_x4A_ADDRESS 0x4a |
| 3261 | |
| 3262 | // Type |
| 3263 | #define D0F0x98_x4A_TYPE TYPE_D0F0x98 |
| 3264 | // Field Data |
| 3265 | #define D0F0x98_x4A_Reserved_3_0_OFFSET 0 |
| 3266 | #define D0F0x98_x4A_Reserved_3_0_WIDTH 4 |
| 3267 | #define D0F0x98_x4A_Reserved_3_0_MASK 0xf |
| 3268 | #define D0F0x98_x4A_Reserved_23_12_OFFSET 12 |
| 3269 | #define D0F0x98_x4A_Reserved_23_12_WIDTH 12 |
| 3270 | #define D0F0x98_x4A_Reserved_23_12_MASK 0xfff000 |
| 3271 | #define D0F0x98_x4A_SoftOverrideClk6_OFFSET 24 |
| 3272 | #define D0F0x98_x4A_SoftOverrideClk6_WIDTH 1 |
| 3273 | #define D0F0x98_x4A_SoftOverrideClk6_MASK 0x1000000 |
| 3274 | #define D0F0x98_x4A_SoftOverrideClk5_OFFSET 25 |
| 3275 | #define D0F0x98_x4A_SoftOverrideClk5_WIDTH 1 |
| 3276 | #define D0F0x98_x4A_SoftOverrideClk5_MASK 0x2000000 |
| 3277 | #define D0F0x98_x4A_SoftOverrideClk4_OFFSET 26 |
| 3278 | #define D0F0x98_x4A_SoftOverrideClk4_WIDTH 1 |
| 3279 | #define D0F0x98_x4A_SoftOverrideClk4_MASK 0x4000000 |
| 3280 | #define D0F0x98_x4A_SoftOverrideClk3_OFFSET 27 |
| 3281 | #define D0F0x98_x4A_SoftOverrideClk3_WIDTH 1 |
| 3282 | #define D0F0x98_x4A_SoftOverrideClk3_MASK 0x8000000 |
| 3283 | #define D0F0x98_x4A_SoftOverrideClk2_OFFSET 28 |
| 3284 | #define D0F0x98_x4A_SoftOverrideClk2_WIDTH 1 |
| 3285 | #define D0F0x98_x4A_SoftOverrideClk2_MASK 0x10000000 |
| 3286 | #define D0F0x98_x4A_SoftOverrideClk1_OFFSET 29 |
| 3287 | #define D0F0x98_x4A_SoftOverrideClk1_WIDTH 1 |
| 3288 | #define D0F0x98_x4A_SoftOverrideClk1_MASK 0x20000000 |
| 3289 | #define D0F0x98_x4A_SoftOverrideClk0_OFFSET 30 |
| 3290 | #define D0F0x98_x4A_SoftOverrideClk0_WIDTH 1 |
| 3291 | #define D0F0x98_x4A_SoftOverrideClk0_MASK 0x40000000 |
| 3292 | #define D0F0x98_x4A_Reserved_31_31_OFFSET 31 |
| 3293 | #define D0F0x98_x4A_Reserved_31_31_WIDTH 1 |
| 3294 | #define D0F0x98_x4A_Reserved_31_31_MASK 0x80000000 |
| 3295 | |
| 3296 | /// D0F0x98_x4A |
| 3297 | typedef union { |
| 3298 | struct { ///< |
| 3299 | UINT32 Reserved_3_0:4 ; ///< |
| 3300 | UINT32 :8 ; ///< |
| 3301 | UINT32 Reserved_23_12:12; ///< |
| 3302 | UINT32 SoftOverrideClk6:1 ; ///< |
| 3303 | UINT32 SoftOverrideClk5:1 ; ///< |
| 3304 | UINT32 SoftOverrideClk4:1 ; ///< |
| 3305 | UINT32 SoftOverrideClk3:1 ; ///< |
| 3306 | UINT32 SoftOverrideClk2:1 ; ///< |
| 3307 | UINT32 SoftOverrideClk1:1 ; ///< |
| 3308 | UINT32 SoftOverrideClk0:1 ; ///< |
| 3309 | UINT32 Reserved_31_31:1 ; ///< |
| 3310 | } Field; ///< |
| 3311 | UINT32 Value; ///< |
| 3312 | } D0F0x98_x4A_STRUCT; |
| 3313 | |
| 3314 | |
| 3315 | // **** D0F0xE4_WRAP_0080 Register Definition **** |
| 3316 | // Address |
| 3317 | #define D0F0xE4_WRAP_0080_ADDRESS 0x80 |
| 3318 | |
| 3319 | // Type |
| 3320 | #define D0F0xE4_WRAP_0080_TYPE TYPE_D0F0xE4 |
| 3321 | // Field Data |
| 3322 | #define D0F0xE4_WRAP_0080_StrapBifLinkConfig_OFFSET 0 |
| 3323 | #define D0F0xE4_WRAP_0080_StrapBifLinkConfig_WIDTH 4 |
| 3324 | #define D0F0xE4_WRAP_0080_StrapBifLinkConfig_MASK 0xf |
| 3325 | #define D0F0xE4_WRAP_0080_Reserved_31_4_OFFSET 4 |
| 3326 | #define D0F0xE4_WRAP_0080_Reserved_31_4_WIDTH 28 |
| 3327 | #define D0F0xE4_WRAP_0080_Reserved_31_4_MASK 0xfffffff0 |
| 3328 | |
| 3329 | /// D0F0xE4_WRAP_0080 |
| 3330 | typedef union { |
| 3331 | struct { ///< |
| 3332 | UINT32 StrapBifLinkConfig:4 ; ///< |
| 3333 | UINT32 Reserved_31_4:28; ///< |
| 3334 | } Field; ///< |
| 3335 | UINT32 Value; ///< |
| 3336 | } D0F0xE4_WRAP_0080_STRUCT; |
| 3337 | |
| 3338 | // **** D0F0xE4_WRAP_0800 Register Definition **** |
| 3339 | // Address |
| 3340 | #define D0F0xE4_WRAP_0800_ADDRESS 0x800 |
| 3341 | |
| 3342 | // Type |
| 3343 | #define D0F0xE4_WRAP_0800_TYPE TYPE_D0F0xE4 |
| 3344 | // Field Data |
| 3345 | #define D0F0xE4_WRAP_0800_HoldTraining_OFFSET 0 |
| 3346 | #define D0F0xE4_WRAP_0800_HoldTraining_WIDTH 1 |
| 3347 | #define D0F0xE4_WRAP_0800_HoldTraining_MASK 0x1 |
| 3348 | #define D0F0xE4_WRAP_0800_Reserved_31_1_OFFSET 1 |
| 3349 | #define D0F0xE4_WRAP_0800_Reserved_31_1_WIDTH 31 |
| 3350 | #define D0F0xE4_WRAP_0800_Reserved_31_1_MASK 0xfffffffe |
| 3351 | |
| 3352 | /// D0F0xE4_WRAP_0800 |
| 3353 | typedef union { |
| 3354 | struct { ///< |
| 3355 | UINT32 HoldTraining:1 ; ///< |
| 3356 | UINT32 Reserved_31_1:31; ///< |
| 3357 | } Field; ///< |
| 3358 | UINT32 Value; ///< |
| 3359 | } D0F0xE4_WRAP_0800_STRUCT; |
| 3360 | |
| 3361 | // **** D0F0xE4_WRAP_0803 Register Definition **** |
| 3362 | // Address |
| 3363 | #define D0F0xE4_WRAP_0803_ADDRESS 0x803 |
| 3364 | |
| 3365 | // Type |
| 3366 | #define D0F0xE4_WRAP_0803_TYPE TYPE_D0F0xE4 |
| 3367 | // Field Data |
| 3368 | #define D0F0xE4_WRAP_0803_Reserved_4_0_OFFSET 0 |
| 3369 | #define D0F0xE4_WRAP_0803_Reserved_4_0_WIDTH 5 |
| 3370 | #define D0F0xE4_WRAP_0803_Reserved_4_0_MASK 0x1f |
| 3371 | #define D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_OFFSET 5 |
| 3372 | #define D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_WIDTH 1 |
| 3373 | #define D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_MASK 0x20 |
| 3374 | #define D0F0xE4_WRAP_0803_Reserved_31_6_OFFSET 6 |
| 3375 | #define D0F0xE4_WRAP_0803_Reserved_31_6_WIDTH 26 |
| 3376 | #define D0F0xE4_WRAP_0803_Reserved_31_6_MASK 0xffffffc0 |
| 3377 | |
| 3378 | /// D0F0xE4_WRAP_0803 |
| 3379 | typedef union { |
| 3380 | struct { ///< |
| 3381 | UINT32 Reserved_4_0:5 ; ///< |
| 3382 | UINT32 StrapBifDeemphasisSel:1 ; ///< |
| 3383 | UINT32 Reserved_31_6:26; ///< |
| 3384 | } Field; ///< |
| 3385 | UINT32 Value; ///< |
| 3386 | } D0F0xE4_WRAP_0803_STRUCT; |
| 3387 | |
| 3388 | // **** D0F0xE4_WRAP_0903 Register Definition **** |
| 3389 | // Address |
| 3390 | #define D0F0xE4_WRAP_0903_ADDRESS 0x903 |
| 3391 | |
| 3392 | // Type |
| 3393 | #define D0F0xE4_WRAP_0903_TYPE TYPE_D0F0xE4 |
| 3394 | // Field Data |
| 3395 | #define D0F0xE4_WRAP_0903_Reserved_4_0_OFFSET 0 |
| 3396 | #define D0F0xE4_WRAP_0903_Reserved_4_0_WIDTH 5 |
| 3397 | #define D0F0xE4_WRAP_0903_Reserved_4_0_MASK 0x1f |
| 3398 | #define D0F0xE4_WRAP_0903_StrapBifDeemphasisSel_OFFSET 5 |
| 3399 | #define D0F0xE4_WRAP_0903_StrapBifDeemphasisSel_WIDTH 1 |
| 3400 | #define D0F0xE4_WRAP_0903_StrapBifDeemphasisSel_MASK 0x20 |
| 3401 | #define D0F0xE4_WRAP_0903_Reserved_31_6_OFFSET 6 |
| 3402 | #define D0F0xE4_WRAP_0903_Reserved_31_6_WIDTH 26 |
| 3403 | #define D0F0xE4_WRAP_0903_Reserved_31_6_MASK 0xffffffc0 |
| 3404 | |
| 3405 | /// D0F0xE4_WRAP_0903 |
| 3406 | typedef union { |
| 3407 | struct { ///< |
| 3408 | UINT32 Reserved_4_0:5 ; ///< |
| 3409 | UINT32 StrapBifDeemphasisSel:1 ; ///< |
| 3410 | UINT32 Reserved_31_6:26; ///< |
| 3411 | } Field; ///< |
| 3412 | UINT32 Value; ///< |
| 3413 | } D0F0xE4_WRAP_0903_STRUCT; |
| 3414 | |
| 3415 | |
| 3416 | /// D0F0xE4_WRAP_8011 |
| 3417 | typedef union { |
| 3418 | struct { ///< |
| 3419 | UINT32 TxclkDynGateLatency:6 ; ///< |
| 3420 | UINT32 TxclkPermGateEven:1 ; ///< |
| 3421 | UINT32 TxclkDynGateEnable:1 ; ///< |
| 3422 | UINT32 TxclkPermStop:1 ; ///< |
| 3423 | UINT32 TxclkRegsGateEnable:1 ; ///< |
| 3424 | UINT32 TxclkRegsGateLatency:6 ; ///< |
| 3425 | UINT32 RcvrDetClkEnable:1 ; ///< |
| 3426 | UINT32 TxclkPermGateLatency:6 ; ///< |
| 3427 | UINT32 Reserved_23_23:1 ; ///< |
| 3428 | UINT32 TxclkLcntGateEnable:1 ; ///< |
| 3429 | UINT32 Reserved_30_25:6 ; ///< |
| 3430 | UINT32 StrapBifValid:1 ; ///< |
| 3431 | } Field; ///< |
| 3432 | UINT32 Value; ///< |
| 3433 | } ex501_STRUCT; |
| 3434 | |
| 3435 | // **** D0F0xE4_WRAP_8012 Register Definition **** |
| 3436 | // Address |
| 3437 | #define D0F0xE4_WRAP_8012_ADDRESS 0x8012 |
| 3438 | |
| 3439 | // Type |
| 3440 | #define D0F0xE4_WRAP_8012_TYPE TYPE_D0F0xE4 |
| 3441 | // Field Data |
| 3442 | #define D0F0xE4_WRAP_8012_Pif1xIdleGateLatency_OFFSET 0 |
| 3443 | #define D0F0xE4_WRAP_8012_Pif1xIdleGateLatency_WIDTH 6 |
| 3444 | #define D0F0xE4_WRAP_8012_Pif1xIdleGateLatency_MASK 0x3f |
| 3445 | #define D0F0xE4_WRAP_8012_Reserved_6_6_OFFSET 6 |
| 3446 | #define D0F0xE4_WRAP_8012_Reserved_6_6_WIDTH 1 |
| 3447 | #define D0F0xE4_WRAP_8012_Reserved_6_6_MASK 0x40 |
| 3448 | #define D0F0xE4_WRAP_8012_Pif1xIdleGateEnable_OFFSET 7 |
| 3449 | #define D0F0xE4_WRAP_8012_Pif1xIdleGateEnable_WIDTH 1 |
| 3450 | #define D0F0xE4_WRAP_8012_Pif1xIdleGateEnable_MASK 0x80 |
| 3451 | #define D0F0xE4_WRAP_8012_Pif1xIdleResumeLatency_OFFSET 8 |
| 3452 | #define D0F0xE4_WRAP_8012_Pif1xIdleResumeLatency_WIDTH 6 |
| 3453 | #define D0F0xE4_WRAP_8012_Pif1xIdleResumeLatency_MASK 0x3f00 |
| 3454 | #define D0F0xE4_WRAP_8012_Reserved_15_14_OFFSET 14 |
| 3455 | #define D0F0xE4_WRAP_8012_Reserved_15_14_WIDTH 2 |
| 3456 | #define D0F0xE4_WRAP_8012_Reserved_15_14_MASK 0xc000 |
| 3457 | #define D0F0xE4_WRAP_8012_Pif2p5xIdleGateLatency_OFFSET 16 |
| 3458 | #define D0F0xE4_WRAP_8012_Pif2p5xIdleGateLatency_WIDTH 6 |
| 3459 | #define D0F0xE4_WRAP_8012_Pif2p5xIdleGateLatency_MASK 0x3f0000 |
| 3460 | #define D0F0xE4_WRAP_8012_Reserved_22_22_OFFSET 22 |
| 3461 | #define D0F0xE4_WRAP_8012_Reserved_22_22_WIDTH 1 |
| 3462 | #define D0F0xE4_WRAP_8012_Reserved_22_22_MASK 0x400000 |
| 3463 | #define D0F0xE4_WRAP_8012_Pif2p5xIdleGateEnable_OFFSET 23 |
| 3464 | #define D0F0xE4_WRAP_8012_Pif2p5xIdleGateEnable_WIDTH 1 |
| 3465 | #define D0F0xE4_WRAP_8012_Pif2p5xIdleGateEnable_MASK 0x800000 |
| 3466 | #define D0F0xE4_WRAP_8012_Pif2p5xIdleResumeLatency_OFFSET 24 |
| 3467 | #define D0F0xE4_WRAP_8012_Pif2p5xIdleResumeLatency_WIDTH 6 |
| 3468 | #define D0F0xE4_WRAP_8012_Pif2p5xIdleResumeLatency_MASK 0x3f000000 |
| 3469 | #define D0F0xE4_WRAP_8012_Reserved_31_30_OFFSET 30 |
| 3470 | #define D0F0xE4_WRAP_8012_Reserved_31_30_WIDTH 2 |
| 3471 | #define D0F0xE4_WRAP_8012_Reserved_31_30_MASK 0xc0000000 |
| 3472 | |
| 3473 | /// D0F0xE4_WRAP_8012 |
| 3474 | typedef union { |
| 3475 | struct { ///< |
| 3476 | UINT32 Pif1xIdleGateLatency:6 ; ///< |
| 3477 | UINT32 Reserved_6_6:1 ; ///< |
| 3478 | UINT32 Pif1xIdleGateEnable:1 ; ///< |
| 3479 | UINT32 Pif1xIdleResumeLatency:6 ; ///< |
| 3480 | UINT32 Reserved_15_14:2 ; ///< |
| 3481 | UINT32 Pif2p5xIdleGateLatency:6 ; ///< |
| 3482 | UINT32 Reserved_22_22:1 ; ///< |
| 3483 | UINT32 Pif2p5xIdleGateEnable:1 ; ///< |
| 3484 | UINT32 Pif2p5xIdleResumeLatency:6 ; ///< |
| 3485 | UINT32 Reserved_31_30:2 ; ///< |
| 3486 | } Field; ///< |
| 3487 | UINT32 Value; ///< |
| 3488 | } D0F0xE4_WRAP_8012_STRUCT; |
| 3489 | |
| 3490 | |
| 3491 | // **** D0F0xE4_WRAP_8021 Register Definition **** |
| 3492 | // Address |
| 3493 | #define D0F0xE4_WRAP_8021_ADDRESS 0x8021 |
| 3494 | |
| 3495 | // Type |
| 3496 | #define D0F0xE4_WRAP_8021_TYPE TYPE_D0F0xE4 |
| 3497 | // Field Data |
| 3498 | #define D0F0xE4_WRAP_8021_Lanes10_OFFSET 0 |
| 3499 | #define D0F0xE4_WRAP_8021_Lanes10_WIDTH 4 |
| 3500 | #define D0F0xE4_WRAP_8021_Lanes10_MASK 0xf |
| 3501 | #define D0F0xE4_WRAP_8021_Lanes32_OFFSET 4 |
| 3502 | #define D0F0xE4_WRAP_8021_Lanes32_WIDTH 4 |
| 3503 | #define D0F0xE4_WRAP_8021_Lanes32_MASK 0xf0 |
| 3504 | #define D0F0xE4_WRAP_8021_Lanes54_OFFSET 8 |
| 3505 | #define D0F0xE4_WRAP_8021_Lanes54_WIDTH 4 |
| 3506 | #define D0F0xE4_WRAP_8021_Lanes54_MASK 0xf00 |
| 3507 | #define D0F0xE4_WRAP_8021_Lanes76_OFFSET 12 |
| 3508 | #define D0F0xE4_WRAP_8021_Lanes76_WIDTH 4 |
| 3509 | #define D0F0xE4_WRAP_8021_Lanes76_MASK 0xf000 |
| 3510 | #define D0F0xE4_WRAP_8021_Lanes98_OFFSET 16 |
| 3511 | #define D0F0xE4_WRAP_8021_Lanes98_WIDTH 4 |
| 3512 | #define D0F0xE4_WRAP_8021_Lanes98_MASK 0xf0000 |
| 3513 | #define D0F0xE4_WRAP_8021_Lanes1110_OFFSET 20 |
| 3514 | #define D0F0xE4_WRAP_8021_Lanes1110_WIDTH 4 |
| 3515 | #define D0F0xE4_WRAP_8021_Lanes1110_MASK 0xf00000 |
| 3516 | #define D0F0xE4_WRAP_8021_Lanes1312_OFFSET 24 |
| 3517 | #define D0F0xE4_WRAP_8021_Lanes1312_WIDTH 4 |
| 3518 | #define D0F0xE4_WRAP_8021_Lanes1312_MASK 0xf000000 |
| 3519 | #define D0F0xE4_WRAP_8021_Lanes1514_OFFSET 28 |
| 3520 | #define D0F0xE4_WRAP_8021_Lanes1514_WIDTH 4 |
| 3521 | #define D0F0xE4_WRAP_8021_Lanes1514_MASK 0xf0000000 |
| 3522 | |
| 3523 | /// D0F0xE4_WRAP_8021 |
| 3524 | typedef union { |
| 3525 | struct { ///< |
| 3526 | UINT32 Lanes10:4 ; ///< |
| 3527 | UINT32 Lanes32:4 ; ///< |
| 3528 | UINT32 Lanes54:4 ; ///< |
| 3529 | UINT32 Lanes76:4 ; ///< |
| 3530 | UINT32 Lanes98:4 ; ///< |
| 3531 | UINT32 Lanes1110:4 ; ///< |
| 3532 | UINT32 Lanes1312:4 ; ///< |
| 3533 | UINT32 Lanes1514:4 ; ///< |
| 3534 | } Field; ///< |
| 3535 | UINT32 Value; ///< |
| 3536 | } D0F0xE4_WRAP_8021_STRUCT; |
| 3537 | |
| 3538 | // **** D0F0xE4_WRAP_8022 Register Definition **** |
| 3539 | // Address |
| 3540 | #define D0F0xE4_WRAP_8022_ADDRESS 0x8022 |
| 3541 | |
| 3542 | // Type |
| 3543 | #define D0F0xE4_WRAP_8022_TYPE TYPE_D0F0xE4 |
| 3544 | // Field Data |
| 3545 | #define D0F0xE4_WRAP_8022_Lanes10_OFFSET 0 |
| 3546 | #define D0F0xE4_WRAP_8022_Lanes10_WIDTH 4 |
| 3547 | #define D0F0xE4_WRAP_8022_Lanes10_MASK 0xf |
| 3548 | #define D0F0xE4_WRAP_8022_Lanes32_OFFSET 4 |
| 3549 | #define D0F0xE4_WRAP_8022_Lanes32_WIDTH 4 |
| 3550 | #define D0F0xE4_WRAP_8022_Lanes32_MASK 0xf0 |
| 3551 | #define D0F0xE4_WRAP_8022_Lanes54_OFFSET 8 |
| 3552 | #define D0F0xE4_WRAP_8022_Lanes54_WIDTH 4 |
| 3553 | #define D0F0xE4_WRAP_8022_Lanes54_MASK 0xf00 |
| 3554 | #define D0F0xE4_WRAP_8022_Lanes76_OFFSET 12 |
| 3555 | #define D0F0xE4_WRAP_8022_Lanes76_WIDTH 4 |
| 3556 | #define D0F0xE4_WRAP_8022_Lanes76_MASK 0xf000 |
| 3557 | #define D0F0xE4_WRAP_8022_Lanes98_OFFSET 16 |
| 3558 | #define D0F0xE4_WRAP_8022_Lanes98_WIDTH 4 |
| 3559 | #define D0F0xE4_WRAP_8022_Lanes98_MASK 0xf0000 |
| 3560 | #define D0F0xE4_WRAP_8022_Lanes1110_OFFSET 20 |
| 3561 | #define D0F0xE4_WRAP_8022_Lanes1110_WIDTH 4 |
| 3562 | #define D0F0xE4_WRAP_8022_Lanes1110_MASK 0xf00000 |
| 3563 | #define D0F0xE4_WRAP_8022_Lanes1312_OFFSET 24 |
| 3564 | #define D0F0xE4_WRAP_8022_Lanes1312_WIDTH 4 |
| 3565 | #define D0F0xE4_WRAP_8022_Lanes1312_MASK 0xf000000 |
| 3566 | #define D0F0xE4_WRAP_8022_Lanes1514_OFFSET 28 |
| 3567 | #define D0F0xE4_WRAP_8022_Lanes1514_WIDTH 4 |
| 3568 | #define D0F0xE4_WRAP_8022_Lanes1514_MASK 0xf0000000 |
| 3569 | |
| 3570 | /// D0F0xE4_WRAP_8022 |
| 3571 | typedef union { |
| 3572 | struct { ///< |
| 3573 | UINT32 Lanes10:4 ; ///< |
| 3574 | UINT32 Lanes32:4 ; ///< |
| 3575 | UINT32 Lanes54:4 ; ///< |
| 3576 | UINT32 Lanes76:4 ; ///< |
| 3577 | UINT32 Lanes98:4 ; ///< |
| 3578 | UINT32 Lanes1110:4 ; ///< |
| 3579 | UINT32 Lanes1312:4 ; ///< |
| 3580 | UINT32 Lanes1514:4 ; ///< |
| 3581 | } Field; ///< |
| 3582 | UINT32 Value; ///< |
| 3583 | } D0F0xE4_WRAP_8022_STRUCT; |
| 3584 | |
| 3585 | // **** D0F0xE4_WRAP_8023 Register Definition **** |
| 3586 | // Address |
| 3587 | #define D0F0xE4_WRAP_8023_ADDRESS 0x8023 |
| 3588 | |
| 3589 | // Type |
| 3590 | #define D0F0xE4_WRAP_8023_TYPE TYPE_D0F0xE4 |
| 3591 | // Field Data |
| 3592 | #define D0F0xE4_WRAP_8023_LaneEnable_OFFSET 0 |
| 3593 | #define D0F0xE4_WRAP_8023_LaneEnable_WIDTH 16 |
| 3594 | #define D0F0xE4_WRAP_8023_LaneEnable_MASK 0xffff |
| 3595 | #define D0F0xE4_WRAP_8023_Reserved_31_16_OFFSET 16 |
| 3596 | #define D0F0xE4_WRAP_8023_Reserved_31_16_WIDTH 16 |
| 3597 | #define D0F0xE4_WRAP_8023_Reserved_31_16_MASK 0xffff0000 |
| 3598 | |
| 3599 | /// D0F0xE4_WRAP_8023 |
| 3600 | typedef union { |
| 3601 | struct { ///< |
| 3602 | UINT32 LaneEnable:16; ///< |
| 3603 | UINT32 Reserved_31_16:16; ///< |
| 3604 | } Field; ///< |
| 3605 | UINT32 Value; ///< |
| 3606 | } D0F0xE4_WRAP_8023_STRUCT; |
| 3607 | |
| 3608 | // **** D0F0xE4_WRAP_8025 Register Definition **** |
| 3609 | // Address |
| 3610 | #define D0F0xE4_WRAP_8025_ADDRESS 0x8025 |
| 3611 | |
| 3612 | // Type |
| 3613 | #define D0F0xE4_WRAP_8025_TYPE TYPE_D0F0xE4 |
| 3614 | // Field Data |
| 3615 | #define D0F0xE4_WRAP_8025_LMTxPhyCmd0_OFFSET 0 |
| 3616 | #define D0F0xE4_WRAP_8025_LMTxPhyCmd0_WIDTH 3 |
| 3617 | #define D0F0xE4_WRAP_8025_LMTxPhyCmd0_MASK 0x7 |
| 3618 | #define D0F0xE4_WRAP_8025_LMRxPhyCmd0_OFFSET 3 |
| 3619 | #define D0F0xE4_WRAP_8025_LMRxPhyCmd0_WIDTH 2 |
| 3620 | #define D0F0xE4_WRAP_8025_LMRxPhyCmd0_MASK 0x18 |
| 3621 | #define D0F0xE4_WRAP_8025_LMLinkSpeed0_OFFSET 5 |
| 3622 | #define D0F0xE4_WRAP_8025_LMLinkSpeed0_WIDTH 1 |
| 3623 | #define D0F0xE4_WRAP_8025_LMLinkSpeed0_MASK 0x20 |
| 3624 | #define D0F0xE4_WRAP_8025_Reserved_7_6_OFFSET 6 |
| 3625 | #define D0F0xE4_WRAP_8025_Reserved_7_6_WIDTH 2 |
| 3626 | #define D0F0xE4_WRAP_8025_Reserved_7_6_MASK 0xc0 |
| 3627 | #define D0F0xE4_WRAP_8025_LMTxPhyCmd1_OFFSET 8 |
| 3628 | #define D0F0xE4_WRAP_8025_LMTxPhyCmd1_WIDTH 3 |
| 3629 | #define D0F0xE4_WRAP_8025_LMTxPhyCmd1_MASK 0x700 |
| 3630 | #define D0F0xE4_WRAP_8025_LMRxPhyCmd1_OFFSET 11 |
| 3631 | #define D0F0xE4_WRAP_8025_LMRxPhyCmd1_WIDTH 2 |
| 3632 | #define D0F0xE4_WRAP_8025_LMRxPhyCmd1_MASK 0x1800 |
| 3633 | #define D0F0xE4_WRAP_8025_LMLinkSpeed1_OFFSET 13 |
| 3634 | #define D0F0xE4_WRAP_8025_LMLinkSpeed1_WIDTH 1 |
| 3635 | #define D0F0xE4_WRAP_8025_LMLinkSpeed1_MASK 0x2000 |
| 3636 | #define D0F0xE4_WRAP_8025_Reserved_15_14_OFFSET 14 |
| 3637 | #define D0F0xE4_WRAP_8025_Reserved_15_14_WIDTH 2 |
| 3638 | #define D0F0xE4_WRAP_8025_Reserved_15_14_MASK 0xc000 |
| 3639 | #define D0F0xE4_WRAP_8025_LMTxPhyCmd2_OFFSET 16 |
| 3640 | #define D0F0xE4_WRAP_8025_LMTxPhyCmd2_WIDTH 3 |
| 3641 | #define D0F0xE4_WRAP_8025_LMTxPhyCmd2_MASK 0x70000 |
| 3642 | #define D0F0xE4_WRAP_8025_LMRxPhyCmd2_OFFSET 19 |
| 3643 | #define D0F0xE4_WRAP_8025_LMRxPhyCmd2_WIDTH 2 |
| 3644 | #define D0F0xE4_WRAP_8025_LMRxPhyCmd2_MASK 0x180000 |
| 3645 | #define D0F0xE4_WRAP_8025_LMLinkSpeed2_OFFSET 21 |
| 3646 | #define D0F0xE4_WRAP_8025_LMLinkSpeed2_WIDTH 1 |
| 3647 | #define D0F0xE4_WRAP_8025_LMLinkSpeed2_MASK 0x200000 |
| 3648 | #define D0F0xE4_WRAP_8025_Reserved_23_22_OFFSET 22 |
| 3649 | #define D0F0xE4_WRAP_8025_Reserved_23_22_WIDTH 2 |
| 3650 | #define D0F0xE4_WRAP_8025_Reserved_23_22_MASK 0xc00000 |
| 3651 | #define D0F0xE4_WRAP_8025_LMTxPhyCmd3_OFFSET 24 |
| 3652 | #define D0F0xE4_WRAP_8025_LMTxPhyCmd3_WIDTH 3 |
| 3653 | #define D0F0xE4_WRAP_8025_LMTxPhyCmd3_MASK 0x7000000 |
| 3654 | #define D0F0xE4_WRAP_8025_LMRxPhyCmd3_OFFSET 27 |
| 3655 | #define D0F0xE4_WRAP_8025_LMRxPhyCmd3_WIDTH 2 |
| 3656 | #define D0F0xE4_WRAP_8025_LMRxPhyCmd3_MASK 0x18000000 |
| 3657 | #define D0F0xE4_WRAP_8025_LMLinkSpeed3_OFFSET 29 |
| 3658 | #define D0F0xE4_WRAP_8025_LMLinkSpeed3_WIDTH 1 |
| 3659 | #define D0F0xE4_WRAP_8025_LMLinkSpeed3_MASK 0x20000000 |
| 3660 | #define D0F0xE4_WRAP_8025_Reserved_31_30_OFFSET 30 |
| 3661 | #define D0F0xE4_WRAP_8025_Reserved_31_30_WIDTH 2 |
| 3662 | #define D0F0xE4_WRAP_8025_Reserved_31_30_MASK 0xc0000000 |
| 3663 | |
| 3664 | /// D0F0xE4_WRAP_8025 |
| 3665 | typedef union { |
| 3666 | struct { ///< |
| 3667 | UINT32 LMTxPhyCmd0:3 ; ///< |
| 3668 | UINT32 LMRxPhyCmd0:2 ; ///< |
| 3669 | UINT32 LMLinkSpeed0:1 ; ///< |
| 3670 | UINT32 Reserved_7_6:2 ; ///< |
| 3671 | UINT32 LMTxPhyCmd1:3 ; ///< |
| 3672 | UINT32 LMRxPhyCmd1:2 ; ///< |
| 3673 | UINT32 LMLinkSpeed1:1 ; ///< |
| 3674 | UINT32 Reserved_15_14:2 ; ///< |
| 3675 | UINT32 LMTxPhyCmd2:3 ; ///< |
| 3676 | UINT32 LMRxPhyCmd2:2 ; ///< |
| 3677 | UINT32 LMLinkSpeed2:1 ; ///< |
| 3678 | UINT32 Reserved_23_22:2 ; ///< |
| 3679 | UINT32 LMTxPhyCmd3:3 ; ///< |
| 3680 | UINT32 LMRxPhyCmd3:2 ; ///< |
| 3681 | UINT32 LMLinkSpeed3:1 ; ///< |
| 3682 | UINT32 Reserved_31_30:2 ; ///< |
| 3683 | } Field; ///< |
| 3684 | UINT32 Value; ///< |
| 3685 | } D0F0xE4_WRAP_8025_STRUCT; |
| 3686 | |
| 3687 | // **** D0F0xE4_WRAP_8031 Register Definition **** |
| 3688 | // Address |
| 3689 | #define D0F0xE4_WRAP_8031_ADDRESS 0x8031 |
| 3690 | |
| 3691 | // Type |
| 3692 | #define D0F0xE4_WRAP_8031_TYPE TYPE_D0F0xE4 |
| 3693 | // Field Data |
| 3694 | #define D0F0xE4_WRAP_8031_LnCntBandwidth_OFFSET 0 |
| 3695 | #define D0F0xE4_WRAP_8031_LnCntBandwidth_WIDTH 10 |
| 3696 | #define D0F0xE4_WRAP_8031_LnCntBandwidth_MASK 0x3ff |
| 3697 | #define D0F0xE4_WRAP_8031_Reserved_15_10_OFFSET 10 |
| 3698 | #define D0F0xE4_WRAP_8031_Reserved_15_10_WIDTH 6 |
| 3699 | #define D0F0xE4_WRAP_8031_Reserved_15_10_MASK 0xfc00 |
| 3700 | #define D0F0xE4_WRAP_8031_LnCntValid_OFFSET 16 |
| 3701 | #define D0F0xE4_WRAP_8031_LnCntValid_WIDTH 1 |
| 3702 | #define D0F0xE4_WRAP_8031_LnCntValid_MASK 0x10000 |
| 3703 | #define D0F0xE4_WRAP_8031_Reserved_31_17_OFFSET 17 |
| 3704 | #define D0F0xE4_WRAP_8031_Reserved_31_17_WIDTH 15 |
| 3705 | #define D0F0xE4_WRAP_8031_Reserved_31_17_MASK 0xfffe0000 |
| 3706 | |
| 3707 | /// D0F0xE4_WRAP_8031 |
| 3708 | typedef union { |
| 3709 | struct { ///< |
| 3710 | UINT32 LnCntBandwidth:10; ///< |
| 3711 | UINT32 Reserved_15_10:6 ; ///< |
| 3712 | UINT32 LnCntValid:1 ; ///< |
| 3713 | UINT32 Reserved_31_17:15; ///< |
| 3714 | } Field; ///< |
| 3715 | UINT32 Value; ///< |
| 3716 | } D0F0xE4_WRAP_8031_STRUCT; |
| 3717 | |
| 3718 | /// D0F0xE4_WRAP_8040 |
| 3719 | typedef union { |
| 3720 | struct { ///< |
| 3721 | UINT32 OwnPhyA:1 ; ///< |
| 3722 | UINT32 OwnPhyB:1 ; ///< |
| 3723 | UINT32 OwnPhyC:1 ; ///< |
| 3724 | UINT32 OwnPhyD:1 ; ///< |
| 3725 | UINT32 Reserved_7_4:4 ; ///< |
| 3726 | UINT32 DigaPwrdnValue:3 ; ///< |
| 3727 | UINT32 Reserved_11_11:1 ; ///< |
| 3728 | UINT32 DigbPwrdnValue:3 ; ///< |
| 3729 | UINT32 Reserved_15_15:1 ; ///< |
| 3730 | UINT32 CntPhyA:1 ; ///< |
| 3731 | UINT32 CntPhyB:1 ; ///< |
| 3732 | UINT32 CntPhyC:1 ; ///< |
| 3733 | UINT32 CntPhyD:1 ; ///< |
| 3734 | UINT32 CntDigA:1 ; ///< |
| 3735 | UINT32 CntDigB:1 ; ///< |
| 3736 | UINT32 ChangeLnSpd:1 ; ///< |
| 3737 | UINT32 Reserved_31_23:9 ; ///< |
| 3738 | } Field; ///< |
| 3739 | UINT32 Value; ///< |
| 3740 | } ex502_STRUCT; |
| 3741 | |
| 3742 | // **** D0F0xE4_WRAP_8060 Register Definition **** |
| 3743 | // Address |
| 3744 | #define D0F0xE4_WRAP_8060_ADDRESS 0x8060 |
| 3745 | |
| 3746 | // Type |
| 3747 | #define D0F0xE4_WRAP_8060_TYPE TYPE_D0F0xE4 |
| 3748 | // Field Data |
| 3749 | #define D0F0xE4_WRAP_8060_Reconfigure_OFFSET 0 |
| 3750 | #define D0F0xE4_WRAP_8060_Reconfigure_WIDTH 1 |
| 3751 | #define D0F0xE4_WRAP_8060_Reconfigure_MASK 0x1 |
| 3752 | #define D0F0xE4_WRAP_8060_Reserved_1_1_OFFSET 1 |
| 3753 | #define D0F0xE4_WRAP_8060_Reserved_1_1_WIDTH 1 |
| 3754 | #define D0F0xE4_WRAP_8060_Reserved_1_1_MASK 0x2 |
| 3755 | #define D0F0xE4_WRAP_8060_ResetComplete_OFFSET 2 |
| 3756 | #define D0F0xE4_WRAP_8060_ResetComplete_WIDTH 1 |
| 3757 | #define D0F0xE4_WRAP_8060_ResetComplete_MASK 0x4 |
| 3758 | #define D0F0xE4_WRAP_8060_Reserved_15_3_OFFSET 3 |
| 3759 | #define D0F0xE4_WRAP_8060_Reserved_15_3_WIDTH 13 |
| 3760 | #define D0F0xE4_WRAP_8060_Reserved_15_3_MASK 0xfff8 |
| 3761 | #define D0F0xE4_WRAP_8060_Reserved_31_18_OFFSET 18 |
| 3762 | #define D0F0xE4_WRAP_8060_Reserved_31_18_WIDTH 14 |
| 3763 | #define D0F0xE4_WRAP_8060_Reserved_31_18_MASK 0xfffc0000 |
| 3764 | |
| 3765 | /// D0F0xE4_WRAP_8060 |
| 3766 | typedef union { |
| 3767 | struct { ///< |
| 3768 | UINT32 Reconfigure:1 ; ///< |
| 3769 | UINT32 Reserved_1_1:1 ; ///< |
| 3770 | UINT32 ResetComplete:1 ; ///< |
| 3771 | UINT32 Reserved_15_3:13; ///< |
| 3772 | UINT32 :1 ; ///< |
| 3773 | UINT32 :1 ; ///< |
| 3774 | UINT32 Reserved_31_18:14; ///< |
| 3775 | } Field; ///< |
| 3776 | UINT32 Value; ///< |
| 3777 | } D0F0xE4_WRAP_8060_STRUCT; |
| 3778 | |
| 3779 | // **** D0F0xE4_WRAP_8062 Register Definition **** |
| 3780 | // Address |
| 3781 | #define D0F0xE4_WRAP_8062_ADDRESS 0x8062 |
| 3782 | |
| 3783 | // Type |
| 3784 | #define D0F0xE4_WRAP_8062_TYPE TYPE_D0F0xE4 |
| 3785 | // Field Data |
| 3786 | #define D0F0xE4_WRAP_8062_ReconfigureEn_OFFSET 0 |
| 3787 | #define D0F0xE4_WRAP_8062_ReconfigureEn_WIDTH 1 |
| 3788 | #define D0F0xE4_WRAP_8062_ReconfigureEn_MASK 0x1 |
| 3789 | #define D0F0xE4_WRAP_8062_Reserved_1_1_OFFSET 1 |
| 3790 | #define D0F0xE4_WRAP_8062_Reserved_1_1_WIDTH 1 |
| 3791 | #define D0F0xE4_WRAP_8062_Reserved_1_1_MASK 0x2 |
| 3792 | #define D0F0xE4_WRAP_8062_ResetPeriod_OFFSET 2 |
| 3793 | #define D0F0xE4_WRAP_8062_ResetPeriod_WIDTH 3 |
| 3794 | #define D0F0xE4_WRAP_8062_ResetPeriod_MASK 0x1c |
| 3795 | #define D0F0xE4_WRAP_8062_Reserved_9_5_OFFSET 5 |
| 3796 | #define D0F0xE4_WRAP_8062_Reserved_9_5_WIDTH 5 |
| 3797 | #define D0F0xE4_WRAP_8062_Reserved_9_5_MASK 0x3e0 |
| 3798 | #define D0F0xE4_WRAP_8062_BlockOnIdle_OFFSET 10 |
| 3799 | #define D0F0xE4_WRAP_8062_BlockOnIdle_WIDTH 1 |
| 3800 | #define D0F0xE4_WRAP_8062_BlockOnIdle_MASK 0x400 |
| 3801 | #define D0F0xE4_WRAP_8062_ConfigXferMode_OFFSET 11 |
| 3802 | #define D0F0xE4_WRAP_8062_ConfigXferMode_WIDTH 1 |
| 3803 | #define D0F0xE4_WRAP_8062_ConfigXferMode_MASK 0x800 |
| 3804 | #define D0F0xE4_WRAP_8062_Reserved_31_12_OFFSET 12 |
| 3805 | #define D0F0xE4_WRAP_8062_Reserved_31_12_WIDTH 20 |
| 3806 | #define D0F0xE4_WRAP_8062_Reserved_31_12_MASK 0xfffff000 |
| 3807 | |
| 3808 | /// D0F0xE4_WRAP_8062 |
| 3809 | typedef union { |
| 3810 | struct { ///< |
| 3811 | UINT32 ReconfigureEn:1 ; ///< |
| 3812 | UINT32 Reserved_1_1:1 ; ///< |
| 3813 | UINT32 ResetPeriod:3 ; ///< |
| 3814 | UINT32 Reserved_9_5:5 ; ///< |
| 3815 | UINT32 BlockOnIdle:1 ; ///< |
| 3816 | UINT32 ConfigXferMode:1 ; ///< |
| 3817 | UINT32 Reserved_31_12:20; ///< |
| 3818 | } Field; ///< |
| 3819 | UINT32 Value; ///< |
| 3820 | } D0F0xE4_WRAP_8062_STRUCT; |
| 3821 | |
| 3822 | // **** D0F0xE4_WRAP_80F0 Register Definition **** |
| 3823 | // Address |
| 3824 | #define D0F0xE4_WRAP_80F0_ADDRESS 0x80f0 |
| 3825 | |
| 3826 | // Type |
| 3827 | #define D0F0xE4_WRAP_80F0_TYPE TYPE_D0F0xE4 |
| 3828 | // Field Data |
| 3829 | #define D0F0xE4_WRAP_80F0_MicroSeconds_OFFSET 0 |
| 3830 | #define D0F0xE4_WRAP_80F0_MicroSeconds_WIDTH 32 |
| 3831 | #define D0F0xE4_WRAP_80F0_MicroSeconds_MASK 0xffffffff |
| 3832 | |
| 3833 | /// D0F0xE4_WRAP_80F0 |
| 3834 | typedef union { |
| 3835 | struct { ///< |
| 3836 | UINT32 MicroSeconds:32; ///< |
| 3837 | } Field; ///< |
| 3838 | UINT32 Value; ///< |
| 3839 | } D0F0xE4_WRAP_80F0_STRUCT; |
| 3840 | |
| 3841 | // **** D0F0xE4_WRAP_80F1 Register Definition **** |
| 3842 | // Address |
| 3843 | #define D0F0xE4_WRAP_80F1_ADDRESS 0x80f1 |
| 3844 | |
| 3845 | // Type |
| 3846 | #define D0F0xE4_WRAP_80F1_TYPE TYPE_D0F0xE4 |
| 3847 | // Field Data |
| 3848 | #define D0F0xE4_WRAP_80F1_ClockRate_OFFSET 0 |
| 3849 | #define D0F0xE4_WRAP_80F1_ClockRate_WIDTH 8 |
| 3850 | #define D0F0xE4_WRAP_80F1_ClockRate_MASK 0xff |
| 3851 | #define D0F0xE4_WRAP_80F1_Reserved_31_8_OFFSET 8 |
| 3852 | #define D0F0xE4_WRAP_80F1_Reserved_31_8_WIDTH 24 |
| 3853 | #define D0F0xE4_WRAP_80F1_Reserved_31_8_MASK 0xffffff00 |
| 3854 | |
| 3855 | /// D0F0xE4_WRAP_80F1 |
| 3856 | typedef union { |
| 3857 | struct { ///< |
| 3858 | UINT32 ClockRate:8 ; ///< |
| 3859 | UINT32 Reserved_31_8:24; ///< |
| 3860 | } Field; ///< |
| 3861 | UINT32 Value; ///< |
| 3862 | } D0F0xE4_WRAP_80F1_STRUCT; |
| 3863 | |
| 3864 | // **** D0F0xE4_PIF_0010 Register Definition **** |
| 3865 | // Address |
| 3866 | #define D0F0xE4_PIF_0010_ADDRESS 0x10 |
| 3867 | |
| 3868 | // Type |
| 3869 | #define D0F0xE4_PIF_0010_TYPE TYPE_D0F0xE4 |
| 3870 | // Field Data |
| 3871 | #define D0F0xE4_PIF_0010_Reserved_3_0_OFFSET 0 |
| 3872 | #define D0F0xE4_PIF_0010_Reserved_3_0_WIDTH 4 |
| 3873 | #define D0F0xE4_PIF_0010_Reserved_3_0_MASK 0xf |
| 3874 | #define D0F0xE4_PIF_0010_EiDetCycleMode_OFFSET 4 |
| 3875 | #define D0F0xE4_PIF_0010_EiDetCycleMode_WIDTH 1 |
| 3876 | #define D0F0xE4_PIF_0010_EiDetCycleMode_MASK 0x10 |
| 3877 | #define D0F0xE4_PIF_0010_Reserved_5_5_OFFSET 5 |
| 3878 | #define D0F0xE4_PIF_0010_Reserved_5_5_WIDTH 1 |
| 3879 | #define D0F0xE4_PIF_0010_Reserved_5_5_MASK 0x20 |
| 3880 | #define D0F0xE4_PIF_0010_RxDetectFifoResetMode_OFFSET 6 |
| 3881 | #define D0F0xE4_PIF_0010_RxDetectFifoResetMode_WIDTH 1 |
| 3882 | #define D0F0xE4_PIF_0010_RxDetectFifoResetMode_MASK 0x40 |
| 3883 | #define D0F0xE4_PIF_0010_RxDetectTxPwrMode_OFFSET 7 |
| 3884 | #define D0F0xE4_PIF_0010_RxDetectTxPwrMode_WIDTH 1 |
| 3885 | #define D0F0xE4_PIF_0010_RxDetectTxPwrMode_MASK 0x80 |
| 3886 | #define D0F0xE4_PIF_0010_Reserved_16_8_OFFSET 8 |
| 3887 | #define D0F0xE4_PIF_0010_Reserved_16_8_WIDTH 9 |
| 3888 | #define D0F0xE4_PIF_0010_Reserved_16_8_MASK 0x1ff00 |
| 3889 | #define D0F0xE4_PIF_0010_Ls2ExitTime_OFFSET 17 |
| 3890 | #define D0F0xE4_PIF_0010_Ls2ExitTime_WIDTH 3 |
| 3891 | #define D0F0xE4_PIF_0010_Ls2ExitTime_MASK 0xe0000 |
| 3892 | #define D0F0xE4_PIF_0010_Reserved_31_23_OFFSET 23 |
| 3893 | #define D0F0xE4_PIF_0010_Reserved_31_23_WIDTH 9 |
| 3894 | #define D0F0xE4_PIF_0010_Reserved_31_23_MASK 0xff800000 |
| 3895 | |
| 3896 | /// D0F0xE4_PIF_0010 |
| 3897 | typedef union { |
| 3898 | struct { ///< |
| 3899 | UINT32 Reserved_3_0:4 ; ///< |
| 3900 | UINT32 EiDetCycleMode:1 ; ///< |
| 3901 | UINT32 Reserved_5_5:1 ; ///< |
| 3902 | UINT32 RxDetectFifoResetMode:1 ; ///< |
| 3903 | UINT32 RxDetectTxPwrMode:1 ; ///< |
| 3904 | UINT32 Reserved_16_8:9 ; ///< |
| 3905 | UINT32 Ls2ExitTime:3 ; ///< |
| 3906 | UINT32 :3 ; ///< |
| 3907 | UINT32 Reserved_31_23:9 ; ///< |
| 3908 | } Field; ///< |
| 3909 | UINT32 Value; ///< |
| 3910 | } D0F0xE4_PIF_0010_STRUCT; |
| 3911 | |
| 3912 | // **** D0F0xE4_PIF_0011 Register Definition **** |
| 3913 | // Address |
| 3914 | #define D0F0xE4_PIF_0011_ADDRESS 0x11 |
| 3915 | |
| 3916 | // Type |
| 3917 | #define D0F0xE4_PIF_0011_TYPE TYPE_D0F0xE4 |
| 3918 | // Field Data |
| 3919 | #define D0F0xE4_PIF_0011_X2Lane10_OFFSET 0 |
| 3920 | #define D0F0xE4_PIF_0011_X2Lane10_WIDTH 1 |
| 3921 | #define D0F0xE4_PIF_0011_X2Lane10_MASK 0x1 |
| 3922 | #define D0F0xE4_PIF_0011_X2Lane32_OFFSET 1 |
| 3923 | #define D0F0xE4_PIF_0011_X2Lane32_WIDTH 1 |
| 3924 | #define D0F0xE4_PIF_0011_X2Lane32_MASK 0x2 |
| 3925 | #define D0F0xE4_PIF_0011_X2Lane54_OFFSET 2 |
| 3926 | #define D0F0xE4_PIF_0011_X2Lane54_WIDTH 1 |
| 3927 | #define D0F0xE4_PIF_0011_X2Lane54_MASK 0x4 |
| 3928 | #define D0F0xE4_PIF_0011_X2Lane76_OFFSET 3 |
| 3929 | #define D0F0xE4_PIF_0011_X2Lane76_WIDTH 1 |
| 3930 | #define D0F0xE4_PIF_0011_X2Lane76_MASK 0x8 |
| 3931 | #define D0F0xE4_PIF_0011_Reserved_7_4_OFFSET 4 |
| 3932 | #define D0F0xE4_PIF_0011_Reserved_7_4_WIDTH 4 |
| 3933 | #define D0F0xE4_PIF_0011_Reserved_7_4_MASK 0xf0 |
| 3934 | #define D0F0xE4_PIF_0011_X4Lane30_OFFSET 8 |
| 3935 | #define D0F0xE4_PIF_0011_X4Lane30_WIDTH 1 |
| 3936 | #define D0F0xE4_PIF_0011_X4Lane30_MASK 0x100 |
| 3937 | #define D0F0xE4_PIF_0011_X4Lane74_OFFSET 9 |
| 3938 | #define D0F0xE4_PIF_0011_X4Lane74_WIDTH 1 |
| 3939 | #define D0F0xE4_PIF_0011_X4Lane74_MASK 0x200 |
| 3940 | #define D0F0xE4_PIF_0011_Reserved_11_10_OFFSET 10 |
| 3941 | #define D0F0xE4_PIF_0011_Reserved_11_10_WIDTH 2 |
| 3942 | #define D0F0xE4_PIF_0011_Reserved_11_10_MASK 0xc00 |
| 3943 | #define D0F0xE4_PIF_0011_X4Lane52_OFFSET 12 |
| 3944 | #define D0F0xE4_PIF_0011_X4Lane52_WIDTH 1 |
| 3945 | #define D0F0xE4_PIF_0011_X4Lane52_MASK 0x1000 |
| 3946 | #define D0F0xE4_PIF_0011_Reserved_15_13_OFFSET 13 |
| 3947 | #define D0F0xE4_PIF_0011_Reserved_15_13_WIDTH 3 |
| 3948 | #define D0F0xE4_PIF_0011_Reserved_15_13_MASK 0xe000 |
| 3949 | #define D0F0xE4_PIF_0011_X8Lane70_OFFSET 16 |
| 3950 | #define D0F0xE4_PIF_0011_X8Lane70_WIDTH 1 |
| 3951 | #define D0F0xE4_PIF_0011_X8Lane70_MASK 0x10000 |
| 3952 | #define D0F0xE4_PIF_0011_Reserved_24_17_OFFSET 17 |
| 3953 | #define D0F0xE4_PIF_0011_Reserved_24_17_WIDTH 8 |
| 3954 | #define D0F0xE4_PIF_0011_Reserved_24_17_MASK 0x1fe0000 |
| 3955 | #define D0F0xE4_PIF_0011_MultiPif_OFFSET 25 |
| 3956 | #define D0F0xE4_PIF_0011_MultiPif_WIDTH 1 |
| 3957 | #define D0F0xE4_PIF_0011_MultiPif_MASK 0x2000000 |
| 3958 | #define D0F0xE4_PIF_0011_Reserved_31_26_OFFSET 26 |
| 3959 | #define D0F0xE4_PIF_0011_Reserved_31_26_WIDTH 6 |
| 3960 | #define D0F0xE4_PIF_0011_Reserved_31_26_MASK 0xfc000000 |
| 3961 | |
| 3962 | /// D0F0xE4_PIF_0011 |
| 3963 | typedef union { |
| 3964 | struct { ///< |
| 3965 | UINT32 X2Lane10:1 ; ///< |
| 3966 | UINT32 X2Lane32:1 ; ///< |
| 3967 | UINT32 X2Lane54:1 ; ///< |
| 3968 | UINT32 X2Lane76:1 ; ///< |
| 3969 | UINT32 Reserved_7_4:4 ; ///< |
| 3970 | UINT32 X4Lane30:1 ; ///< |
| 3971 | UINT32 X4Lane74:1 ; ///< |
| 3972 | UINT32 Reserved_11_10:2 ; ///< |
| 3973 | UINT32 X4Lane52:1 ; ///< |
| 3974 | UINT32 Reserved_15_13:3 ; ///< |
| 3975 | UINT32 X8Lane70:1 ; ///< |
| 3976 | UINT32 Reserved_24_17:8 ; ///< |
| 3977 | UINT32 MultiPif:1 ; ///< |
| 3978 | UINT32 Reserved_31_26:6 ; ///< |
| 3979 | } Field; ///< |
| 3980 | UINT32 Value; ///< |
| 3981 | } D0F0xE4_PIF_0011_STRUCT; |
| 3982 | |
| 3983 | // **** D0F0xE4_PIF_0012 Register Definition **** |
| 3984 | // Address |
| 3985 | #define D0F0xE4_PIF_0012_ADDRESS 0x12 |
| 3986 | |
| 3987 | // Type |
| 3988 | #define D0F0xE4_PIF_0012_TYPE TYPE_D0F0xE4 |
| 3989 | // Field Data |
| 3990 | #define D0F0xE4_PIF_0012_TxPowerStateInTxs2_OFFSET 0 |
| 3991 | #define D0F0xE4_PIF_0012_TxPowerStateInTxs2_WIDTH 3 |
| 3992 | #define D0F0xE4_PIF_0012_TxPowerStateInTxs2_MASK 0x7 |
| 3993 | #define D0F0xE4_PIF_0012_ForceRxEnInL0s_OFFSET 3 |
| 3994 | #define D0F0xE4_PIF_0012_ForceRxEnInL0s_WIDTH 1 |
| 3995 | #define D0F0xE4_PIF_0012_ForceRxEnInL0s_MASK 0x8 |
| 3996 | #define D0F0xE4_PIF_0012_RxPowerStateInRxs2_OFFSET 4 |
| 3997 | #define D0F0xE4_PIF_0012_RxPowerStateInRxs2_WIDTH 3 |
| 3998 | #define D0F0xE4_PIF_0012_RxPowerStateInRxs2_MASK 0x70 |
| 3999 | #define D0F0xE4_PIF_0012_PllPowerStateInTxs2_OFFSET 7 |
| 4000 | #define D0F0xE4_PIF_0012_PllPowerStateInTxs2_WIDTH 3 |
| 4001 | #define D0F0xE4_PIF_0012_PllPowerStateInTxs2_MASK 0x380 |
| 4002 | #define D0F0xE4_PIF_0012_PllPowerStateInOff_OFFSET 10 |
| 4003 | #define D0F0xE4_PIF_0012_PllPowerStateInOff_WIDTH 3 |
| 4004 | #define D0F0xE4_PIF_0012_PllPowerStateInOff_MASK 0x1c00 |
| 4005 | #define D0F0xE4_PIF_0012_Reserved_15_13_OFFSET 13 |
| 4006 | #define D0F0xE4_PIF_0012_Reserved_15_13_WIDTH 3 |
| 4007 | #define D0F0xE4_PIF_0012_Reserved_15_13_MASK 0xe000 |
| 4008 | #define D0F0xE4_PIF_0012_Tx2p5clkClockGatingEn_OFFSET 16 |
| 4009 | #define D0F0xE4_PIF_0012_Tx2p5clkClockGatingEn_WIDTH 1 |
| 4010 | #define D0F0xE4_PIF_0012_Tx2p5clkClockGatingEn_MASK 0x10000 |
| 4011 | #define D0F0xE4_PIF_0012_Reserved_23_17_OFFSET 17 |
| 4012 | #define D0F0xE4_PIF_0012_Reserved_23_17_WIDTH 7 |
| 4013 | #define D0F0xE4_PIF_0012_Reserved_23_17_MASK 0xfe0000 |
| 4014 | #define D0F0xE4_PIF_0012_PllRampUpTime_OFFSET 24 |
| 4015 | #define D0F0xE4_PIF_0012_PllRampUpTime_WIDTH 3 |
| 4016 | #define D0F0xE4_PIF_0012_PllRampUpTime_MASK 0x7000000 |
| 4017 | #define D0F0xE4_PIF_0012_Reserved_27_27_OFFSET 27 |
| 4018 | #define D0F0xE4_PIF_0012_Reserved_27_27_WIDTH 1 |
| 4019 | #define D0F0xE4_PIF_0012_Reserved_27_27_MASK 0x8000000 |
| 4020 | #define D0F0xE4_PIF_0012_PllPwrOverrideEn_OFFSET 28 |
| 4021 | #define D0F0xE4_PIF_0012_PllPwrOverrideEn_WIDTH 1 |
| 4022 | #define D0F0xE4_PIF_0012_PllPwrOverrideEn_MASK 0x10000000 |
| 4023 | #define D0F0xE4_PIF_0012_PllPwrOverrideVal_OFFSET 29 |
| 4024 | #define D0F0xE4_PIF_0012_PllPwrOverrideVal_WIDTH 3 |
| 4025 | #define D0F0xE4_PIF_0012_PllPwrOverrideVal_MASK 0xe0000000 |
| 4026 | |
| 4027 | /// D0F0xE4_PIF_0012 |
| 4028 | typedef union { |
| 4029 | struct { ///< |
| 4030 | UINT32 TxPowerStateInTxs2:3 ; ///< |
| 4031 | UINT32 ForceRxEnInL0s:1 ; ///< |
| 4032 | UINT32 RxPowerStateInRxs2:3 ; ///< |
| 4033 | UINT32 PllPowerStateInTxs2:3 ; ///< |
| 4034 | UINT32 PllPowerStateInOff:3 ; ///< |
| 4035 | UINT32 Reserved_15_13:3 ; ///< |
| 4036 | UINT32 Tx2p5clkClockGatingEn:1 ; ///< |
| 4037 | UINT32 Reserved_23_17:7 ; ///< |
| 4038 | UINT32 PllRampUpTime:3 ; ///< |
| 4039 | UINT32 Reserved_27_27:1 ; ///< |
| 4040 | UINT32 PllPwrOverrideEn:1 ; ///< |
| 4041 | UINT32 PllPwrOverrideVal:3 ; ///< |
| 4042 | } Field; ///< |
| 4043 | UINT32 Value; ///< |
| 4044 | } D0F0xE4_PIF_0012_STRUCT; |
| 4045 | |
| 4046 | // **** D0F0xE4_PIF_0013 Register Definition **** |
| 4047 | // Address |
| 4048 | #define D0F0xE4_PIF_0013_ADDRESS 0x13 |
| 4049 | |
| 4050 | // Type |
| 4051 | #define D0F0xE4_PIF_0013_TYPE TYPE_D0F0xE4 |
| 4052 | // Field Data |
| 4053 | #define D0F0xE4_PIF_0013_TxPowerStateInTxs2_OFFSET 0 |
| 4054 | #define D0F0xE4_PIF_0013_TxPowerStateInTxs2_WIDTH 3 |
| 4055 | #define D0F0xE4_PIF_0013_TxPowerStateInTxs2_MASK 0x7 |
| 4056 | #define D0F0xE4_PIF_0013_ForceRxEnInL0s_OFFSET 3 |
| 4057 | #define D0F0xE4_PIF_0013_ForceRxEnInL0s_WIDTH 1 |
| 4058 | #define D0F0xE4_PIF_0013_ForceRxEnInL0s_MASK 0x8 |
| 4059 | #define D0F0xE4_PIF_0013_RxPowerStateInRxs2_OFFSET 4 |
| 4060 | #define D0F0xE4_PIF_0013_RxPowerStateInRxs2_WIDTH 3 |
| 4061 | #define D0F0xE4_PIF_0013_RxPowerStateInRxs2_MASK 0x70 |
| 4062 | #define D0F0xE4_PIF_0013_PllPowerStateInTxs2_OFFSET 7 |
| 4063 | #define D0F0xE4_PIF_0013_PllPowerStateInTxs2_WIDTH 3 |
| 4064 | #define D0F0xE4_PIF_0013_PllPowerStateInTxs2_MASK 0x380 |
| 4065 | #define D0F0xE4_PIF_0013_PllPowerStateInOff_OFFSET 10 |
| 4066 | #define D0F0xE4_PIF_0013_PllPowerStateInOff_WIDTH 3 |
| 4067 | #define D0F0xE4_PIF_0013_PllPowerStateInOff_MASK 0x1c00 |
| 4068 | #define D0F0xE4_PIF_0013_Reserved_15_13_OFFSET 13 |
| 4069 | #define D0F0xE4_PIF_0013_Reserved_15_13_WIDTH 3 |
| 4070 | #define D0F0xE4_PIF_0013_Reserved_15_13_MASK 0xe000 |
| 4071 | #define D0F0xE4_PIF_0013_Tx2p5clkClockGatingEn_OFFSET 16 |
| 4072 | #define D0F0xE4_PIF_0013_Tx2p5clkClockGatingEn_WIDTH 1 |
| 4073 | #define D0F0xE4_PIF_0013_Tx2p5clkClockGatingEn_MASK 0x10000 |
| 4074 | #define D0F0xE4_PIF_0013_Reserved_23_17_OFFSET 17 |
| 4075 | #define D0F0xE4_PIF_0013_Reserved_23_17_WIDTH 7 |
| 4076 | #define D0F0xE4_PIF_0013_Reserved_23_17_MASK 0xfe0000 |
| 4077 | #define D0F0xE4_PIF_0013_PllRampUpTime_OFFSET 24 |
| 4078 | #define D0F0xE4_PIF_0013_PllRampUpTime_WIDTH 3 |
| 4079 | #define D0F0xE4_PIF_0013_PllRampUpTime_MASK 0x7000000 |
| 4080 | #define D0F0xE4_PIF_0013_Reserved_27_27_OFFSET 27 |
| 4081 | #define D0F0xE4_PIF_0013_Reserved_27_27_WIDTH 1 |
| 4082 | #define D0F0xE4_PIF_0013_Reserved_27_27_MASK 0x8000000 |
| 4083 | #define D0F0xE4_PIF_0013_PllPwrOverrideEn_OFFSET 28 |
| 4084 | #define D0F0xE4_PIF_0013_PllPwrOverrideEn_WIDTH 1 |
| 4085 | #define D0F0xE4_PIF_0013_PllPwrOverrideEn_MASK 0x10000000 |
| 4086 | #define D0F0xE4_PIF_0013_PllPwrOverrideVal_OFFSET 29 |
| 4087 | #define D0F0xE4_PIF_0013_PllPwrOverrideVal_WIDTH 3 |
| 4088 | #define D0F0xE4_PIF_0013_PllPwrOverrideVal_MASK 0xe0000000 |
| 4089 | |
| 4090 | /// D0F0xE4_PIF_0013 |
| 4091 | typedef union { |
| 4092 | struct { ///< |
| 4093 | UINT32 TxPowerStateInTxs2:3 ; ///< |
| 4094 | UINT32 ForceRxEnInL0s:1 ; ///< |
| 4095 | UINT32 RxPowerStateInRxs2:3 ; ///< |
| 4096 | UINT32 PllPowerStateInTxs2:3 ; ///< |
| 4097 | UINT32 PllPowerStateInOff:3 ; ///< |
| 4098 | UINT32 Reserved_15_13:3 ; ///< |
| 4099 | UINT32 Tx2p5clkClockGatingEn:1 ; ///< |
| 4100 | UINT32 Reserved_23_17:7 ; ///< |
| 4101 | UINT32 PllRampUpTime:3 ; ///< |
| 4102 | UINT32 Reserved_27_27:1 ; ///< |
| 4103 | UINT32 PllPwrOverrideEn:1 ; ///< |
| 4104 | UINT32 PllPwrOverrideVal:3 ; ///< |
| 4105 | } Field; ///< |
| 4106 | UINT32 Value; ///< |
| 4107 | } D0F0xE4_PIF_0013_STRUCT; |
| 4108 | |
| 4109 | // **** D0F0xE4_PIF_0015 Register Definition **** |
| 4110 | // Address |
| 4111 | #define D0F0xE4_PIF_0015_ADDRESS 0x15 |
| 4112 | |
| 4113 | // Type |
| 4114 | #define D0F0xE4_PIF_0015_TYPE TYPE_D0F0xE4 |
| 4115 | // Field Data |
| 4116 | #define D0F0xE4_PIF_0015_TxPhyStatus00_OFFSET 0 |
| 4117 | #define D0F0xE4_PIF_0015_TxPhyStatus00_WIDTH 1 |
| 4118 | #define D0F0xE4_PIF_0015_TxPhyStatus00_MASK 0x1 |
| 4119 | #define D0F0xE4_PIF_0015_TxPhyStatus01_OFFSET 1 |
| 4120 | #define D0F0xE4_PIF_0015_TxPhyStatus01_WIDTH 1 |
| 4121 | #define D0F0xE4_PIF_0015_TxPhyStatus01_MASK 0x2 |
| 4122 | #define D0F0xE4_PIF_0015_TxPhyStatus02_OFFSET 2 |
| 4123 | #define D0F0xE4_PIF_0015_TxPhyStatus02_WIDTH 1 |
| 4124 | #define D0F0xE4_PIF_0015_TxPhyStatus02_MASK 0x4 |
| 4125 | #define D0F0xE4_PIF_0015_TxPhyStatus03_OFFSET 3 |
| 4126 | #define D0F0xE4_PIF_0015_TxPhyStatus03_WIDTH 1 |
| 4127 | #define D0F0xE4_PIF_0015_TxPhyStatus03_MASK 0x8 |
| 4128 | #define D0F0xE4_PIF_0015_TxPhyStatus04_OFFSET 4 |
| 4129 | #define D0F0xE4_PIF_0015_TxPhyStatus04_WIDTH 1 |
| 4130 | #define D0F0xE4_PIF_0015_TxPhyStatus04_MASK 0x10 |
| 4131 | #define D0F0xE4_PIF_0015_TxPhyStatus05_OFFSET 5 |
| 4132 | #define D0F0xE4_PIF_0015_TxPhyStatus05_WIDTH 1 |
| 4133 | #define D0F0xE4_PIF_0015_TxPhyStatus05_MASK 0x20 |
| 4134 | #define D0F0xE4_PIF_0015_TxPhyStatus06_OFFSET 6 |
| 4135 | #define D0F0xE4_PIF_0015_TxPhyStatus06_WIDTH 1 |
| 4136 | #define D0F0xE4_PIF_0015_TxPhyStatus06_MASK 0x40 |
| 4137 | #define D0F0xE4_PIF_0015_TxPhyStatus07_OFFSET 7 |
| 4138 | #define D0F0xE4_PIF_0015_TxPhyStatus07_WIDTH 1 |
| 4139 | #define D0F0xE4_PIF_0015_TxPhyStatus07_MASK 0x80 |
| 4140 | #define D0F0xE4_PIF_0015_Reserved_31_8_OFFSET 8 |
| 4141 | #define D0F0xE4_PIF_0015_Reserved_31_8_WIDTH 24 |
| 4142 | #define D0F0xE4_PIF_0015_Reserved_31_8_MASK 0xffffff00 |
| 4143 | |
| 4144 | /// D0F0xE4_PIF_0015 |
| 4145 | typedef union { |
| 4146 | struct { ///< |
| 4147 | UINT32 TxPhyStatus00:1 ; ///< |
| 4148 | UINT32 TxPhyStatus01:1 ; ///< |
| 4149 | UINT32 TxPhyStatus02:1 ; ///< |
| 4150 | UINT32 TxPhyStatus03:1 ; ///< |
| 4151 | UINT32 TxPhyStatus04:1 ; ///< |
| 4152 | UINT32 TxPhyStatus05:1 ; ///< |
| 4153 | UINT32 TxPhyStatus06:1 ; ///< |
| 4154 | UINT32 TxPhyStatus07:1 ; ///< |
| 4155 | UINT32 Reserved_31_8:24; ///< |
| 4156 | } Field; ///< |
| 4157 | UINT32 Value; ///< |
| 4158 | } D0F0xE4_PIF_0015_STRUCT; |
| 4159 | |
| 4160 | // **** D0F0xE4_CORE_0002 Register Definition **** |
| 4161 | // Address |
| 4162 | #define D0F0xE4_CORE_0002_ADDRESS 0x2 |
| 4163 | |
| 4164 | // Type |
| 4165 | #define D0F0xE4_CORE_0002_TYPE TYPE_D0F0xE4 |
| 4166 | // Field Data |
| 4167 | #define D0F0xE4_CORE_0002_HwDebug_0__OFFSET 0 |
| 4168 | #define D0F0xE4_CORE_0002_HwDebug_0__WIDTH 1 |
| 4169 | #define D0F0xE4_CORE_0002_HwDebug_0__MASK 0x1 |
| 4170 | #define D0F0xE4_CORE_0002_Reserved_31_1_OFFSET 1 |
| 4171 | #define D0F0xE4_CORE_0002_Reserved_31_1_WIDTH 31 |
| 4172 | #define D0F0xE4_CORE_0002_Reserved_31_1_MASK 0xfffffffe |
| 4173 | |
| 4174 | /// D0F0xE4_CORE_0002 |
| 4175 | typedef union { |
| 4176 | struct { ///< |
| 4177 | UINT32 HwDebug_0_:1 ; ///< |
| 4178 | UINT32 Reserved_31_1:31; ///< |
| 4179 | } Field; ///< |
| 4180 | UINT32 Value; ///< |
| 4181 | } D0F0xE4_CORE_0002_STRUCT; |
| 4182 | |
| 4183 | |
| 4184 | |
| 4185 | // **** D0F0xE4_CORE_001C Register Definition **** |
| 4186 | // Address |
| 4187 | #define D0F0xE4_CORE_001C_ADDRESS 0x1c |
| 4188 | |
| 4189 | // Type |
| 4190 | #define D0F0xE4_CORE_001C_TYPE TYPE_D0F0xE4 |
| 4191 | // Field Data |
| 4192 | #define D0F0xE4_CORE_001C_TxArbRoundRobinEn_OFFSET 0 |
| 4193 | #define D0F0xE4_CORE_001C_TxArbRoundRobinEn_WIDTH 1 |
| 4194 | #define D0F0xE4_CORE_001C_TxArbRoundRobinEn_MASK 0x1 |
| 4195 | #define D0F0xE4_CORE_001C_TxArbSlvLimit_OFFSET 1 |
| 4196 | #define D0F0xE4_CORE_001C_TxArbSlvLimit_WIDTH 5 |
| 4197 | #define D0F0xE4_CORE_001C_TxArbSlvLimit_MASK 0x3e |
| 4198 | #define D0F0xE4_CORE_001C_TxArbMstLimit_OFFSET 6 |
| 4199 | #define D0F0xE4_CORE_001C_TxArbMstLimit_WIDTH 5 |
| 4200 | #define D0F0xE4_CORE_001C_TxArbMstLimit_MASK 0x7c0 |
| 4201 | #define D0F0xE4_CORE_001C_Reserved_31_11_OFFSET 11 |
| 4202 | #define D0F0xE4_CORE_001C_Reserved_31_11_WIDTH 21 |
| 4203 | #define D0F0xE4_CORE_001C_Reserved_31_11_MASK 0xfffff800 |
| 4204 | |
| 4205 | /// D0F0xE4_CORE_001C |
| 4206 | typedef union { |
| 4207 | struct { ///< |
| 4208 | UINT32 TxArbRoundRobinEn:1 ; ///< |
| 4209 | UINT32 TxArbSlvLimit:5 ; ///< |
| 4210 | UINT32 TxArbMstLimit:5 ; ///< |
| 4211 | UINT32 Reserved_31_11:21; ///< |
| 4212 | } Field; ///< |
| 4213 | UINT32 Value; ///< |
| 4214 | } D0F0xE4_CORE_001C_STRUCT; |
| 4215 | |
| 4216 | // **** D0F0xE4_CORE_0040 Register Definition **** |
| 4217 | // Address |
| 4218 | #define D0F0xE4_CORE_0040_ADDRESS 0x40 |
| 4219 | |
| 4220 | // Type |
| 4221 | #define D0F0xE4_CORE_0040_TYPE TYPE_D0F0xE4 |
| 4222 | // Field Data |
| 4223 | #define D0F0xE4_CORE_0040_Reserved_13_0_OFFSET 0 |
| 4224 | #define D0F0xE4_CORE_0040_Reserved_13_0_WIDTH 14 |
| 4225 | #define D0F0xE4_CORE_0040_Reserved_13_0_MASK 0x3fff |
| 4226 | #define D0F0xE4_CORE_0040_PElecIdleMode_OFFSET 14 |
| 4227 | #define D0F0xE4_CORE_0040_PElecIdleMode_WIDTH 2 |
| 4228 | #define D0F0xE4_CORE_0040_PElecIdleMode_MASK 0xc000 |
| 4229 | #define D0F0xE4_CORE_0040_Reserved_31_16_OFFSET 16 |
| 4230 | #define D0F0xE4_CORE_0040_Reserved_31_16_WIDTH 16 |
| 4231 | #define D0F0xE4_CORE_0040_Reserved_31_16_MASK 0xffff0000 |
| 4232 | |
| 4233 | /// D0F0xE4_CORE_0040 |
| 4234 | typedef union { |
| 4235 | struct { ///< |
| 4236 | UINT32 Reserved_13_0:14; ///< |
| 4237 | UINT32 PElecIdleMode:2 ; ///< |
| 4238 | UINT32 Reserved_31_16:16; ///< |
| 4239 | } Field; ///< |
| 4240 | UINT32 Value; ///< |
| 4241 | } D0F0xE4_CORE_0040_STRUCT; |
| 4242 | |
| 4243 | // **** D0F0xE4_CORE_00B0 Register Definition **** |
| 4244 | // Address |
| 4245 | #define D0F0xE4_CORE_00B0_ADDRESS 0xb0 |
| 4246 | |
| 4247 | // Type |
| 4248 | #define D0F0xE4_CORE_00B0_TYPE TYPE_D0F0xE4 |
| 4249 | // Field Data |
| 4250 | #define D0F0xE4_CORE_00B0_Reserved_1_0_OFFSET 0 |
| 4251 | #define D0F0xE4_CORE_00B0_Reserved_1_0_WIDTH 2 |
| 4252 | #define D0F0xE4_CORE_00B0_Reserved_1_0_MASK 0x3 |
| 4253 | #define D0F0xE4_CORE_00B0_StrapF0MsiEn_OFFSET 2 |
| 4254 | #define D0F0xE4_CORE_00B0_StrapF0MsiEn_WIDTH 1 |
| 4255 | #define D0F0xE4_CORE_00B0_StrapF0MsiEn_MASK 0x4 |
| 4256 | #define D0F0xE4_CORE_00B0_Reserved_4_3_OFFSET 3 |
| 4257 | #define D0F0xE4_CORE_00B0_Reserved_4_3_WIDTH 2 |
| 4258 | #define D0F0xE4_CORE_00B0_Reserved_4_3_MASK 0x18 |
| 4259 | #define D0F0xE4_CORE_00B0_StrapF0AerEn_OFFSET 5 |
| 4260 | #define D0F0xE4_CORE_00B0_StrapF0AerEn_WIDTH 1 |
| 4261 | #define D0F0xE4_CORE_00B0_StrapF0AerEn_MASK 0x20 |
| 4262 | #define D0F0xE4_CORE_00B0_Reserved_31_6_OFFSET 6 |
| 4263 | #define D0F0xE4_CORE_00B0_Reserved_31_6_WIDTH 26 |
| 4264 | #define D0F0xE4_CORE_00B0_Reserved_31_6_MASK 0xffffffc0 |
| 4265 | |
| 4266 | /// D0F0xE4_CORE_00B0 |
| 4267 | typedef union { |
| 4268 | struct { ///< |
| 4269 | UINT32 Reserved_1_0:2 ; ///< |
| 4270 | UINT32 StrapF0MsiEn:1 ; ///< |
| 4271 | UINT32 Reserved_4_3:2 ; ///< |
| 4272 | UINT32 StrapF0AerEn:1 ; ///< |
| 4273 | UINT32 Reserved_31_6:26; ///< |
| 4274 | } Field; ///< |
| 4275 | UINT32 Value; ///< |
| 4276 | } D0F0xE4_CORE_00B0_STRUCT; |
| 4277 | |
| 4278 | |
| 4279 | // **** D0F0xE4_CORE_00C1 Register Definition **** |
| 4280 | // Address |
| 4281 | #define D0F0xE4_CORE_00C1_ADDRESS 0xc1 |
| 4282 | |
| 4283 | // Type |
| 4284 | #define D0F0xE4_CORE_00C1_TYPE TYPE_D0F0xE4 |
| 4285 | // Field Data |
| 4286 | #define D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_OFFSET 0 |
| 4287 | #define D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_WIDTH 1 |
| 4288 | #define D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_MASK 0x1 |
| 4289 | #define D0F0xE4_CORE_00C1_StrapGen2Compliance_OFFSET 1 |
| 4290 | #define D0F0xE4_CORE_00C1_StrapGen2Compliance_WIDTH 1 |
| 4291 | #define D0F0xE4_CORE_00C1_StrapGen2Compliance_MASK 0x2 |
| 4292 | #define D0F0xE4_CORE_00C1_Reserved_31_2_OFFSET 2 |
| 4293 | #define D0F0xE4_CORE_00C1_Reserved_31_2_WIDTH 30 |
| 4294 | #define D0F0xE4_CORE_00C1_Reserved_31_2_MASK 0xfffffffc |
| 4295 | |
| 4296 | /// D0F0xE4_CORE_00C1 |
| 4297 | typedef union { |
| 4298 | struct { ///< |
| 4299 | UINT32 StrapLinkBwNotificationCapEn:1 ; ///< |
| 4300 | UINT32 StrapGen2Compliance:1 ; ///< |
| 4301 | UINT32 Reserved_31_2:30; ///< |
| 4302 | } Field; ///< |
| 4303 | UINT32 Value; ///< |
| 4304 | } D0F0xE4_CORE_00C1_STRUCT; |
| 4305 | |
| 4306 | // **** D0F0xE4_PHY_0009 Register Definition **** |
| 4307 | // Address |
| 4308 | #define D0F0xE4_PHY_0009_ADDRESS 0x9 |
| 4309 | |
| 4310 | // Type |
| 4311 | #define D0F0xE4_PHY_0009_TYPE TYPE_D0F0xE4 |
| 4312 | // Field Data |
| 4313 | #define D0F0xE4_PHY_0009_Reserved_23_0_OFFSET 0 |
| 4314 | #define D0F0xE4_PHY_0009_Reserved_23_0_WIDTH 24 |
| 4315 | #define D0F0xE4_PHY_0009_Reserved_23_0_MASK 0xffffff |
| 4316 | #define D0F0xE4_PHY_0009_ClkOff_OFFSET 24 |
| 4317 | #define D0F0xE4_PHY_0009_ClkOff_WIDTH 1 |
| 4318 | #define D0F0xE4_PHY_0009_ClkOff_MASK 0x1000000 |
| 4319 | #define D0F0xE4_PHY_0009_DisplayStream_OFFSET 25 |
| 4320 | #define D0F0xE4_PHY_0009_DisplayStream_WIDTH 1 |
| 4321 | #define D0F0xE4_PHY_0009_DisplayStream_MASK 0x2000000 |
| 4322 | #define D0F0xE4_PHY_0009_Reserved_27_26_OFFSET 26 |
| 4323 | #define D0F0xE4_PHY_0009_Reserved_27_26_WIDTH 2 |
| 4324 | #define D0F0xE4_PHY_0009_Reserved_27_26_MASK 0xc000000 |
| 4325 | #define D0F0xE4_PHY_0009_CascadedPllSel_OFFSET 28 |
| 4326 | #define D0F0xE4_PHY_0009_CascadedPllSel_WIDTH 1 |
| 4327 | #define D0F0xE4_PHY_0009_CascadedPllSel_MASK 0x10000000 |
| 4328 | #define D0F0xE4_PHY_0009_Reserved_30_29_OFFSET 29 |
| 4329 | #define D0F0xE4_PHY_0009_Reserved_30_29_WIDTH 2 |
| 4330 | #define D0F0xE4_PHY_0009_Reserved_30_29_MASK 0x60000000 |
| 4331 | #define D0F0xE4_PHY_0009_PCIePllSel_OFFSET 31 |
| 4332 | #define D0F0xE4_PHY_0009_PCIePllSel_WIDTH 1 |
| 4333 | #define D0F0xE4_PHY_0009_PCIePllSel_MASK 0x80000000 |
| 4334 | |
| 4335 | /// D0F0xE4_PHY_0009 |
| 4336 | typedef union { |
| 4337 | struct { ///< |
| 4338 | UINT32 Reserved_23_0:24; ///< |
| 4339 | UINT32 ClkOff:1 ; ///< |
| 4340 | UINT32 DisplayStream:1 ; ///< |
| 4341 | UINT32 Reserved_27_26:2 ; ///< |
| 4342 | UINT32 CascadedPllSel:1 ; ///< |
| 4343 | UINT32 Reserved_30_29:2 ; ///< |
| 4344 | UINT32 PCIePllSel:1 ; ///< |
| 4345 | } Field; ///< |
| 4346 | UINT32 Value; ///< |
| 4347 | } D0F0xE4_PHY_0009_STRUCT; |
| 4348 | |
| 4349 | // **** D0F0xE4_PHY_000A Register Definition **** |
| 4350 | // Address |
| 4351 | #define D0F0xE4_PHY_000A_ADDRESS 0xa |
| 4352 | |
| 4353 | // Type |
| 4354 | #define D0F0xE4_PHY_000A_TYPE TYPE_D0F0xE4 |
| 4355 | // Field Data |
| 4356 | #define D0F0xE4_PHY_000A_Reserved_23_0_OFFSET 0 |
| 4357 | #define D0F0xE4_PHY_000A_Reserved_23_0_WIDTH 24 |
| 4358 | #define D0F0xE4_PHY_000A_Reserved_23_0_MASK 0xffffff |
| 4359 | #define D0F0xE4_PHY_000A_ClkOff_OFFSET 24 |
| 4360 | #define D0F0xE4_PHY_000A_ClkOff_WIDTH 1 |
| 4361 | #define D0F0xE4_PHY_000A_ClkOff_MASK 0x1000000 |
| 4362 | #define D0F0xE4_PHY_000A_DisplayStream_OFFSET 25 |
| 4363 | #define D0F0xE4_PHY_000A_DisplayStream_WIDTH 1 |
| 4364 | #define D0F0xE4_PHY_000A_DisplayStream_MASK 0x2000000 |
| 4365 | #define D0F0xE4_PHY_000A_Reserved_27_26_OFFSET 26 |
| 4366 | #define D0F0xE4_PHY_000A_Reserved_27_26_WIDTH 2 |
| 4367 | #define D0F0xE4_PHY_000A_Reserved_27_26_MASK 0xc000000 |
| 4368 | #define D0F0xE4_PHY_000A_CascadedPllSel_OFFSET 28 |
| 4369 | #define D0F0xE4_PHY_000A_CascadedPllSel_WIDTH 1 |
| 4370 | #define D0F0xE4_PHY_000A_CascadedPllSel_MASK 0x10000000 |
| 4371 | #define D0F0xE4_PHY_000A_Reserved_30_29_OFFSET 29 |
| 4372 | #define D0F0xE4_PHY_000A_Reserved_30_29_WIDTH 2 |
| 4373 | #define D0F0xE4_PHY_000A_Reserved_30_29_MASK 0x60000000 |
| 4374 | #define D0F0xE4_PHY_000A_PCIePllSel_OFFSET 31 |
| 4375 | #define D0F0xE4_PHY_000A_PCIePllSel_WIDTH 1 |
| 4376 | #define D0F0xE4_PHY_000A_PCIePllSel_MASK 0x80000000 |
| 4377 | |
| 4378 | /// D0F0xE4_PHY_000A |
| 4379 | typedef union { |
| 4380 | struct { ///< |
| 4381 | UINT32 Reserved_23_0:24; ///< |
| 4382 | UINT32 ClkOff:1 ; ///< |
| 4383 | UINT32 DisplayStream:1 ; ///< |
| 4384 | UINT32 Reserved_27_26:2 ; ///< |
| 4385 | UINT32 CascadedPllSel:1 ; ///< |
| 4386 | UINT32 Reserved_30_29:2 ; ///< |
| 4387 | UINT32 PCIePllSel:1 ; ///< |
| 4388 | } Field; ///< |
| 4389 | UINT32 Value; ///< |
| 4390 | } D0F0xE4_PHY_000A_STRUCT; |
| 4391 | |
| 4392 | // **** D0F0xE4_PHY_000B Register Definition **** |
| 4393 | // Address |
| 4394 | #define D0F0xE4_PHY_000B_ADDRESS 0xb |
| 4395 | |
| 4396 | // Type |
| 4397 | #define D0F0xE4_PHY_000B_TYPE TYPE_D0F0xE4 |
| 4398 | // Field Data |
| 4399 | #define D0F0xE4_PHY_000B_TxPwrSbiEn_OFFSET 0 |
| 4400 | #define D0F0xE4_PHY_000B_TxPwrSbiEn_WIDTH 1 |
| 4401 | #define D0F0xE4_PHY_000B_TxPwrSbiEn_MASK 0x1 |
| 4402 | #define D0F0xE4_PHY_000B_RxPwrSbiEn_OFFSET 1 |
| 4403 | #define D0F0xE4_PHY_000B_RxPwrSbiEn_WIDTH 1 |
| 4404 | #define D0F0xE4_PHY_000B_RxPwrSbiEn_MASK 0x2 |
| 4405 | #define D0F0xE4_PHY_000B_PcieModeSbiEn_OFFSET 2 |
| 4406 | #define D0F0xE4_PHY_000B_PcieModeSbiEn_WIDTH 1 |
| 4407 | #define D0F0xE4_PHY_000B_PcieModeSbiEn_MASK 0x4 |
| 4408 | #define D0F0xE4_PHY_000B_FreqDivSbiEn_OFFSET 3 |
| 4409 | #define D0F0xE4_PHY_000B_FreqDivSbiEn_WIDTH 1 |
| 4410 | #define D0F0xE4_PHY_000B_FreqDivSbiEn_MASK 0x8 |
| 4411 | #define D0F0xE4_PHY_000B_DllLockSbiEn_OFFSET 4 |
| 4412 | #define D0F0xE4_PHY_000B_DllLockSbiEn_WIDTH 1 |
| 4413 | #define D0F0xE4_PHY_000B_DllLockSbiEn_MASK 0x10 |
| 4414 | #define D0F0xE4_PHY_000B_OffsetCancelSbiEn_OFFSET 5 |
| 4415 | #define D0F0xE4_PHY_000B_OffsetCancelSbiEn_WIDTH 1 |
| 4416 | #define D0F0xE4_PHY_000B_OffsetCancelSbiEn_MASK 0x20 |
| 4417 | #define D0F0xE4_PHY_000B_SkipBitSbiEn_OFFSET 6 |
| 4418 | #define D0F0xE4_PHY_000B_SkipBitSbiEn_WIDTH 1 |
| 4419 | #define D0F0xE4_PHY_000B_SkipBitSbiEn_MASK 0x40 |
| 4420 | #define D0F0xE4_PHY_000B_IncoherentClkSbiEn_OFFSET 7 |
| 4421 | #define D0F0xE4_PHY_000B_IncoherentClkSbiEn_WIDTH 1 |
| 4422 | #define D0F0xE4_PHY_000B_IncoherentClkSbiEn_MASK 0x80 |
| 4423 | #define D0F0xE4_PHY_000B_EiDetSbiEn_OFFSET 8 |
| 4424 | #define D0F0xE4_PHY_000B_EiDetSbiEn_WIDTH 1 |
| 4425 | #define D0F0xE4_PHY_000B_EiDetSbiEn_MASK 0x100 |
| 4426 | #define D0F0xE4_PHY_000B_Reserved_13_9_OFFSET 9 |
| 4427 | #define D0F0xE4_PHY_000B_Reserved_13_9_WIDTH 5 |
| 4428 | #define D0F0xE4_PHY_000B_Reserved_13_9_MASK 0x3e00 |
| 4429 | #define D0F0xE4_PHY_000B_MargPktSbiEn_OFFSET 14 |
| 4430 | #define D0F0xE4_PHY_000B_MargPktSbiEn_WIDTH 1 |
| 4431 | #define D0F0xE4_PHY_000B_MargPktSbiEn_MASK 0x4000 |
| 4432 | #define D0F0xE4_PHY_000B_PllCmpPktSbiEn_OFFSET 15 |
| 4433 | #define D0F0xE4_PHY_000B_PllCmpPktSbiEn_WIDTH 1 |
| 4434 | #define D0F0xE4_PHY_000B_PllCmpPktSbiEn_MASK 0x8000 |
| 4435 | #define D0F0xE4_PHY_000B_Reserved_31_16_OFFSET 16 |
| 4436 | #define D0F0xE4_PHY_000B_Reserved_31_16_WIDTH 16 |
| 4437 | #define D0F0xE4_PHY_000B_Reserved_31_16_MASK 0xffff0000 |
| 4438 | |
| 4439 | /// D0F0xE4_PHY_000B |
| 4440 | typedef union { |
| 4441 | struct { ///< |
| 4442 | UINT32 TxPwrSbiEn:1 ; ///< |
| 4443 | UINT32 RxPwrSbiEn:1 ; ///< |
| 4444 | UINT32 PcieModeSbiEn:1 ; ///< |
| 4445 | UINT32 FreqDivSbiEn:1 ; ///< |
| 4446 | UINT32 DllLockSbiEn:1 ; ///< |
| 4447 | UINT32 OffsetCancelSbiEn:1 ; ///< |
| 4448 | UINT32 SkipBitSbiEn:1 ; ///< |
| 4449 | UINT32 IncoherentClkSbiEn:1 ; ///< |
| 4450 | UINT32 EiDetSbiEn:1 ; ///< |
| 4451 | UINT32 Reserved_13_9:5 ; ///< |
| 4452 | UINT32 MargPktSbiEn:1 ; ///< |
| 4453 | UINT32 PllCmpPktSbiEn:1 ; ///< |
| 4454 | UINT32 Reserved_31_16:16; ///< |
| 4455 | } Field; ///< |
| 4456 | UINT32 Value; ///< |
| 4457 | } D0F0xE4_PHY_000B_STRUCT; |
| 4458 | |
| 4459 | // **** D0F0xE4_PHY_2000 Register Definition **** |
| 4460 | // Address |
| 4461 | #define D0F0xE4_PHY_2000_ADDRESS 0x2000 |
| 4462 | |
| 4463 | // Type |
| 4464 | #define D0F0xE4_PHY_2000_TYPE TYPE_D0F0xE4 |
| 4465 | // Field Data |
| 4466 | #define D0F0xE4_PHY_2000_PllPowerDownEn_OFFSET 0 |
| 4467 | #define D0F0xE4_PHY_2000_PllPowerDownEn_WIDTH 3 |
| 4468 | #define D0F0xE4_PHY_2000_PllPowerDownEn_MASK 0x7 |
| 4469 | #define D0F0xE4_PHY_2000_PllAutoPwrDownDis_OFFSET 3 |
| 4470 | #define D0F0xE4_PHY_2000_PllAutoPwrDownDis_WIDTH 1 |
| 4471 | #define D0F0xE4_PHY_2000_PllAutoPwrDownDis_MASK 0x8 |
| 4472 | #define D0F0xE4_PHY_2000_Reserved_31_4_OFFSET 4 |
| 4473 | #define D0F0xE4_PHY_2000_Reserved_31_4_WIDTH 28 |
| 4474 | #define D0F0xE4_PHY_2000_Reserved_31_4_MASK 0xfffffff0 |
| 4475 | |
| 4476 | /// D0F0xE4_PHY_2000 |
| 4477 | typedef union { |
| 4478 | struct { ///< |
| 4479 | UINT32 PllPowerDownEn:3 ; ///< |
| 4480 | UINT32 PllAutoPwrDownDis:1 ; ///< |
| 4481 | UINT32 Reserved_31_4:28; ///< |
| 4482 | } Field; ///< |
| 4483 | UINT32 Value; ///< |
| 4484 | } D0F0xE4_PHY_2000_STRUCT; |
| 4485 | |
| 4486 | |
| 4487 | // **** D0F0xE4_PHY_2005 Register Definition **** |
| 4488 | // Address |
| 4489 | #define D0F0xE4_PHY_2005_ADDRESS 0x2005 |
| 4490 | |
| 4491 | // Type |
| 4492 | #define D0F0xE4_PHY_2005_TYPE TYPE_D0F0xE4 |
| 4493 | // Field Data |
| 4494 | #define D0F0xE4_PHY_2005_PllClkFreq_OFFSET 0 |
| 4495 | #define D0F0xE4_PHY_2005_PllClkFreq_WIDTH 4 |
| 4496 | #define D0F0xE4_PHY_2005_PllClkFreq_MASK 0xf |
| 4497 | #define D0F0xE4_PHY_2005_Reserved_8_4_OFFSET 4 |
| 4498 | #define D0F0xE4_PHY_2005_Reserved_8_4_WIDTH 5 |
| 4499 | #define D0F0xE4_PHY_2005_Reserved_8_4_MASK 0x1f0 |
| 4500 | #define D0F0xE4_PHY_2005_PllClkFreqExt_OFFSET 9 |
| 4501 | #define D0F0xE4_PHY_2005_PllClkFreqExt_WIDTH 2 |
| 4502 | #define D0F0xE4_PHY_2005_PllClkFreqExt_MASK 0x600 |
| 4503 | #define D0F0xE4_PHY_2005_Reserved_12_11_OFFSET 11 |
| 4504 | #define D0F0xE4_PHY_2005_Reserved_12_11_WIDTH 2 |
| 4505 | #define D0F0xE4_PHY_2005_Reserved_12_11_MASK 0x1800 |
| 4506 | #define D0F0xE4_PHY_2005_PllMode_OFFSET 13 |
| 4507 | #define D0F0xE4_PHY_2005_PllMode_WIDTH 2 |
| 4508 | #define D0F0xE4_PHY_2005_PllMode_MASK 0x6000 |
| 4509 | #define D0F0xE4_PHY_2005_Reserved_31_15_OFFSET 15 |
| 4510 | #define D0F0xE4_PHY_2005_Reserved_31_15_WIDTH 17 |
| 4511 | #define D0F0xE4_PHY_2005_Reserved_31_15_MASK 0xffff8000 |
| 4512 | |
| 4513 | /// D0F0xE4_PHY_2005 |
| 4514 | typedef union { |
| 4515 | struct { ///< |
| 4516 | UINT32 PllClkFreq:4 ; ///< |
| 4517 | UINT32 Reserved_8_4:5 ; ///< |
| 4518 | UINT32 PllClkFreqExt:2 ; ///< |
| 4519 | UINT32 Reserved_12_11:2 ; ///< |
| 4520 | UINT32 PllMode:2 ; ///< |
| 4521 | UINT32 Reserved_31_15:17; ///< |
| 4522 | } Field; ///< |
| 4523 | UINT32 Value; ///< |
| 4524 | } D0F0xE4_PHY_2005_STRUCT; |
| 4525 | |
| 4526 | // **** D0F0xE4_PHY_2008 Register Definition **** |
| 4527 | // Address |
| 4528 | #define D0F0xE4_PHY_2008_ADDRESS 0x2008 |
| 4529 | |
| 4530 | // Type |
| 4531 | #define D0F0xE4_PHY_2008_TYPE TYPE_D0F0xE4 |
| 4532 | // Field Data |
| 4533 | #define D0F0xE4_PHY_2008_PllControlUpdate_OFFSET 0 |
| 4534 | #define D0F0xE4_PHY_2008_PllControlUpdate_WIDTH 1 |
| 4535 | #define D0F0xE4_PHY_2008_PllControlUpdate_MASK 0x1 |
| 4536 | #define D0F0xE4_PHY_2008_Reserved_22_1_OFFSET 1 |
| 4537 | #define D0F0xE4_PHY_2008_Reserved_22_1_WIDTH 22 |
| 4538 | #define D0F0xE4_PHY_2008_Reserved_22_1_MASK 0x7ffffe |
| 4539 | #define D0F0xE4_PHY_2008_MeasCycCntVal_2_0__OFFSET 23 |
| 4540 | #define D0F0xE4_PHY_2008_MeasCycCntVal_2_0__WIDTH 3 |
| 4541 | #define D0F0xE4_PHY_2008_MeasCycCntVal_2_0__MASK 0x3800000 |
| 4542 | #define D0F0xE4_PHY_2008_Reserved_28_26_OFFSET 26 |
| 4543 | #define D0F0xE4_PHY_2008_Reserved_28_26_WIDTH 3 |
| 4544 | #define D0F0xE4_PHY_2008_Reserved_28_26_MASK 0x1c000000 |
| 4545 | #define D0F0xE4_PHY_2008_VdDetectEn_OFFSET 29 |
| 4546 | #define D0F0xE4_PHY_2008_VdDetectEn_WIDTH 1 |
| 4547 | #define D0F0xE4_PHY_2008_VdDetectEn_MASK 0x20000000 |
| 4548 | #define D0F0xE4_PHY_2008_Reserved_31_30_OFFSET 30 |
| 4549 | #define D0F0xE4_PHY_2008_Reserved_31_30_WIDTH 2 |
| 4550 | #define D0F0xE4_PHY_2008_Reserved_31_30_MASK 0xc0000000 |
| 4551 | |
| 4552 | /// D0F0xE4_PHY_2008 |
| 4553 | typedef union { |
| 4554 | struct { ///< |
| 4555 | UINT32 PllControlUpdate:1 ; ///< |
| 4556 | UINT32 Reserved_22_1:22; ///< |
| 4557 | UINT32 MeasCycCntVal_2_0_:3 ; ///< |
| 4558 | UINT32 Reserved_28_26:3 ; ///< |
| 4559 | UINT32 VdDetectEn:1 ; ///< |
| 4560 | UINT32 Reserved_31_30:2 ; ///< |
| 4561 | } Field; ///< |
| 4562 | UINT32 Value; ///< |
| 4563 | } D0F0xE4_PHY_2008_STRUCT; |
| 4564 | |
| 4565 | // **** D0F0xE4_PHY_4001 Register Definition **** |
| 4566 | // Address |
| 4567 | #define D0F0xE4_PHY_4001_ADDRESS 0x4001 |
| 4568 | |
| 4569 | // Type |
| 4570 | #define D0F0xE4_PHY_4001_TYPE TYPE_D0F0xE4 |
| 4571 | // Field Data |
| 4572 | #define D0F0xE4_PHY_4001_Reserved_14_0_OFFSET 0 |
| 4573 | #define D0F0xE4_PHY_4001_Reserved_14_0_WIDTH 15 |
| 4574 | #define D0F0xE4_PHY_4001_Reserved_14_0_MASK 0x7fff |
| 4575 | #define D0F0xE4_PHY_4001_ForceDccRecalc_OFFSET 15 |
| 4576 | #define D0F0xE4_PHY_4001_ForceDccRecalc_WIDTH 1 |
| 4577 | #define D0F0xE4_PHY_4001_ForceDccRecalc_MASK 0x8000 |
| 4578 | #define D0F0xE4_PHY_4001_Reserved_31_16_OFFSET 16 |
| 4579 | #define D0F0xE4_PHY_4001_Reserved_31_16_WIDTH 16 |
| 4580 | #define D0F0xE4_PHY_4001_Reserved_31_16_MASK 0xffff0000 |
| 4581 | |
| 4582 | /// D0F0xE4_PHY_4001 |
| 4583 | typedef union { |
| 4584 | struct { ///< |
| 4585 | UINT32 Reserved_14_0:15; ///< |
| 4586 | UINT32 ForceDccRecalc:1 ; ///< |
| 4587 | UINT32 Reserved_31_16:16; ///< |
| 4588 | } Field; ///< |
| 4589 | UINT32 Value; ///< |
| 4590 | } D0F0xE4_PHY_4001_STRUCT; |
| 4591 | |
| 4592 | // **** D0F0xE4_PHY_4002 Register Definition **** |
| 4593 | // Address |
| 4594 | #define D0F0xE4_PHY_4002_ADDRESS 0x4002 |
| 4595 | |
| 4596 | // Type |
| 4597 | #define D0F0xE4_PHY_4002_TYPE TYPE_D0F0xE4 |
| 4598 | // Field Data |
| 4599 | #define D0F0xE4_PHY_4002_Reserved_2_0_OFFSET 0 |
| 4600 | #define D0F0xE4_PHY_4002_Reserved_2_0_WIDTH 3 |
| 4601 | #define D0F0xE4_PHY_4002_Reserved_2_0_MASK 0x7 |
| 4602 | #define D0F0xE4_PHY_4002_SamClkPiOffsetSign_OFFSET 3 |
| 4603 | #define D0F0xE4_PHY_4002_SamClkPiOffsetSign_WIDTH 1 |
| 4604 | #define D0F0xE4_PHY_4002_SamClkPiOffsetSign_MASK 0x8 |
| 4605 | #define D0F0xE4_PHY_4002_SamClkPiOffset_OFFSET 4 |
| 4606 | #define D0F0xE4_PHY_4002_SamClkPiOffset_WIDTH 3 |
| 4607 | #define D0F0xE4_PHY_4002_SamClkPiOffset_MASK 0x70 |
| 4608 | #define D0F0xE4_PHY_4002_SamClkPiOffsetEn_OFFSET 7 |
| 4609 | #define D0F0xE4_PHY_4002_SamClkPiOffsetEn_WIDTH 1 |
| 4610 | #define D0F0xE4_PHY_4002_SamClkPiOffsetEn_MASK 0x80 |
| 4611 | #define D0F0xE4_PHY_4002_Reserved_13_8_OFFSET 8 |
| 4612 | #define D0F0xE4_PHY_4002_Reserved_13_8_WIDTH 6 |
| 4613 | #define D0F0xE4_PHY_4002_Reserved_13_8_MASK 0x3f00 |
| 4614 | #define D0F0xE4_PHY_4002_LfcMin_OFFSET 14 |
| 4615 | #define D0F0xE4_PHY_4002_LfcMin_WIDTH 8 |
| 4616 | #define D0F0xE4_PHY_4002_LfcMin_MASK 0x3fc000 |
| 4617 | #define D0F0xE4_PHY_4002_LfcMax_OFFSET 22 |
| 4618 | #define D0F0xE4_PHY_4002_LfcMax_WIDTH 8 |
| 4619 | #define D0F0xE4_PHY_4002_LfcMax_MASK 0x3fc00000 |
| 4620 | #define D0F0xE4_PHY_4002_Reserved_31_30_OFFSET 30 |
| 4621 | #define D0F0xE4_PHY_4002_Reserved_31_30_WIDTH 2 |
| 4622 | #define D0F0xE4_PHY_4002_Reserved_31_30_MASK 0xc0000000 |
| 4623 | |
| 4624 | /// D0F0xE4_PHY_4002 |
| 4625 | typedef union { |
| 4626 | struct { ///< |
| 4627 | UINT32 Reserved_2_0:3 ; ///< |
| 4628 | UINT32 SamClkPiOffsetSign:1 ; ///< |
| 4629 | UINT32 SamClkPiOffset:3 ; ///< |
| 4630 | UINT32 SamClkPiOffsetEn:1 ; ///< |
| 4631 | UINT32 Reserved_13_8:6 ; ///< |
| 4632 | UINT32 LfcMin:8 ; ///< |
| 4633 | UINT32 LfcMax:8 ; ///< |
| 4634 | UINT32 Reserved_31_30:2 ; ///< |
| 4635 | } Field; ///< |
| 4636 | UINT32 Value; ///< |
| 4637 | } D0F0xE4_PHY_4002_STRUCT; |
| 4638 | |
| 4639 | // **** D0F0xE4_PHY_4005 Register Definition **** |
| 4640 | // Address |
| 4641 | #define D0F0xE4_PHY_4005_ADDRESS 0x4005 |
| 4642 | |
| 4643 | // Type |
| 4644 | #define D0F0xE4_PHY_4005_TYPE TYPE_D0F0xE4 |
| 4645 | // Field Data |
| 4646 | #define D0F0xE4_PHY_4005_Reserved_8_0_OFFSET 0 |
| 4647 | #define D0F0xE4_PHY_4005_Reserved_8_0_WIDTH 9 |
| 4648 | #define D0F0xE4_PHY_4005_Reserved_8_0_MASK 0x1ff |
| 4649 | #define D0F0xE4_PHY_4005_JitterInjHold_OFFSET 9 |
| 4650 | #define D0F0xE4_PHY_4005_JitterInjHold_WIDTH 1 |
| 4651 | #define D0F0xE4_PHY_4005_JitterInjHold_MASK 0x200 |
| 4652 | #define D0F0xE4_PHY_4005_JitterInjOffCnt_OFFSET 10 |
| 4653 | #define D0F0xE4_PHY_4005_JitterInjOffCnt_WIDTH 6 |
| 4654 | #define D0F0xE4_PHY_4005_JitterInjOffCnt_MASK 0xfc00 |
| 4655 | #define D0F0xE4_PHY_4005_Reserved_22_16_OFFSET 16 |
| 4656 | #define D0F0xE4_PHY_4005_Reserved_22_16_WIDTH 7 |
| 4657 | #define D0F0xE4_PHY_4005_Reserved_22_16_MASK 0x7f0000 |
| 4658 | #define D0F0xE4_PHY_4005_JitterInjOnCnt_OFFSET 23 |
| 4659 | #define D0F0xE4_PHY_4005_JitterInjOnCnt_WIDTH 6 |
| 4660 | #define D0F0xE4_PHY_4005_JitterInjOnCnt_MASK 0x1f800000 |
| 4661 | #define D0F0xE4_PHY_4005_JitterInjDir_OFFSET 29 |
| 4662 | #define D0F0xE4_PHY_4005_JitterInjDir_WIDTH 1 |
| 4663 | #define D0F0xE4_PHY_4005_JitterInjDir_MASK 0x20000000 |
| 4664 | #define D0F0xE4_PHY_4005_JitterInjEn_OFFSET 30 |
| 4665 | #define D0F0xE4_PHY_4005_JitterInjEn_WIDTH 1 |
| 4666 | #define D0F0xE4_PHY_4005_JitterInjEn_MASK 0x40000000 |
| 4667 | #define D0F0xE4_PHY_4005_Reserved_31_31_OFFSET 31 |
| 4668 | #define D0F0xE4_PHY_4005_Reserved_31_31_WIDTH 1 |
| 4669 | #define D0F0xE4_PHY_4005_Reserved_31_31_MASK 0x80000000 |
| 4670 | |
| 4671 | /// D0F0xE4_PHY_4005 |
| 4672 | typedef union { |
| 4673 | struct { ///< |
| 4674 | UINT32 Reserved_8_0:9 ; ///< |
| 4675 | UINT32 JitterInjHold:1 ; ///< |
| 4676 | UINT32 JitterInjOffCnt:6 ; ///< |
| 4677 | UINT32 Reserved_22_16:7 ; ///< |
| 4678 | UINT32 JitterInjOnCnt:6 ; ///< |
| 4679 | UINT32 JitterInjDir:1 ; ///< |
| 4680 | UINT32 JitterInjEn:1 ; ///< |
| 4681 | UINT32 Reserved_31_31:1 ; ///< |
| 4682 | } Field; ///< |
| 4683 | UINT32 Value; ///< |
| 4684 | } D0F0xE4_PHY_4005_STRUCT; |
| 4685 | |
| 4686 | // **** D0F0xE4_PHY_4006 Register Definition **** |
| 4687 | // Address |
| 4688 | #define D0F0xE4_PHY_4006_ADDRESS 0x4006 |
| 4689 | |
| 4690 | // Type |
| 4691 | #define D0F0xE4_PHY_4006_TYPE TYPE_D0F0xE4 |
| 4692 | // Field Data |
| 4693 | #define D0F0xE4_PHY_4006_Reserved_4_0_OFFSET 0 |
| 4694 | #define D0F0xE4_PHY_4006_Reserved_4_0_WIDTH 5 |
| 4695 | #define D0F0xE4_PHY_4006_Reserved_4_0_MASK 0x1f |
| 4696 | #define D0F0xE4_PHY_4006_DfeVoltage_OFFSET 5 |
| 4697 | #define D0F0xE4_PHY_4006_DfeVoltage_WIDTH 2 |
| 4698 | #define D0F0xE4_PHY_4006_DfeVoltage_MASK 0x60 |
| 4699 | #define D0F0xE4_PHY_4006_DfeEn_OFFSET 7 |
| 4700 | #define D0F0xE4_PHY_4006_DfeEn_WIDTH 1 |
| 4701 | #define D0F0xE4_PHY_4006_DfeEn_MASK 0x80 |
| 4702 | #define D0F0xE4_PHY_4006_Reserved_31_8_OFFSET 8 |
| 4703 | #define D0F0xE4_PHY_4006_Reserved_31_8_WIDTH 24 |
| 4704 | #define D0F0xE4_PHY_4006_Reserved_31_8_MASK 0xffffff00 |
| 4705 | |
| 4706 | /// D0F0xE4_PHY_4006 |
| 4707 | typedef union { |
| 4708 | struct { ///< |
| 4709 | UINT32 Reserved_4_0:5 ; ///< |
| 4710 | UINT32 DfeVoltage:2 ; ///< |
| 4711 | UINT32 DfeEn:1 ; ///< |
| 4712 | UINT32 Reserved_31_8:24; ///< |
| 4713 | } Field; ///< |
| 4714 | UINT32 Value; ///< |
| 4715 | } D0F0xE4_PHY_4006_STRUCT; |
| 4716 | |
| 4717 | // **** D0F0xE4_PHY_400A Register Definition **** |
| 4718 | // Address |
| 4719 | #define D0F0xE4_PHY_400A_ADDRESS 0x400a |
| 4720 | |
| 4721 | // Type |
| 4722 | #define D0F0xE4_PHY_400A_TYPE TYPE_D0F0xE4 |
| 4723 | // Field Data |
| 4724 | #define D0F0xE4_PHY_400A_EnCoreLoopFirst_OFFSET 0 |
| 4725 | #define D0F0xE4_PHY_400A_EnCoreLoopFirst_WIDTH 1 |
| 4726 | #define D0F0xE4_PHY_400A_EnCoreLoopFirst_MASK 0x1 |
| 4727 | #define D0F0xE4_PHY_400A_Reserved_3_1_OFFSET 1 |
| 4728 | #define D0F0xE4_PHY_400A_Reserved_3_1_WIDTH 3 |
| 4729 | #define D0F0xE4_PHY_400A_Reserved_3_1_MASK 0xe |
| 4730 | #define D0F0xE4_PHY_400A_LockDetOnLs2Exit_OFFSET 4 |
| 4731 | #define D0F0xE4_PHY_400A_LockDetOnLs2Exit_WIDTH 1 |
| 4732 | #define D0F0xE4_PHY_400A_LockDetOnLs2Exit_MASK 0x10 |
| 4733 | #define D0F0xE4_PHY_400A_Reserved_6_5_OFFSET 5 |
| 4734 | #define D0F0xE4_PHY_400A_Reserved_6_5_WIDTH 2 |
| 4735 | #define D0F0xE4_PHY_400A_Reserved_6_5_MASK 0x60 |
| 4736 | #define D0F0xE4_PHY_400A_BiasDisInLs2_OFFSET 7 |
| 4737 | #define D0F0xE4_PHY_400A_BiasDisInLs2_WIDTH 1 |
| 4738 | #define D0F0xE4_PHY_400A_BiasDisInLs2_MASK 0x80 |
| 4739 | #define D0F0xE4_PHY_400A_Reserved_12_8_OFFSET 8 |
| 4740 | #define D0F0xE4_PHY_400A_Reserved_12_8_WIDTH 5 |
| 4741 | #define D0F0xE4_PHY_400A_Reserved_12_8_MASK 0x1f00 |
| 4742 | #define D0F0xE4_PHY_400A_AnalogWaitTime_OFFSET 13 |
| 4743 | #define D0F0xE4_PHY_400A_AnalogWaitTime_WIDTH 2 |
| 4744 | #define D0F0xE4_PHY_400A_AnalogWaitTime_MASK 0x6000 |
| 4745 | #define D0F0xE4_PHY_400A_Reserved_16_15_OFFSET 15 |
| 4746 | #define D0F0xE4_PHY_400A_Reserved_16_15_WIDTH 2 |
| 4747 | #define D0F0xE4_PHY_400A_Reserved_16_15_MASK 0x18000 |
| 4748 | #define D0F0xE4_PHY_400A_DllLockFastModeEn_OFFSET 17 |
| 4749 | #define D0F0xE4_PHY_400A_DllLockFastModeEn_WIDTH 1 |
| 4750 | #define D0F0xE4_PHY_400A_DllLockFastModeEn_MASK 0x20000 |
| 4751 | #define D0F0xE4_PHY_400A_Reserved_28_18_OFFSET 18 |
| 4752 | #define D0F0xE4_PHY_400A_Reserved_28_18_WIDTH 11 |
| 4753 | #define D0F0xE4_PHY_400A_Reserved_28_18_MASK 0x1ffc0000 |
| 4754 | #define D0F0xE4_PHY_400A_Ls2ExitTime_OFFSET 29 |
| 4755 | #define D0F0xE4_PHY_400A_Ls2ExitTime_WIDTH 3 |
| 4756 | #define D0F0xE4_PHY_400A_Ls2ExitTime_MASK 0xe0000000 |
| 4757 | |
| 4758 | /// D0F0xE4_PHY_400A |
| 4759 | typedef union { |
| 4760 | struct { ///< |
| 4761 | UINT32 EnCoreLoopFirst:1 ; ///< |
| 4762 | UINT32 Reserved_3_1:3 ; ///< |
| 4763 | UINT32 LockDetOnLs2Exit:1 ; ///< |
| 4764 | UINT32 Reserved_6_5:2 ; ///< |
| 4765 | UINT32 BiasDisInLs2:1 ; ///< |
| 4766 | UINT32 Reserved_12_8:5 ; ///< |
| 4767 | UINT32 AnalogWaitTime:2 ; ///< |
| 4768 | UINT32 Reserved_16_15:2 ; ///< |
| 4769 | UINT32 DllLockFastModeEn:1 ; ///< |
| 4770 | UINT32 Reserved_28_18:11; ///< |
| 4771 | UINT32 Ls2ExitTime:3 ; ///< |
| 4772 | } Field; ///< |
| 4773 | UINT32 Value; ///< |
| 4774 | } D0F0xE4_PHY_400A_STRUCT; |
| 4775 | |
| 4776 | // **** D0F0xE4_PHY_6005 Register Definition **** |
| 4777 | // Address |
| 4778 | #define D0F0xE4_PHY_6005_ADDRESS 0x6005 |
| 4779 | |
| 4780 | // Type |
| 4781 | #define D0F0xE4_PHY_6005_TYPE TYPE_D0F0xE4 |
| 4782 | // Field Data |
| 4783 | #define D0F0xE4_PHY_6005_Reserved_28_0_OFFSET 0 |
| 4784 | #define D0F0xE4_PHY_6005_Reserved_28_0_WIDTH 29 |
| 4785 | #define D0F0xE4_PHY_6005_Reserved_28_0_MASK 0x1fffffff |
| 4786 | #define D0F0xE4_PHY_6005_IsOwnMstr_OFFSET 29 |
| 4787 | #define D0F0xE4_PHY_6005_IsOwnMstr_WIDTH 1 |
| 4788 | #define D0F0xE4_PHY_6005_IsOwnMstr_MASK 0x20000000 |
| 4789 | #define D0F0xE4_PHY_6005_Reserved_30_30_OFFSET 30 |
| 4790 | #define D0F0xE4_PHY_6005_Reserved_30_30_WIDTH 1 |
| 4791 | #define D0F0xE4_PHY_6005_Reserved_30_30_MASK 0x40000000 |
| 4792 | #define D0F0xE4_PHY_6005_GangedModeEn_OFFSET 31 |
| 4793 | #define D0F0xE4_PHY_6005_GangedModeEn_WIDTH 1 |
| 4794 | #define D0F0xE4_PHY_6005_GangedModeEn_MASK 0x80000000 |
| 4795 | |
| 4796 | /// D0F0xE4_PHY_6005 |
| 4797 | typedef union { |
| 4798 | struct { ///< |
| 4799 | UINT32 Reserved_28_0:29; ///< |
| 4800 | UINT32 IsOwnMstr:1 ; ///< |
| 4801 | UINT32 Reserved_30_30:1 ; ///< |
| 4802 | UINT32 GangedModeEn:1 ; ///< |
| 4803 | } Field; ///< |
| 4804 | UINT32 Value; ///< |
| 4805 | } D0F0xE4_PHY_6005_STRUCT; |
| 4806 | |
| 4807 | // **** D18F2x09C_x0000_0000 Register Definition **** |
| 4808 | // Address |
| 4809 | #define D18F2x09C_x0000_0000_ADDRESS 0x0 |
| 4810 | |
| 4811 | // Type |
| 4812 | #define D18F2x09C_x0000_0000_TYPE TYPE_D18F2x09C |
| 4813 | // Field Data |
| 4814 | #define D18F2x09C_x0000_0000_CkeDrvStren_OFFSET 0 |
| 4815 | #define D18F2x09C_x0000_0000_CkeDrvStren_WIDTH 3 |
| 4816 | #define D18F2x09C_x0000_0000_CkeDrvStren_MASK 0x7 |
| 4817 | #define D18F2x09C_x0000_0000_Reserved_3_3_OFFSET 3 |
| 4818 | #define D18F2x09C_x0000_0000_Reserved_3_3_WIDTH 1 |
| 4819 | #define D18F2x09C_x0000_0000_Reserved_3_3_MASK 0x8 |
| 4820 | #define D18F2x09C_x0000_0000_CsOdtDrvStren_OFFSET 4 |
| 4821 | #define D18F2x09C_x0000_0000_CsOdtDrvStren_WIDTH 3 |
| 4822 | #define D18F2x09C_x0000_0000_CsOdtDrvStren_MASK 0x70 |
| 4823 | #define D18F2x09C_x0000_0000_Reserved_7_7_OFFSET 7 |
| 4824 | #define D18F2x09C_x0000_0000_Reserved_7_7_WIDTH 1 |
| 4825 | #define D18F2x09C_x0000_0000_Reserved_7_7_MASK 0x80 |
| 4826 | #define D18F2x09C_x0000_0000_AddrCmdDrvStren_OFFSET 8 |
| 4827 | #define D18F2x09C_x0000_0000_AddrCmdDrvStren_WIDTH 3 |
| 4828 | #define D18F2x09C_x0000_0000_AddrCmdDrvStren_MASK 0x700 |
| 4829 | #define D18F2x09C_x0000_0000_Reserved_11_11_OFFSET 11 |
| 4830 | #define D18F2x09C_x0000_0000_Reserved_11_11_WIDTH 1 |
| 4831 | #define D18F2x09C_x0000_0000_Reserved_11_11_MASK 0x800 |
| 4832 | #define D18F2x09C_x0000_0000_ClkDrvStren_OFFSET 12 |
| 4833 | #define D18F2x09C_x0000_0000_ClkDrvStren_WIDTH 3 |
| 4834 | #define D18F2x09C_x0000_0000_ClkDrvStren_MASK 0x7000 |
| 4835 | #define D18F2x09C_x0000_0000_Reserved_15_15_OFFSET 15 |
| 4836 | #define D18F2x09C_x0000_0000_Reserved_15_15_WIDTH 1 |
| 4837 | #define D18F2x09C_x0000_0000_Reserved_15_15_MASK 0x8000 |
| 4838 | #define D18F2x09C_x0000_0000_DataDrvStren_OFFSET 16 |
| 4839 | #define D18F2x09C_x0000_0000_DataDrvStren_WIDTH 3 |
| 4840 | #define D18F2x09C_x0000_0000_DataDrvStren_MASK 0x70000 |
| 4841 | #define D18F2x09C_x0000_0000_Reserved_19_19_OFFSET 19 |
| 4842 | #define D18F2x09C_x0000_0000_Reserved_19_19_WIDTH 1 |
| 4843 | #define D18F2x09C_x0000_0000_Reserved_19_19_MASK 0x80000 |
| 4844 | #define D18F2x09C_x0000_0000_DqsDrvStren_OFFSET 20 |
| 4845 | #define D18F2x09C_x0000_0000_DqsDrvStren_WIDTH 3 |
| 4846 | #define D18F2x09C_x0000_0000_DqsDrvStren_MASK 0x700000 |
| 4847 | #define D18F2x09C_x0000_0000_Reserved_27_23_OFFSET 23 |
| 4848 | #define D18F2x09C_x0000_0000_Reserved_27_23_WIDTH 5 |
| 4849 | #define D18F2x09C_x0000_0000_Reserved_27_23_MASK 0xf800000 |
| 4850 | #define D18F2x09C_x0000_0000_ProcOdt_OFFSET 28 |
| 4851 | #define D18F2x09C_x0000_0000_ProcOdt_WIDTH 3 |
| 4852 | #define D18F2x09C_x0000_0000_ProcOdt_MASK 0x70000000 |
| 4853 | #define D18F2x09C_x0000_0000_Reserved_31_31_OFFSET 31 |
| 4854 | #define D18F2x09C_x0000_0000_Reserved_31_31_WIDTH 1 |
| 4855 | #define D18F2x09C_x0000_0000_Reserved_31_31_MASK 0x80000000 |
| 4856 | |
| 4857 | /// D18F2x09C_x0000_0000 |
| 4858 | typedef union { |
| 4859 | struct { ///< |
| 4860 | UINT32 CkeDrvStren:3 ; ///< |
| 4861 | UINT32 Reserved_3_3:1 ; ///< |
| 4862 | UINT32 CsOdtDrvStren:3 ; ///< |
| 4863 | UINT32 Reserved_7_7:1 ; ///< |
| 4864 | UINT32 AddrCmdDrvStren:3 ; ///< |
| 4865 | UINT32 Reserved_11_11:1 ; ///< |
| 4866 | UINT32 ClkDrvStren:3 ; ///< |
| 4867 | UINT32 Reserved_15_15:1 ; ///< |
| 4868 | UINT32 DataDrvStren:3 ; ///< |
| 4869 | UINT32 Reserved_19_19:1 ; ///< |
| 4870 | UINT32 DqsDrvStren:3 ; ///< |
| 4871 | UINT32 Reserved_27_23:5 ; ///< |
| 4872 | UINT32 ProcOdt:3 ; ///< |
| 4873 | UINT32 Reserved_31_31:1 ; ///< |
| 4874 | } Field; ///< |
| 4875 | UINT32 Value; ///< |
| 4876 | } D18F2x09C_x0000_0000_STRUCT; |
| 4877 | |
| 4878 | // **** D18F2x09C_x0000_0001 Register Definition **** |
| 4879 | // Address |
| 4880 | #define D18F2x09C_x0000_0001_ADDRESS 0x1 |
| 4881 | |
| 4882 | // Type |
| 4883 | #define D18F2x09C_x0000_0001_TYPE TYPE_D18F2x09C |
| 4884 | // Field Data |
| 4885 | #define D18F2x09C_x0000_0001_WrDatFineDly_Byte0_OFFSET 0 |
| 4886 | #define D18F2x09C_x0000_0001_WrDatFineDly_Byte0_WIDTH 5 |
| 4887 | #define D18F2x09C_x0000_0001_WrDatFineDly_Byte0_MASK 0x1f |
| 4888 | #define D18F2x09C_x0000_0001_WrDatGrossDly_Byte0_OFFSET 5 |
| 4889 | #define D18F2x09C_x0000_0001_WrDatGrossDly_Byte0_WIDTH 3 |
| 4890 | #define D18F2x09C_x0000_0001_WrDatGrossDly_Byte0_MASK 0xe0 |
| 4891 | #define D18F2x09C_x0000_0001_WrDatFineDly_Byte1_OFFSET 8 |
| 4892 | #define D18F2x09C_x0000_0001_WrDatFineDly_Byte1_WIDTH 5 |
| 4893 | #define D18F2x09C_x0000_0001_WrDatFineDly_Byte1_MASK 0x1f00 |
| 4894 | #define D18F2x09C_x0000_0001_WrDatGrossDly_Byte1_OFFSET 13 |
| 4895 | #define D18F2x09C_x0000_0001_WrDatGrossDly_Byte1_WIDTH 3 |
| 4896 | #define D18F2x09C_x0000_0001_WrDatGrossDly_Byte1_MASK 0xe000 |
| 4897 | #define D18F2x09C_x0000_0001_WrDatFineDly_Byte2_OFFSET 16 |
| 4898 | #define D18F2x09C_x0000_0001_WrDatFineDly_Byte2_WIDTH 5 |
| 4899 | #define D18F2x09C_x0000_0001_WrDatFineDly_Byte2_MASK 0x1f0000 |
| 4900 | #define D18F2x09C_x0000_0001_WrDatGrossDly_Byte2_OFFSET 21 |
| 4901 | #define D18F2x09C_x0000_0001_WrDatGrossDly_Byte2_WIDTH 3 |
| 4902 | #define D18F2x09C_x0000_0001_WrDatGrossDly_Byte2_MASK 0xe00000 |
| 4903 | #define D18F2x09C_x0000_0001_WrDatFineDly_Byte3_OFFSET 24 |
| 4904 | #define D18F2x09C_x0000_0001_WrDatFineDly_Byte3_WIDTH 5 |
| 4905 | #define D18F2x09C_x0000_0001_WrDatFineDly_Byte3_MASK 0x1f000000 |
| 4906 | #define D18F2x09C_x0000_0001_WrDatGrossDly_Byte3_OFFSET 29 |
| 4907 | #define D18F2x09C_x0000_0001_WrDatGrossDly_Byte3_WIDTH 3 |
| 4908 | #define D18F2x09C_x0000_0001_WrDatGrossDly_Byte3_MASK 0xe0000000 |
| 4909 | |
| 4910 | /// D18F2x09C_x0000_0001 |
| 4911 | typedef union { |
| 4912 | struct { ///< |
| 4913 | UINT32 WrDatFineDly_Byte0:5 ; ///< |
| 4914 | UINT32 WrDatGrossDly_Byte0:3 ; ///< |
| 4915 | UINT32 WrDatFineDly_Byte1:5 ; ///< |
| 4916 | UINT32 WrDatGrossDly_Byte1:3 ; ///< |
| 4917 | UINT32 WrDatFineDly_Byte2:5 ; ///< |
| 4918 | UINT32 WrDatGrossDly_Byte2:3 ; ///< |
| 4919 | UINT32 WrDatFineDly_Byte3:5 ; ///< |
| 4920 | UINT32 WrDatGrossDly_Byte3:3 ; ///< |
| 4921 | } Field; ///< |
| 4922 | UINT32 Value; ///< |
| 4923 | } D18F2x09C_x0000_0001_STRUCT; |
| 4924 | |
| 4925 | // **** D18F2x09C_x0000_0002 Register Definition **** |
| 4926 | // Address |
| 4927 | #define D18F2x09C_x0000_0002_ADDRESS 0x2 |
| 4928 | |
| 4929 | // Type |
| 4930 | #define D18F2x09C_x0000_0002_TYPE TYPE_D18F2x09C |
| 4931 | // Field Data |
| 4932 | #define D18F2x09C_x0000_0002_WrDatFineDly_Byte4_OFFSET 0 |
| 4933 | #define D18F2x09C_x0000_0002_WrDatFineDly_Byte4_WIDTH 5 |
| 4934 | #define D18F2x09C_x0000_0002_WrDatFineDly_Byte4_MASK 0x1f |
| 4935 | #define D18F2x09C_x0000_0002_WrDatGrossDly_Byte4_OFFSET 5 |
| 4936 | #define D18F2x09C_x0000_0002_WrDatGrossDly_Byte4_WIDTH 3 |
| 4937 | #define D18F2x09C_x0000_0002_WrDatGrossDly_Byte4_MASK 0xe0 |
| 4938 | #define D18F2x09C_x0000_0002_WrDatFineDly_Byte5_OFFSET 8 |
| 4939 | #define D18F2x09C_x0000_0002_WrDatFineDly_Byte5_WIDTH 5 |
| 4940 | #define D18F2x09C_x0000_0002_WrDatFineDly_Byte5_MASK 0x1f00 |
| 4941 | #define D18F2x09C_x0000_0002_WrDatGrossDly_Byte5_OFFSET 13 |
| 4942 | #define D18F2x09C_x0000_0002_WrDatGrossDly_Byte5_WIDTH 3 |
| 4943 | #define D18F2x09C_x0000_0002_WrDatGrossDly_Byte5_MASK 0xe000 |
| 4944 | #define D18F2x09C_x0000_0002_WrDatFineDly_Byte6_OFFSET 16 |
| 4945 | #define D18F2x09C_x0000_0002_WrDatFineDly_Byte6_WIDTH 5 |
| 4946 | #define D18F2x09C_x0000_0002_WrDatFineDly_Byte6_MASK 0x1f0000 |
| 4947 | #define D18F2x09C_x0000_0002_WrDatGrossDly_Byte6_OFFSET 21 |
| 4948 | #define D18F2x09C_x0000_0002_WrDatGrossDly_Byte6_WIDTH 3 |
| 4949 | #define D18F2x09C_x0000_0002_WrDatGrossDly_Byte6_MASK 0xe00000 |
| 4950 | #define D18F2x09C_x0000_0002_WrDatFineDly_Byte7_OFFSET 24 |
| 4951 | #define D18F2x09C_x0000_0002_WrDatFineDly_Byte7_WIDTH 5 |
| 4952 | #define D18F2x09C_x0000_0002_WrDatFineDly_Byte7_MASK 0x1f000000 |
| 4953 | #define D18F2x09C_x0000_0002_WrDatGrossDly_Byte7_OFFSET 29 |
| 4954 | #define D18F2x09C_x0000_0002_WrDatGrossDly_Byte7_WIDTH 3 |
| 4955 | #define D18F2x09C_x0000_0002_WrDatGrossDly_Byte7_MASK 0xe0000000 |
| 4956 | |
| 4957 | /// D18F2x09C_x0000_0002 |
| 4958 | typedef union { |
| 4959 | struct { ///< |
| 4960 | UINT32 WrDatFineDly_Byte4:5 ; ///< |
| 4961 | UINT32 WrDatGrossDly_Byte4:3 ; ///< |
| 4962 | UINT32 WrDatFineDly_Byte5:5 ; ///< |
| 4963 | UINT32 WrDatGrossDly_Byte5:3 ; ///< |
| 4964 | UINT32 WrDatFineDly_Byte6:5 ; ///< |
| 4965 | UINT32 WrDatGrossDly_Byte6:3 ; ///< |
| 4966 | UINT32 WrDatFineDly_Byte7:5 ; ///< |
| 4967 | UINT32 WrDatGrossDly_Byte7:3 ; ///< |
| 4968 | } Field; ///< |
| 4969 | UINT32 Value; ///< |
| 4970 | } D18F2x09C_x0000_0002_STRUCT; |
| 4971 | |
| 4972 | // **** D18F2x09C_x0000_0004 Register Definition **** |
| 4973 | // Address |
| 4974 | #define D18F2x09C_x0000_0004_ADDRESS 0x4 |
| 4975 | |
| 4976 | // Type |
| 4977 | #define D18F2x09C_x0000_0004_TYPE TYPE_D18F2x09C |
| 4978 | // Field Data |
| 4979 | #define D18F2x09C_x0000_0004_CkeFineDelay_OFFSET 0 |
| 4980 | #define D18F2x09C_x0000_0004_CkeFineDelay_WIDTH 5 |
| 4981 | #define D18F2x09C_x0000_0004_CkeFineDelay_MASK 0x1f |
| 4982 | #define D18F2x09C_x0000_0004_CkeSetup_OFFSET 5 |
| 4983 | #define D18F2x09C_x0000_0004_CkeSetup_WIDTH 1 |
| 4984 | #define D18F2x09C_x0000_0004_CkeSetup_MASK 0x20 |
| 4985 | #define D18F2x09C_x0000_0004_Reserved_7_6_OFFSET 6 |
| 4986 | #define D18F2x09C_x0000_0004_Reserved_7_6_WIDTH 2 |
| 4987 | #define D18F2x09C_x0000_0004_Reserved_7_6_MASK 0xc0 |
| 4988 | #define D18F2x09C_x0000_0004_CsOdtFineDelay_OFFSET 8 |
| 4989 | #define D18F2x09C_x0000_0004_CsOdtFineDelay_WIDTH 5 |
| 4990 | #define D18F2x09C_x0000_0004_CsOdtFineDelay_MASK 0x1f00 |
| 4991 | #define D18F2x09C_x0000_0004_CsOdtSetup_OFFSET 13 |
| 4992 | #define D18F2x09C_x0000_0004_CsOdtSetup_WIDTH 1 |
| 4993 | #define D18F2x09C_x0000_0004_CsOdtSetup_MASK 0x2000 |
| 4994 | #define D18F2x09C_x0000_0004_Reserved_15_14_OFFSET 14 |
| 4995 | #define D18F2x09C_x0000_0004_Reserved_15_14_WIDTH 2 |
| 4996 | #define D18F2x09C_x0000_0004_Reserved_15_14_MASK 0xc000 |
| 4997 | #define D18F2x09C_x0000_0004_AddrCmdFineDelay_OFFSET 16 |
| 4998 | #define D18F2x09C_x0000_0004_AddrCmdFineDelay_WIDTH 5 |
| 4999 | #define D18F2x09C_x0000_0004_AddrCmdFineDelay_MASK 0x1f0000 |
| 5000 | #define D18F2x09C_x0000_0004_AddrCmdSetup_OFFSET 21 |
| 5001 | #define D18F2x09C_x0000_0004_AddrCmdSetup_WIDTH 1 |
| 5002 | #define D18F2x09C_x0000_0004_AddrCmdSetup_MASK 0x200000 |
| 5003 | #define D18F2x09C_x0000_0004_Reserved_31_22_OFFSET 22 |
| 5004 | #define D18F2x09C_x0000_0004_Reserved_31_22_WIDTH 10 |
| 5005 | #define D18F2x09C_x0000_0004_Reserved_31_22_MASK 0xffc00000 |
| 5006 | |
| 5007 | /// D18F2x09C_x0000_0004 |
| 5008 | typedef union { |
| 5009 | struct { ///< |
| 5010 | UINT32 CkeFineDelay:5 ; ///< |
| 5011 | UINT32 CkeSetup:1 ; ///< |
| 5012 | UINT32 Reserved_7_6:2 ; ///< |
| 5013 | UINT32 CsOdtFineDelay:5 ; ///< |
| 5014 | UINT32 CsOdtSetup:1 ; ///< |
| 5015 | UINT32 Reserved_15_14:2 ; ///< |
| 5016 | UINT32 AddrCmdFineDelay:5 ; ///< |
| 5017 | UINT32 AddrCmdSetup:1 ; ///< |
| 5018 | UINT32 Reserved_31_22:10; ///< |
| 5019 | } Field; ///< |
| 5020 | UINT32 Value; ///< |
| 5021 | } D18F2x09C_x0000_0004_STRUCT; |
| 5022 | |
| 5023 | // **** D18F2x09C_x0000_0005 Register Definition **** |
| 5024 | // Address |
| 5025 | #define D18F2x09C_x0000_0005_ADDRESS 0x5 |
| 5026 | |
| 5027 | // Type |
| 5028 | #define D18F2x09C_x0000_0005_TYPE TYPE_D18F2x09C |
| 5029 | // Field Data |
| 5030 | #define D18F2x09C_x0000_0005_Reserved_0_0_OFFSET 0 |
| 5031 | #define D18F2x09C_x0000_0005_Reserved_0_0_WIDTH 1 |
| 5032 | #define D18F2x09C_x0000_0005_Reserved_0_0_MASK 0x1 |
| 5033 | #define D18F2x09C_x0000_0005_RdDqsTime_Byte0_OFFSET 1 |
| 5034 | #define D18F2x09C_x0000_0005_RdDqsTime_Byte0_WIDTH 5 |
| 5035 | #define D18F2x09C_x0000_0005_RdDqsTime_Byte0_MASK 0x3e |
| 5036 | #define D18F2x09C_x0000_0005_Reserved_8_6_OFFSET 6 |
| 5037 | #define D18F2x09C_x0000_0005_Reserved_8_6_WIDTH 3 |
| 5038 | #define D18F2x09C_x0000_0005_Reserved_8_6_MASK 0x1c0 |
| 5039 | #define D18F2x09C_x0000_0005_RdDqsTime_Byte1_OFFSET 9 |
| 5040 | #define D18F2x09C_x0000_0005_RdDqsTime_Byte1_WIDTH 5 |
| 5041 | #define D18F2x09C_x0000_0005_RdDqsTime_Byte1_MASK 0x3e00 |
| 5042 | #define D18F2x09C_x0000_0005_Reserved_16_14_OFFSET 14 |
| 5043 | #define D18F2x09C_x0000_0005_Reserved_16_14_WIDTH 3 |
| 5044 | #define D18F2x09C_x0000_0005_Reserved_16_14_MASK 0x1c000 |
| 5045 | #define D18F2x09C_x0000_0005_RdDqsTime_Byte2_OFFSET 17 |
| 5046 | #define D18F2x09C_x0000_0005_RdDqsTime_Byte2_WIDTH 5 |
| 5047 | #define D18F2x09C_x0000_0005_RdDqsTime_Byte2_MASK 0x3e0000 |
| 5048 | #define D18F2x09C_x0000_0005_Reserved_24_22_OFFSET 22 |
| 5049 | #define D18F2x09C_x0000_0005_Reserved_24_22_WIDTH 3 |
| 5050 | #define D18F2x09C_x0000_0005_Reserved_24_22_MASK 0x1c00000 |
| 5051 | #define D18F2x09C_x0000_0005_RdDqsTime_Byte3_OFFSET 25 |
| 5052 | #define D18F2x09C_x0000_0005_RdDqsTime_Byte3_WIDTH 5 |
| 5053 | #define D18F2x09C_x0000_0005_RdDqsTime_Byte3_MASK 0x3e000000 |
| 5054 | #define D18F2x09C_x0000_0005_Reserved_31_30_OFFSET 30 |
| 5055 | #define D18F2x09C_x0000_0005_Reserved_31_30_WIDTH 2 |
| 5056 | #define D18F2x09C_x0000_0005_Reserved_31_30_MASK 0xc0000000 |
| 5057 | |
| 5058 | /// D18F2x09C_x0000_0005 |
| 5059 | typedef union { |
| 5060 | struct { ///< |
| 5061 | UINT32 Reserved_0_0:1 ; ///< |
| 5062 | UINT32 RdDqsTime_Byte0:5 ; ///< |
| 5063 | UINT32 Reserved_8_6:3 ; ///< |
| 5064 | UINT32 RdDqsTime_Byte1:5 ; ///< |
| 5065 | UINT32 Reserved_16_14:3 ; ///< |
| 5066 | UINT32 RdDqsTime_Byte2:5 ; ///< |
| 5067 | UINT32 Reserved_24_22:3 ; ///< |
| 5068 | UINT32 RdDqsTime_Byte3:5 ; ///< |
| 5069 | UINT32 Reserved_31_30:2 ; ///< |
| 5070 | } Field; ///< |
| 5071 | UINT32 Value; ///< |
| 5072 | } D18F2x09C_x0000_0005_STRUCT; |
| 5073 | |
| 5074 | // **** D18F2x09C_x0000_0006 Register Definition **** |
| 5075 | // Address |
| 5076 | #define D18F2x09C_x0000_0006_ADDRESS 0x6 |
| 5077 | |
| 5078 | // Type |
| 5079 | #define D18F2x09C_x0000_0006_TYPE TYPE_D18F2x09C |
| 5080 | // Field Data |
| 5081 | #define D18F2x09C_x0000_0006_Reserved_0_0_OFFSET 0 |
| 5082 | #define D18F2x09C_x0000_0006_Reserved_0_0_WIDTH 1 |
| 5083 | #define D18F2x09C_x0000_0006_Reserved_0_0_MASK 0x1 |
| 5084 | #define D18F2x09C_x0000_0006_RdDqsTime_Byte4_OFFSET 1 |
| 5085 | #define D18F2x09C_x0000_0006_RdDqsTime_Byte4_WIDTH 5 |
| 5086 | #define D18F2x09C_x0000_0006_RdDqsTime_Byte4_MASK 0x3e |
| 5087 | #define D18F2x09C_x0000_0006_Reserved_8_6_OFFSET 6 |
| 5088 | #define D18F2x09C_x0000_0006_Reserved_8_6_WIDTH 3 |
| 5089 | #define D18F2x09C_x0000_0006_Reserved_8_6_MASK 0x1c0 |
| 5090 | #define D18F2x09C_x0000_0006_RdDqsTime_Byte5_OFFSET 9 |
| 5091 | #define D18F2x09C_x0000_0006_RdDqsTime_Byte5_WIDTH 5 |
| 5092 | #define D18F2x09C_x0000_0006_RdDqsTime_Byte5_MASK 0x3e00 |
| 5093 | #define D18F2x09C_x0000_0006_Reserved_16_14_OFFSET 14 |
| 5094 | #define D18F2x09C_x0000_0006_Reserved_16_14_WIDTH 3 |
| 5095 | #define D18F2x09C_x0000_0006_Reserved_16_14_MASK 0x1c000 |
| 5096 | #define D18F2x09C_x0000_0006_RdDqsTime_Byte6_OFFSET 17 |
| 5097 | #define D18F2x09C_x0000_0006_RdDqsTime_Byte6_WIDTH 5 |
| 5098 | #define D18F2x09C_x0000_0006_RdDqsTime_Byte6_MASK 0x3e0000 |
| 5099 | #define D18F2x09C_x0000_0006_Reserved_24_22_OFFSET 22 |
| 5100 | #define D18F2x09C_x0000_0006_Reserved_24_22_WIDTH 3 |
| 5101 | #define D18F2x09C_x0000_0006_Reserved_24_22_MASK 0x1c00000 |
| 5102 | #define D18F2x09C_x0000_0006_RdDqsTime_Byte7_OFFSET 25 |
| 5103 | #define D18F2x09C_x0000_0006_RdDqsTime_Byte7_WIDTH 5 |
| 5104 | #define D18F2x09C_x0000_0006_RdDqsTime_Byte7_MASK 0x3e000000 |
| 5105 | #define D18F2x09C_x0000_0006_Reserved_31_30_OFFSET 30 |
| 5106 | #define D18F2x09C_x0000_0006_Reserved_31_30_WIDTH 2 |
| 5107 | #define D18F2x09C_x0000_0006_Reserved_31_30_MASK 0xc0000000 |
| 5108 | |
| 5109 | /// D18F2x09C_x0000_0006 |
| 5110 | typedef union { |
| 5111 | struct { ///< |
| 5112 | UINT32 Reserved_0_0:1 ; ///< |
| 5113 | UINT32 RdDqsTime_Byte4:5 ; ///< |
| 5114 | UINT32 Reserved_8_6:3 ; ///< |
| 5115 | UINT32 RdDqsTime_Byte5:5 ; ///< |
| 5116 | UINT32 Reserved_16_14:3 ; ///< |
| 5117 | UINT32 RdDqsTime_Byte6:5 ; ///< |
| 5118 | UINT32 Reserved_24_22:3 ; ///< |
| 5119 | UINT32 RdDqsTime_Byte7:5 ; ///< |
| 5120 | UINT32 Reserved_31_30:2 ; ///< |
| 5121 | } Field; ///< |
| 5122 | UINT32 Value; ///< |
| 5123 | } D18F2x09C_x0000_0006_STRUCT; |
| 5124 | |
| 5125 | |
| 5126 | |
| 5127 | // **** D18F2x09C_x0000_000D Register Definition **** |
| 5128 | // Address |
| 5129 | #define D18F2x09C_x0000_000D_ADDRESS 0xd |
| 5130 | |
| 5131 | // Type |
| 5132 | #define D18F2x09C_x0000_000D_TYPE TYPE_D18F2x09C |
| 5133 | // Field Data |
| 5134 | #define D18F2x09C_x0000_000D_TxMaxDurDllNoLock_OFFSET 0 |
| 5135 | #define D18F2x09C_x0000_000D_TxMaxDurDllNoLock_WIDTH 4 |
| 5136 | #define D18F2x09C_x0000_000D_TxMaxDurDllNoLock_MASK 0xf |
| 5137 | #define D18F2x09C_x0000_000D_TxCPUpdPeriod_OFFSET 4 |
| 5138 | #define D18F2x09C_x0000_000D_TxCPUpdPeriod_WIDTH 3 |
| 5139 | #define D18F2x09C_x0000_000D_TxCPUpdPeriod_MASK 0x70 |
| 5140 | #define D18F2x09C_x0000_000D_Reserved_7_7_OFFSET 7 |
| 5141 | #define D18F2x09C_x0000_000D_Reserved_7_7_WIDTH 1 |
| 5142 | #define D18F2x09C_x0000_000D_Reserved_7_7_MASK 0x80 |
| 5143 | #define D18F2x09C_x0000_000D_TxDLLWakeupTime_OFFSET 8 |
| 5144 | #define D18F2x09C_x0000_000D_TxDLLWakeupTime_WIDTH 2 |
| 5145 | #define D18F2x09C_x0000_000D_TxDLLWakeupTime_MASK 0x300 |
| 5146 | #define D18F2x09C_x0000_000D_Reserved_15_10_OFFSET 10 |
| 5147 | #define D18F2x09C_x0000_000D_Reserved_15_10_WIDTH 6 |
| 5148 | #define D18F2x09C_x0000_000D_Reserved_15_10_MASK 0xfc00 |
| 5149 | #define D18F2x09C_x0000_000D_RxMaxDurDllNoLock_OFFSET 16 |
| 5150 | #define D18F2x09C_x0000_000D_RxMaxDurDllNoLock_WIDTH 4 |
| 5151 | #define D18F2x09C_x0000_000D_RxMaxDurDllNoLock_MASK 0xf0000 |
| 5152 | #define D18F2x09C_x0000_000D_RxCPUpdPeriod_OFFSET 20 |
| 5153 | #define D18F2x09C_x0000_000D_RxCPUpdPeriod_WIDTH 3 |
| 5154 | #define D18F2x09C_x0000_000D_RxCPUpdPeriod_MASK 0x700000 |
| 5155 | #define D18F2x09C_x0000_000D_Reserved_23_23_OFFSET 23 |
| 5156 | #define D18F2x09C_x0000_000D_Reserved_23_23_WIDTH 1 |
| 5157 | #define D18F2x09C_x0000_000D_Reserved_23_23_MASK 0x800000 |
| 5158 | #define D18F2x09C_x0000_000D_RxDLLWakeupTime_OFFSET 24 |
| 5159 | #define D18F2x09C_x0000_000D_RxDLLWakeupTime_WIDTH 2 |
| 5160 | #define D18F2x09C_x0000_000D_RxDLLWakeupTime_MASK 0x3000000 |
| 5161 | #define D18F2x09C_x0000_000D_Reserved_31_26_OFFSET 26 |
| 5162 | #define D18F2x09C_x0000_000D_Reserved_31_26_WIDTH 6 |
| 5163 | #define D18F2x09C_x0000_000D_Reserved_31_26_MASK 0xfc000000 |
| 5164 | |
| 5165 | /// D18F2x09C_x0000_000D |
| 5166 | typedef union { |
| 5167 | struct { ///< |
| 5168 | UINT32 TxMaxDurDllNoLock:4 ; ///< |
| 5169 | UINT32 TxCPUpdPeriod:3 ; ///< |
| 5170 | UINT32 Reserved_7_7:1 ; ///< |
| 5171 | UINT32 TxDLLWakeupTime:2 ; ///< |
| 5172 | UINT32 Reserved_15_10:6 ; ///< |
| 5173 | UINT32 RxMaxDurDllNoLock:4 ; ///< |
| 5174 | UINT32 RxCPUpdPeriod:3 ; ///< |
| 5175 | UINT32 Reserved_23_23:1 ; ///< |
| 5176 | UINT32 RxDLLWakeupTime:2 ; ///< |
| 5177 | UINT32 Reserved_31_26:6 ; ///< |
| 5178 | } Field; ///< |
| 5179 | UINT32 Value; ///< |
| 5180 | } D18F2x09C_x0000_000D_STRUCT; |
| 5181 | |
| 5182 | |
| 5183 | // **** D18F2x09C_x0000_0030 Register Definition **** |
| 5184 | // Address |
| 5185 | #define D18F2x09C_x0000_0030_ADDRESS 0x30 |
| 5186 | |
| 5187 | // Type |
| 5188 | #define D18F2x09C_x0000_0030_TYPE TYPE_D18F2x09C |
| 5189 | // Field Data |
| 5190 | #define D18F2x09C_x0000_0030_WrDqsFineDly_Byte0_OFFSET 0 |
| 5191 | #define D18F2x09C_x0000_0030_WrDqsFineDly_Byte0_WIDTH 5 |
| 5192 | #define D18F2x09C_x0000_0030_WrDqsFineDly_Byte0_MASK 0x1f |
| 5193 | #define D18F2x09C_x0000_0030_WrDqsGrossDly_Byte0_OFFSET 5 |
| 5194 | #define D18F2x09C_x0000_0030_WrDqsGrossDly_Byte0_WIDTH 3 |
| 5195 | #define D18F2x09C_x0000_0030_WrDqsGrossDly_Byte0_MASK 0xe0 |
| 5196 | #define D18F2x09C_x0000_0030_Reserved_15_8_OFFSET 8 |
| 5197 | #define D18F2x09C_x0000_0030_Reserved_15_8_WIDTH 8 |
| 5198 | #define D18F2x09C_x0000_0030_Reserved_15_8_MASK 0xff00 |
| 5199 | #define D18F2x09C_x0000_0030_WrDqsFineDly_Byte1_OFFSET 16 |
| 5200 | #define D18F2x09C_x0000_0030_WrDqsFineDly_Byte1_WIDTH 5 |
| 5201 | #define D18F2x09C_x0000_0030_WrDqsFineDly_Byte1_MASK 0x1f0000 |
| 5202 | #define D18F2x09C_x0000_0030_WrDqsGrossDly_Byte1_OFFSET 21 |
| 5203 | #define D18F2x09C_x0000_0030_WrDqsGrossDly_Byte1_WIDTH 3 |
| 5204 | #define D18F2x09C_x0000_0030_WrDqsGrossDly_Byte1_MASK 0xe00000 |
| 5205 | #define D18F2x09C_x0000_0030_Reserved_31_24_OFFSET 24 |
| 5206 | #define D18F2x09C_x0000_0030_Reserved_31_24_WIDTH 8 |
| 5207 | #define D18F2x09C_x0000_0030_Reserved_31_24_MASK 0xff000000 |
| 5208 | |
| 5209 | /// D18F2x09C_x0000_0030 |
| 5210 | typedef union { |
| 5211 | struct { ///< |
| 5212 | UINT32 WrDqsFineDly_Byte0:5 ; ///< |
| 5213 | UINT32 WrDqsGrossDly_Byte0:3 ; ///< |
| 5214 | UINT32 Reserved_15_8:8 ; ///< |
| 5215 | UINT32 WrDqsFineDly_Byte1:5 ; ///< |
| 5216 | UINT32 WrDqsGrossDly_Byte1:3 ; ///< |
| 5217 | UINT32 Reserved_31_24:8 ; ///< |
| 5218 | } Field; ///< |
| 5219 | UINT32 Value; ///< |
| 5220 | } D18F2x09C_x0000_0030_STRUCT; |
| 5221 | |
| 5222 | // **** D18F2x09C_x0000_0031 Register Definition **** |
| 5223 | // Address |
| 5224 | #define D18F2x09C_x0000_0031_ADDRESS 0x31 |
| 5225 | |
| 5226 | // Type |
| 5227 | #define D18F2x09C_x0000_0031_TYPE TYPE_D18F2x09C |
| 5228 | // Field Data |
| 5229 | #define D18F2x09C_x0000_0031_WrDqsFineDly_Byte2_OFFSET 0 |
| 5230 | #define D18F2x09C_x0000_0031_WrDqsFineDly_Byte2_WIDTH 5 |
| 5231 | #define D18F2x09C_x0000_0031_WrDqsFineDly_Byte2_MASK 0x1f |
| 5232 | #define D18F2x09C_x0000_0031_WrDqsGrossDly_Byte2_OFFSET 5 |
| 5233 | #define D18F2x09C_x0000_0031_WrDqsGrossDly_Byte2_WIDTH 3 |
| 5234 | #define D18F2x09C_x0000_0031_WrDqsGrossDly_Byte2_MASK 0xe0 |
| 5235 | #define D18F2x09C_x0000_0031_Reserved_15_8_OFFSET 8 |
| 5236 | #define D18F2x09C_x0000_0031_Reserved_15_8_WIDTH 8 |
| 5237 | #define D18F2x09C_x0000_0031_Reserved_15_8_MASK 0xff00 |
| 5238 | #define D18F2x09C_x0000_0031_WrDqsFineDly_Byte3_OFFSET 16 |
| 5239 | #define D18F2x09C_x0000_0031_WrDqsFineDly_Byte3_WIDTH 5 |
| 5240 | #define D18F2x09C_x0000_0031_WrDqsFineDly_Byte3_MASK 0x1f0000 |
| 5241 | #define D18F2x09C_x0000_0031_WrDqsGrossDly_Byte3_OFFSET 21 |
| 5242 | #define D18F2x09C_x0000_0031_WrDqsGrossDly_Byte3_WIDTH 3 |
| 5243 | #define D18F2x09C_x0000_0031_WrDqsGrossDly_Byte3_MASK 0xe00000 |
| 5244 | #define D18F2x09C_x0000_0031_Reserved_31_24_OFFSET 24 |
| 5245 | #define D18F2x09C_x0000_0031_Reserved_31_24_WIDTH 8 |
| 5246 | #define D18F2x09C_x0000_0031_Reserved_31_24_MASK 0xff000000 |
| 5247 | |
| 5248 | /// D18F2x09C_x0000_0031 |
| 5249 | typedef union { |
| 5250 | struct { ///< |
| 5251 | UINT32 WrDqsFineDly_Byte2:5 ; ///< |
| 5252 | UINT32 WrDqsGrossDly_Byte2:3 ; ///< |
| 5253 | UINT32 Reserved_15_8:8 ; ///< |
| 5254 | UINT32 WrDqsFineDly_Byte3:5 ; ///< |
| 5255 | UINT32 WrDqsGrossDly_Byte3:3 ; ///< |
| 5256 | UINT32 Reserved_31_24:8 ; ///< |
| 5257 | } Field; ///< |
| 5258 | UINT32 Value; ///< |
| 5259 | } D18F2x09C_x0000_0031_STRUCT; |
| 5260 | |
| 5261 | // **** D18F2x09C_x0000_0033 Register Definition **** |
| 5262 | // Address |
| 5263 | #define D18F2x09C_x0000_0033_ADDRESS 0x33 |
| 5264 | |
| 5265 | // Type |
| 5266 | #define D18F2x09C_x0000_0033_TYPE TYPE_D18F2x09C |
| 5267 | // Field Data |
| 5268 | #define D18F2x09C_x0000_0033_WrDqsFineDly_Byte0_OFFSET 0 |
| 5269 | #define D18F2x09C_x0000_0033_WrDqsFineDly_Byte0_WIDTH 5 |
| 5270 | #define D18F2x09C_x0000_0033_WrDqsFineDly_Byte0_MASK 0x1f |
| 5271 | #define D18F2x09C_x0000_0033_WrDqsGrossDly_Byte0_OFFSET 5 |
| 5272 | #define D18F2x09C_x0000_0033_WrDqsGrossDly_Byte0_WIDTH 3 |
| 5273 | #define D18F2x09C_x0000_0033_WrDqsGrossDly_Byte0_MASK 0xe0 |
| 5274 | #define D18F2x09C_x0000_0033_Reserved_15_8_OFFSET 8 |
| 5275 | #define D18F2x09C_x0000_0033_Reserved_15_8_WIDTH 8 |
| 5276 | #define D18F2x09C_x0000_0033_Reserved_15_8_MASK 0xff00 |
| 5277 | #define D18F2x09C_x0000_0033_WrDqsFineDly_Byte1_OFFSET 16 |
| 5278 | #define D18F2x09C_x0000_0033_WrDqsFineDly_Byte1_WIDTH 5 |
| 5279 | #define D18F2x09C_x0000_0033_WrDqsFineDly_Byte1_MASK 0x1f0000 |
| 5280 | #define D18F2x09C_x0000_0033_WrDqsGrossDly_Byte1_OFFSET 21 |
| 5281 | #define D18F2x09C_x0000_0033_WrDqsGrossDly_Byte1_WIDTH 3 |
| 5282 | #define D18F2x09C_x0000_0033_WrDqsGrossDly_Byte1_MASK 0xe00000 |
| 5283 | #define D18F2x09C_x0000_0033_Reserved_31_24_OFFSET 24 |
| 5284 | #define D18F2x09C_x0000_0033_Reserved_31_24_WIDTH 8 |
| 5285 | #define D18F2x09C_x0000_0033_Reserved_31_24_MASK 0xff000000 |
| 5286 | |
| 5287 | /// D18F2x09C_x0000_0033 |
| 5288 | typedef union { |
| 5289 | struct { ///< |
| 5290 | UINT32 WrDqsFineDly_Byte0:5 ; ///< |
| 5291 | UINT32 WrDqsGrossDly_Byte0:3 ; ///< |
| 5292 | UINT32 Reserved_15_8:8 ; ///< |
| 5293 | UINT32 WrDqsFineDly_Byte1:5 ; ///< |
| 5294 | UINT32 WrDqsGrossDly_Byte1:3 ; ///< |
| 5295 | UINT32 Reserved_31_24:8 ; ///< |
| 5296 | } Field; ///< |
| 5297 | UINT32 Value; ///< |
| 5298 | } D18F2x09C_x0000_0033_STRUCT; |
| 5299 | |
| 5300 | // **** D18F2x09C_x0000_0034 Register Definition **** |
| 5301 | // Address |
| 5302 | #define D18F2x09C_x0000_0034_ADDRESS 0x34 |
| 5303 | |
| 5304 | // Type |
| 5305 | #define D18F2x09C_x0000_0034_TYPE TYPE_D18F2x09C |
| 5306 | // Field Data |
| 5307 | #define D18F2x09C_x0000_0034_WrDqsFineDly_Byte2_OFFSET 0 |
| 5308 | #define D18F2x09C_x0000_0034_WrDqsFineDly_Byte2_WIDTH 5 |
| 5309 | #define D18F2x09C_x0000_0034_WrDqsFineDly_Byte2_MASK 0x1f |
| 5310 | #define D18F2x09C_x0000_0034_WrDqsGrossDly_Byte2_OFFSET 5 |
| 5311 | #define D18F2x09C_x0000_0034_WrDqsGrossDly_Byte2_WIDTH 3 |
| 5312 | #define D18F2x09C_x0000_0034_WrDqsGrossDly_Byte2_MASK 0xe0 |
| 5313 | #define D18F2x09C_x0000_0034_Reserved_15_8_OFFSET 8 |
| 5314 | #define D18F2x09C_x0000_0034_Reserved_15_8_WIDTH 8 |
| 5315 | #define D18F2x09C_x0000_0034_Reserved_15_8_MASK 0xff00 |
| 5316 | #define D18F2x09C_x0000_0034_WrDqsFineDly_Byte3_OFFSET 16 |
| 5317 | #define D18F2x09C_x0000_0034_WrDqsFineDly_Byte3_WIDTH 5 |
| 5318 | #define D18F2x09C_x0000_0034_WrDqsFineDly_Byte3_MASK 0x1f0000 |
| 5319 | #define D18F2x09C_x0000_0034_WrDqsGrossDly_Byte3_OFFSET 21 |
| 5320 | #define D18F2x09C_x0000_0034_WrDqsGrossDly_Byte3_WIDTH 3 |
| 5321 | #define D18F2x09C_x0000_0034_WrDqsGrossDly_Byte3_MASK 0xe00000 |
| 5322 | #define D18F2x09C_x0000_0034_Reserved_31_24_OFFSET 24 |
| 5323 | #define D18F2x09C_x0000_0034_Reserved_31_24_WIDTH 8 |
| 5324 | #define D18F2x09C_x0000_0034_Reserved_31_24_MASK 0xff000000 |
| 5325 | |
| 5326 | /// D18F2x09C_x0000_0034 |
| 5327 | typedef union { |
| 5328 | struct { ///< |
| 5329 | UINT32 WrDqsFineDly_Byte2:5 ; ///< |
| 5330 | UINT32 WrDqsGrossDly_Byte2:3 ; ///< |
| 5331 | UINT32 Reserved_15_8:8 ; ///< |
| 5332 | UINT32 WrDqsFineDly_Byte3:5 ; ///< |
| 5333 | UINT32 WrDqsGrossDly_Byte3:3 ; ///< |
| 5334 | UINT32 Reserved_31_24:8 ; ///< |
| 5335 | } Field; ///< |
| 5336 | UINT32 Value; ///< |
| 5337 | } D18F2x09C_x0000_0034_STRUCT; |
| 5338 | |
| 5339 | // **** D18F2x09C_x0000_0040 Register Definition **** |
| 5340 | // Address |
| 5341 | #define D18F2x09C_x0000_0040_ADDRESS 0x40 |
| 5342 | |
| 5343 | // Type |
| 5344 | #define D18F2x09C_x0000_0040_TYPE TYPE_D18F2x09C |
| 5345 | // Field Data |
| 5346 | #define D18F2x09C_x0000_0040_WrDqsFineDly_Byte4_OFFSET 0 |
| 5347 | #define D18F2x09C_x0000_0040_WrDqsFineDly_Byte4_WIDTH 5 |
| 5348 | #define D18F2x09C_x0000_0040_WrDqsFineDly_Byte4_MASK 0x1f |
| 5349 | #define D18F2x09C_x0000_0040_WrDqsGrossDly_Byte4_OFFSET 5 |
| 5350 | #define D18F2x09C_x0000_0040_WrDqsGrossDly_Byte4_WIDTH 3 |
| 5351 | #define D18F2x09C_x0000_0040_WrDqsGrossDly_Byte4_MASK 0xe0 |
| 5352 | #define D18F2x09C_x0000_0040_Reserved_15_8_OFFSET 8 |
| 5353 | #define D18F2x09C_x0000_0040_Reserved_15_8_WIDTH 8 |
| 5354 | #define D18F2x09C_x0000_0040_Reserved_15_8_MASK 0xff00 |
| 5355 | #define D18F2x09C_x0000_0040_WrDqsFineDly_Byte5_OFFSET 16 |
| 5356 | #define D18F2x09C_x0000_0040_WrDqsFineDly_Byte5_WIDTH 5 |
| 5357 | #define D18F2x09C_x0000_0040_WrDqsFineDly_Byte5_MASK 0x1f0000 |
| 5358 | #define D18F2x09C_x0000_0040_WrDqsGrossDly_Byte5_OFFSET 21 |
| 5359 | #define D18F2x09C_x0000_0040_WrDqsGrossDly_Byte5_WIDTH 3 |
| 5360 | #define D18F2x09C_x0000_0040_WrDqsGrossDly_Byte5_MASK 0xe00000 |
| 5361 | #define D18F2x09C_x0000_0040_Reserved_31_24_OFFSET 24 |
| 5362 | #define D18F2x09C_x0000_0040_Reserved_31_24_WIDTH 8 |
| 5363 | #define D18F2x09C_x0000_0040_Reserved_31_24_MASK 0xff000000 |
| 5364 | |
| 5365 | /// D18F2x09C_x0000_0040 |
| 5366 | typedef union { |
| 5367 | struct { ///< |
| 5368 | UINT32 WrDqsFineDly_Byte4:5 ; ///< |
| 5369 | UINT32 WrDqsGrossDly_Byte4:3 ; ///< |
| 5370 | UINT32 Reserved_15_8:8 ; ///< |
| 5371 | UINT32 WrDqsFineDly_Byte5:5 ; ///< |
| 5372 | UINT32 WrDqsGrossDly_Byte5:3 ; ///< |
| 5373 | UINT32 Reserved_31_24:8 ; ///< |
| 5374 | } Field; ///< |
| 5375 | UINT32 Value; ///< |
| 5376 | } D18F2x09C_x0000_0040_STRUCT; |
| 5377 | |
| 5378 | // **** D18F2x09C_x0000_0041 Register Definition **** |
| 5379 | // Address |
| 5380 | #define D18F2x09C_x0000_0041_ADDRESS 0x41 |
| 5381 | |
| 5382 | // Type |
| 5383 | #define D18F2x09C_x0000_0041_TYPE TYPE_D18F2x09C |
| 5384 | // Field Data |
| 5385 | #define D18F2x09C_x0000_0041_WrDqsFineDly_Byte6_OFFSET 0 |
| 5386 | #define D18F2x09C_x0000_0041_WrDqsFineDly_Byte6_WIDTH 5 |
| 5387 | #define D18F2x09C_x0000_0041_WrDqsFineDly_Byte6_MASK 0x1f |
| 5388 | #define D18F2x09C_x0000_0041_WrDqsGrossDly_Byte6_OFFSET 5 |
| 5389 | #define D18F2x09C_x0000_0041_WrDqsGrossDly_Byte6_WIDTH 3 |
| 5390 | #define D18F2x09C_x0000_0041_WrDqsGrossDly_Byte6_MASK 0xe0 |
| 5391 | #define D18F2x09C_x0000_0041_Reserved_15_8_OFFSET 8 |
| 5392 | #define D18F2x09C_x0000_0041_Reserved_15_8_WIDTH 8 |
| 5393 | #define D18F2x09C_x0000_0041_Reserved_15_8_MASK 0xff00 |
| 5394 | #define D18F2x09C_x0000_0041_WrDqsFineDly_Byte7_OFFSET 16 |
| 5395 | #define D18F2x09C_x0000_0041_WrDqsFineDly_Byte7_WIDTH 5 |
| 5396 | #define D18F2x09C_x0000_0041_WrDqsFineDly_Byte7_MASK 0x1f0000 |
| 5397 | #define D18F2x09C_x0000_0041_WrDqsGrossDly_Byte7_OFFSET 21 |
| 5398 | #define D18F2x09C_x0000_0041_WrDqsGrossDly_Byte7_WIDTH 3 |
| 5399 | #define D18F2x09C_x0000_0041_WrDqsGrossDly_Byte7_MASK 0xe00000 |
| 5400 | #define D18F2x09C_x0000_0041_Reserved_31_24_OFFSET 24 |
| 5401 | #define D18F2x09C_x0000_0041_Reserved_31_24_WIDTH 8 |
| 5402 | #define D18F2x09C_x0000_0041_Reserved_31_24_MASK 0xff000000 |
| 5403 | |
| 5404 | /// D18F2x09C_x0000_0041 |
| 5405 | typedef union { |
| 5406 | struct { ///< |
| 5407 | UINT32 WrDqsFineDly_Byte6:5 ; ///< |
| 5408 | UINT32 WrDqsGrossDly_Byte6:3 ; ///< |
| 5409 | UINT32 Reserved_15_8:8 ; ///< |
| 5410 | UINT32 WrDqsFineDly_Byte7:5 ; ///< |
| 5411 | UINT32 WrDqsGrossDly_Byte7:3 ; ///< |
| 5412 | UINT32 Reserved_31_24:8 ; ///< |
| 5413 | } Field; ///< |
| 5414 | UINT32 Value; ///< |
| 5415 | } D18F2x09C_x0000_0041_STRUCT; |
| 5416 | |
| 5417 | // **** D18F2x09C_x0000_0043 Register Definition **** |
| 5418 | // Address |
| 5419 | #define D18F2x09C_x0000_0043_ADDRESS 0x43 |
| 5420 | |
| 5421 | // Type |
| 5422 | #define D18F2x09C_x0000_0043_TYPE TYPE_D18F2x09C |
| 5423 | // Field Data |
| 5424 | #define D18F2x09C_x0000_0043_WrDqsFineDly_Byte4_OFFSET 0 |
| 5425 | #define D18F2x09C_x0000_0043_WrDqsFineDly_Byte4_WIDTH 5 |
| 5426 | #define D18F2x09C_x0000_0043_WrDqsFineDly_Byte4_MASK 0x1f |
| 5427 | #define D18F2x09C_x0000_0043_WrDqsGrossDly_Byte4_OFFSET 5 |
| 5428 | #define D18F2x09C_x0000_0043_WrDqsGrossDly_Byte4_WIDTH 3 |
| 5429 | #define D18F2x09C_x0000_0043_WrDqsGrossDly_Byte4_MASK 0xe0 |
| 5430 | #define D18F2x09C_x0000_0043_Reserved_15_8_OFFSET 8 |
| 5431 | #define D18F2x09C_x0000_0043_Reserved_15_8_WIDTH 8 |
| 5432 | #define D18F2x09C_x0000_0043_Reserved_15_8_MASK 0xff00 |
| 5433 | #define D18F2x09C_x0000_0043_WrDqsFineDly_Byte5_OFFSET 16 |
| 5434 | #define D18F2x09C_x0000_0043_WrDqsFineDly_Byte5_WIDTH 5 |
| 5435 | #define D18F2x09C_x0000_0043_WrDqsFineDly_Byte5_MASK 0x1f0000 |
| 5436 | #define D18F2x09C_x0000_0043_WrDqsGrossDly_Byte5_OFFSET 21 |
| 5437 | #define D18F2x09C_x0000_0043_WrDqsGrossDly_Byte5_WIDTH 3 |
| 5438 | #define D18F2x09C_x0000_0043_WrDqsGrossDly_Byte5_MASK 0xe00000 |
| 5439 | #define D18F2x09C_x0000_0043_Reserved_31_24_OFFSET 24 |
| 5440 | #define D18F2x09C_x0000_0043_Reserved_31_24_WIDTH 8 |
| 5441 | #define D18F2x09C_x0000_0043_Reserved_31_24_MASK 0xff000000 |
| 5442 | |
| 5443 | /// D18F2x09C_x0000_0043 |
| 5444 | typedef union { |
| 5445 | struct { ///< |
| 5446 | UINT32 WrDqsFineDly_Byte4:5 ; ///< |
| 5447 | UINT32 WrDqsGrossDly_Byte4:3 ; ///< |
| 5448 | UINT32 Reserved_15_8:8 ; ///< |
| 5449 | UINT32 WrDqsFineDly_Byte5:5 ; ///< |
| 5450 | UINT32 WrDqsGrossDly_Byte5:3 ; ///< |
| 5451 | UINT32 Reserved_31_24:8 ; ///< |
| 5452 | } Field; ///< |
| 5453 | UINT32 Value; ///< |
| 5454 | } D18F2x09C_x0000_0043_STRUCT; |
| 5455 | |
| 5456 | // **** D18F2x09C_x0000_0044 Register Definition **** |
| 5457 | // Address |
| 5458 | #define D18F2x09C_x0000_0044_ADDRESS 0x44 |
| 5459 | |
| 5460 | // Type |
| 5461 | #define D18F2x09C_x0000_0044_TYPE TYPE_D18F2x09C |
| 5462 | // Field Data |
| 5463 | #define D18F2x09C_x0000_0044_WrDqsFineDly_Byte6_OFFSET 0 |
| 5464 | #define D18F2x09C_x0000_0044_WrDqsFineDly_Byte6_WIDTH 5 |
| 5465 | #define D18F2x09C_x0000_0044_WrDqsFineDly_Byte6_MASK 0x1f |
| 5466 | #define D18F2x09C_x0000_0044_WrDqsGrossDly_Byte6_OFFSET 5 |
| 5467 | #define D18F2x09C_x0000_0044_WrDqsGrossDly_Byte6_WIDTH 3 |
| 5468 | #define D18F2x09C_x0000_0044_WrDqsGrossDly_Byte6_MASK 0xe0 |
| 5469 | #define D18F2x09C_x0000_0044_Reserved_15_8_OFFSET 8 |
| 5470 | #define D18F2x09C_x0000_0044_Reserved_15_8_WIDTH 8 |
| 5471 | #define D18F2x09C_x0000_0044_Reserved_15_8_MASK 0xff00 |
| 5472 | #define D18F2x09C_x0000_0044_WrDqsFineDly_Byte7_OFFSET 16 |
| 5473 | #define D18F2x09C_x0000_0044_WrDqsFineDly_Byte7_WIDTH 5 |
| 5474 | #define D18F2x09C_x0000_0044_WrDqsFineDly_Byte7_MASK 0x1f0000 |
| 5475 | #define D18F2x09C_x0000_0044_WrDqsGrossDly_Byte7_OFFSET 21 |
| 5476 | #define D18F2x09C_x0000_0044_WrDqsGrossDly_Byte7_WIDTH 3 |
| 5477 | #define D18F2x09C_x0000_0044_WrDqsGrossDly_Byte7_MASK 0xe00000 |
| 5478 | #define D18F2x09C_x0000_0044_Reserved_31_24_OFFSET 24 |
| 5479 | #define D18F2x09C_x0000_0044_Reserved_31_24_WIDTH 8 |
| 5480 | #define D18F2x09C_x0000_0044_Reserved_31_24_MASK 0xff000000 |
| 5481 | |
| 5482 | /// D18F2x09C_x0000_0044 |
| 5483 | typedef union { |
| 5484 | struct { ///< |
| 5485 | UINT32 WrDqsFineDly_Byte6:5 ; ///< |
| 5486 | UINT32 WrDqsGrossDly_Byte6:3 ; ///< |
| 5487 | UINT32 Reserved_15_8:8 ; ///< |
| 5488 | UINT32 WrDqsFineDly_Byte7:5 ; ///< |
| 5489 | UINT32 WrDqsGrossDly_Byte7:3 ; ///< |
| 5490 | UINT32 Reserved_31_24:8 ; ///< |
| 5491 | } Field; ///< |
| 5492 | UINT32 Value; ///< |
| 5493 | } D18F2x09C_x0000_0044_STRUCT; |
| 5494 | |
| 5495 | // **** D18F2x09C_x0000_0050 Register Definition **** |
| 5496 | // Address |
| 5497 | #define D18F2x09C_x0000_0050_ADDRESS 0x50 |
| 5498 | |
| 5499 | // Type |
| 5500 | #define D18F2x09C_x0000_0050_TYPE TYPE_D18F2x09C |
| 5501 | // Field Data |
| 5502 | #define D18F2x09C_x0000_0050_PhRecFineDly_Byte0_OFFSET 0 |
| 5503 | #define D18F2x09C_x0000_0050_PhRecFineDly_Byte0_WIDTH 5 |
| 5504 | #define D18F2x09C_x0000_0050_PhRecFineDly_Byte0_MASK 0x1f |
| 5505 | #define D18F2x09C_x0000_0050_PhRecGrossDly_Byte0_OFFSET 5 |
| 5506 | #define D18F2x09C_x0000_0050_PhRecGrossDly_Byte0_WIDTH 2 |
| 5507 | #define D18F2x09C_x0000_0050_PhRecGrossDly_Byte0_MASK 0x60 |
| 5508 | #define D18F2x09C_x0000_0050_Reserved_7_7_OFFSET 7 |
| 5509 | #define D18F2x09C_x0000_0050_Reserved_7_7_WIDTH 1 |
| 5510 | #define D18F2x09C_x0000_0050_Reserved_7_7_MASK 0x80 |
| 5511 | #define D18F2x09C_x0000_0050_PhRecFineDly_Byte1_OFFSET 8 |
| 5512 | #define D18F2x09C_x0000_0050_PhRecFineDly_Byte1_WIDTH 5 |
| 5513 | #define D18F2x09C_x0000_0050_PhRecFineDly_Byte1_MASK 0x1f00 |
| 5514 | #define D18F2x09C_x0000_0050_PhRecGrossDly_Byte1_OFFSET 13 |
| 5515 | #define D18F2x09C_x0000_0050_PhRecGrossDly_Byte1_WIDTH 2 |
| 5516 | #define D18F2x09C_x0000_0050_PhRecGrossDly_Byte1_MASK 0x6000 |
| 5517 | #define D18F2x09C_x0000_0050_Reserved_15_15_OFFSET 15 |
| 5518 | #define D18F2x09C_x0000_0050_Reserved_15_15_WIDTH 1 |
| 5519 | #define D18F2x09C_x0000_0050_Reserved_15_15_MASK 0x8000 |
| 5520 | #define D18F2x09C_x0000_0050_PhRecFineDly_Byte2_OFFSET 16 |
| 5521 | #define D18F2x09C_x0000_0050_PhRecFineDly_Byte2_WIDTH 5 |
| 5522 | #define D18F2x09C_x0000_0050_PhRecFineDly_Byte2_MASK 0x1f0000 |
| 5523 | #define D18F2x09C_x0000_0050_PhRecGrossDly_Byte2_OFFSET 21 |
| 5524 | #define D18F2x09C_x0000_0050_PhRecGrossDly_Byte2_WIDTH 2 |
| 5525 | #define D18F2x09C_x0000_0050_PhRecGrossDly_Byte2_MASK 0x600000 |
| 5526 | #define D18F2x09C_x0000_0050_Reserved_23_23_OFFSET 23 |
| 5527 | #define D18F2x09C_x0000_0050_Reserved_23_23_WIDTH 1 |
| 5528 | #define D18F2x09C_x0000_0050_Reserved_23_23_MASK 0x800000 |
| 5529 | #define D18F2x09C_x0000_0050_PhRecFineDly_Byte3_OFFSET 24 |
| 5530 | #define D18F2x09C_x0000_0050_PhRecFineDly_Byte3_WIDTH 5 |
| 5531 | #define D18F2x09C_x0000_0050_PhRecFineDly_Byte3_MASK 0x1f000000 |
| 5532 | #define D18F2x09C_x0000_0050_PhRecGrossDly_Byte3_OFFSET 29 |
| 5533 | #define D18F2x09C_x0000_0050_PhRecGrossDly_Byte3_WIDTH 2 |
| 5534 | #define D18F2x09C_x0000_0050_PhRecGrossDly_Byte3_MASK 0x60000000 |
| 5535 | #define D18F2x09C_x0000_0050_Reserved_31_31_OFFSET 31 |
| 5536 | #define D18F2x09C_x0000_0050_Reserved_31_31_WIDTH 1 |
| 5537 | #define D18F2x09C_x0000_0050_Reserved_31_31_MASK 0x80000000 |
| 5538 | |
| 5539 | /// D18F2x09C_x0000_0050 |
| 5540 | typedef union { |
| 5541 | struct { ///< |
| 5542 | UINT32 PhRecFineDly_Byte0:5 ; ///< |
| 5543 | UINT32 PhRecGrossDly_Byte0:2 ; ///< |
| 5544 | UINT32 Reserved_7_7:1 ; ///< |
| 5545 | UINT32 PhRecFineDly_Byte1:5 ; ///< |
| 5546 | UINT32 PhRecGrossDly_Byte1:2 ; ///< |
| 5547 | UINT32 Reserved_15_15:1 ; ///< |
| 5548 | UINT32 PhRecFineDly_Byte2:5 ; ///< |
| 5549 | UINT32 PhRecGrossDly_Byte2:2 ; ///< |
| 5550 | UINT32 Reserved_23_23:1 ; ///< |
| 5551 | UINT32 PhRecFineDly_Byte3:5 ; ///< |
| 5552 | UINT32 PhRecGrossDly_Byte3:2 ; ///< |
| 5553 | UINT32 Reserved_31_31:1 ; ///< |
| 5554 | } Field; ///< |
| 5555 | UINT32 Value; ///< |
| 5556 | } D18F2x09C_x0000_0050_STRUCT; |
| 5557 | |
| 5558 | // **** D18F2x09C_x0000_0051 Register Definition **** |
| 5559 | // Address |
| 5560 | #define D18F2x09C_x0000_0051_ADDRESS 0x51 |
| 5561 | |
| 5562 | // Type |
| 5563 | #define D18F2x09C_x0000_0051_TYPE TYPE_D18F2x09C |
| 5564 | // Field Data |
| 5565 | #define D18F2x09C_x0000_0051_PhRecFineDly_Byte4_OFFSET 0 |
| 5566 | #define D18F2x09C_x0000_0051_PhRecFineDly_Byte4_WIDTH 5 |
| 5567 | #define D18F2x09C_x0000_0051_PhRecFineDly_Byte4_MASK 0x1f |
| 5568 | #define D18F2x09C_x0000_0051_PhRecGrossDly_Byte4_OFFSET 5 |
| 5569 | #define D18F2x09C_x0000_0051_PhRecGrossDly_Byte4_WIDTH 2 |
| 5570 | #define D18F2x09C_x0000_0051_PhRecGrossDly_Byte4_MASK 0x60 |
| 5571 | #define D18F2x09C_x0000_0051_Reserved_7_7_OFFSET 7 |
| 5572 | #define D18F2x09C_x0000_0051_Reserved_7_7_WIDTH 1 |
| 5573 | #define D18F2x09C_x0000_0051_Reserved_7_7_MASK 0x80 |
| 5574 | #define D18F2x09C_x0000_0051_PhRecFineDly_Byte5_OFFSET 8 |
| 5575 | #define D18F2x09C_x0000_0051_PhRecFineDly_Byte5_WIDTH 5 |
| 5576 | #define D18F2x09C_x0000_0051_PhRecFineDly_Byte5_MASK 0x1f00 |
| 5577 | #define D18F2x09C_x0000_0051_PhRecGrossDly_Byte5_OFFSET 13 |
| 5578 | #define D18F2x09C_x0000_0051_PhRecGrossDly_Byte5_WIDTH 2 |
| 5579 | #define D18F2x09C_x0000_0051_PhRecGrossDly_Byte5_MASK 0x6000 |
| 5580 | #define D18F2x09C_x0000_0051_Reserved_15_15_OFFSET 15 |
| 5581 | #define D18F2x09C_x0000_0051_Reserved_15_15_WIDTH 1 |
| 5582 | #define D18F2x09C_x0000_0051_Reserved_15_15_MASK 0x8000 |
| 5583 | #define D18F2x09C_x0000_0051_PhRecFineDly_Byte6_OFFSET 16 |
| 5584 | #define D18F2x09C_x0000_0051_PhRecFineDly_Byte6_WIDTH 5 |
| 5585 | #define D18F2x09C_x0000_0051_PhRecFineDly_Byte6_MASK 0x1f0000 |
| 5586 | #define D18F2x09C_x0000_0051_PhRecGrossDly_Byte6_OFFSET 21 |
| 5587 | #define D18F2x09C_x0000_0051_PhRecGrossDly_Byte6_WIDTH 2 |
| 5588 | #define D18F2x09C_x0000_0051_PhRecGrossDly_Byte6_MASK 0x600000 |
| 5589 | #define D18F2x09C_x0000_0051_Reserved_23_23_OFFSET 23 |
| 5590 | #define D18F2x09C_x0000_0051_Reserved_23_23_WIDTH 1 |
| 5591 | #define D18F2x09C_x0000_0051_Reserved_23_23_MASK 0x800000 |
| 5592 | #define D18F2x09C_x0000_0051_PhRecFineDly_Byte7_OFFSET 24 |
| 5593 | #define D18F2x09C_x0000_0051_PhRecFineDly_Byte7_WIDTH 5 |
| 5594 | #define D18F2x09C_x0000_0051_PhRecFineDly_Byte7_MASK 0x1f000000 |
| 5595 | #define D18F2x09C_x0000_0051_PhRecGrossDly_Byte7_OFFSET 29 |
| 5596 | #define D18F2x09C_x0000_0051_PhRecGrossDly_Byte7_WIDTH 2 |
| 5597 | #define D18F2x09C_x0000_0051_PhRecGrossDly_Byte7_MASK 0x60000000 |
| 5598 | #define D18F2x09C_x0000_0051_Reserved_31_31_OFFSET 31 |
| 5599 | #define D18F2x09C_x0000_0051_Reserved_31_31_WIDTH 1 |
| 5600 | #define D18F2x09C_x0000_0051_Reserved_31_31_MASK 0x80000000 |
| 5601 | |
| 5602 | /// D18F2x09C_x0000_0051 |
| 5603 | typedef union { |
| 5604 | struct { ///< |
| 5605 | UINT32 PhRecFineDly_Byte4:5 ; ///< |
| 5606 | UINT32 PhRecGrossDly_Byte4:2 ; ///< |
| 5607 | UINT32 Reserved_7_7:1 ; ///< |
| 5608 | UINT32 PhRecFineDly_Byte5:5 ; ///< |
| 5609 | UINT32 PhRecGrossDly_Byte5:2 ; ///< |
| 5610 | UINT32 Reserved_15_15:1 ; ///< |
| 5611 | UINT32 PhRecFineDly_Byte6:5 ; ///< |
| 5612 | UINT32 PhRecGrossDly_Byte6:2 ; ///< |
| 5613 | UINT32 Reserved_23_23:1 ; ///< |
| 5614 | UINT32 PhRecFineDly_Byte7:5 ; ///< |
| 5615 | UINT32 PhRecGrossDly_Byte7:2 ; ///< |
| 5616 | UINT32 Reserved_31_31:1 ; ///< |
| 5617 | } Field; ///< |
| 5618 | UINT32 Value; ///< |
| 5619 | } D18F2x09C_x0000_0051_STRUCT; |
| 5620 | |
| 5621 | |
| 5622 | |
| 5623 | |
| 5624 | |
| 5625 | // **** D18F2x09C_x0D0F_0002 Register Definition **** |
| 5626 | // Address |
| 5627 | #define D18F2x09C_x0D0F_0002_ADDRESS 0xd0f0002 |
| 5628 | |
| 5629 | // Type |
| 5630 | #define D18F2x09C_x0D0F_0002_TYPE TYPE_D18F2x09C |
| 5631 | // Field Data |
| 5632 | #define D18F2x09C_x0D0F_0002_TxPreN_OFFSET 0 |
| 5633 | #define D18F2x09C_x0D0F_0002_TxPreN_WIDTH 6 |
| 5634 | #define D18F2x09C_x0D0F_0002_TxPreN_MASK 0x3f |
| 5635 | #define D18F2x09C_x0D0F_0002_TxPreP_OFFSET 6 |
| 5636 | #define D18F2x09C_x0D0F_0002_TxPreP_WIDTH 6 |
| 5637 | #define D18F2x09C_x0D0F_0002_TxPreP_MASK 0xfc0 |
| 5638 | #define D18F2x09C_x0D0F_0002_Reserved_14_12_OFFSET 12 |
| 5639 | #define D18F2x09C_x0D0F_0002_Reserved_14_12_WIDTH 3 |
| 5640 | #define D18F2x09C_x0D0F_0002_Reserved_14_12_MASK 0x7000 |
| 5641 | #define D18F2x09C_x0D0F_0002_ValidTxAndPre_OFFSET 15 |
| 5642 | #define D18F2x09C_x0D0F_0002_ValidTxAndPre_WIDTH 1 |
| 5643 | #define D18F2x09C_x0D0F_0002_ValidTxAndPre_MASK 0x8000 |
| 5644 | #define D18F2x09C_x0D0F_0002_Reserved_31_16_OFFSET 16 |
| 5645 | #define D18F2x09C_x0D0F_0002_Reserved_31_16_WIDTH 16 |
| 5646 | #define D18F2x09C_x0D0F_0002_Reserved_31_16_MASK 0xffff0000 |
| 5647 | |
| 5648 | /// D18F2x09C_x0D0F_0002 |
| 5649 | typedef union { |
| 5650 | struct { ///< |
| 5651 | UINT32 TxPreN:6 ; ///< |
| 5652 | UINT32 TxPreP:6 ; ///< |
| 5653 | UINT32 Reserved_14_12:3 ; ///< |
| 5654 | UINT32 ValidTxAndPre:1 ; ///< |
| 5655 | UINT32 Reserved_31_16:16; ///< |
| 5656 | } Field; ///< |
| 5657 | UINT32 Value; ///< |
| 5658 | } D18F2x09C_x0D0F_0002_STRUCT; |
| 5659 | |
| 5660 | // **** D18F2x09C_x0D0F_0006 Register Definition **** |
| 5661 | // Address |
| 5662 | #define D18F2x09C_x0D0F_0006_ADDRESS 0xd0f0006 |
| 5663 | |
| 5664 | // Type |
| 5665 | #define D18F2x09C_x0D0F_0006_TYPE TYPE_D18F2x09C |
| 5666 | // Field Data |
| 5667 | #define D18F2x09C_x0D0F_0006_TxPreN_OFFSET 0 |
| 5668 | #define D18F2x09C_x0D0F_0006_TxPreN_WIDTH 6 |
| 5669 | #define D18F2x09C_x0D0F_0006_TxPreN_MASK 0x3f |
| 5670 | #define D18F2x09C_x0D0F_0006_TxPreP_OFFSET 6 |
| 5671 | #define D18F2x09C_x0D0F_0006_TxPreP_WIDTH 6 |
| 5672 | #define D18F2x09C_x0D0F_0006_TxPreP_MASK 0xfc0 |
| 5673 | #define D18F2x09C_x0D0F_0006_Reserved_31_12_OFFSET 12 |
| 5674 | #define D18F2x09C_x0D0F_0006_Reserved_31_12_WIDTH 20 |
| 5675 | #define D18F2x09C_x0D0F_0006_Reserved_31_12_MASK 0xfffff000 |
| 5676 | |
| 5677 | /// D18F2x09C_x0D0F_0006 |
| 5678 | typedef union { |
| 5679 | struct { ///< |
| 5680 | UINT32 TxPreN:6 ; ///< |
| 5681 | UINT32 TxPreP:6 ; ///< |
| 5682 | UINT32 Reserved_31_12:20; ///< |
| 5683 | } Field; ///< |
| 5684 | UINT32 Value; ///< |
| 5685 | } D18F2x09C_x0D0F_0006_STRUCT; |
| 5686 | |
| 5687 | // **** D18F2x09C_x0D0F_000A Register Definition **** |
| 5688 | // Address |
| 5689 | #define D18F2x09C_x0D0F_000A_ADDRESS 0xd0f000a |
| 5690 | |
| 5691 | // Type |
| 5692 | #define D18F2x09C_x0D0F_000A_TYPE TYPE_D18F2x09C |
| 5693 | // Field Data |
| 5694 | #define D18F2x09C_x0D0F_000A_TxPreN_OFFSET 0 |
| 5695 | #define D18F2x09C_x0D0F_000A_TxPreN_WIDTH 6 |
| 5696 | #define D18F2x09C_x0D0F_000A_TxPreN_MASK 0x3f |
| 5697 | #define D18F2x09C_x0D0F_000A_TxPreP_OFFSET 6 |
| 5698 | #define D18F2x09C_x0D0F_000A_TxPreP_WIDTH 6 |
| 5699 | #define D18F2x09C_x0D0F_000A_TxPreP_MASK 0xfc0 |
| 5700 | #define D18F2x09C_x0D0F_000A_Reserved_31_12_OFFSET 12 |
| 5701 | #define D18F2x09C_x0D0F_000A_Reserved_31_12_WIDTH 20 |
| 5702 | #define D18F2x09C_x0D0F_000A_Reserved_31_12_MASK 0xfffff000 |
| 5703 | |
| 5704 | /// D18F2x09C_x0D0F_000A |
| 5705 | typedef union { |
| 5706 | struct { ///< |
| 5707 | UINT32 TxPreN:6 ; ///< |
| 5708 | UINT32 TxPreP:6 ; ///< |
| 5709 | UINT32 Reserved_31_12:20; ///< |
| 5710 | } Field; ///< |
| 5711 | UINT32 Value; ///< |
| 5712 | } D18F2x09C_x0D0F_000A_STRUCT; |
| 5713 | |
| 5714 | // **** D18F2x09C_x0D0F_000F Register Definition **** |
| 5715 | // Address |
| 5716 | #define D18F2x09C_x0D0F_000F_ADDRESS 0xd0f000f |
| 5717 | |
| 5718 | // Type |
| 5719 | #define D18F2x09C_x0D0F_000F_TYPE TYPE_D18F2x09C |
| 5720 | // Field Data |
| 5721 | #define D18F2x09C_x0D0F_000F_Reserved_11_0_OFFSET 0 |
| 5722 | #define D18F2x09C_x0D0F_000F_Reserved_11_0_WIDTH 12 |
| 5723 | #define D18F2x09C_x0D0F_000F_Reserved_11_0_MASK 0xfff |
| 5724 | #define D18F2x09C_x0D0F_000F_AlwaysEnDllClks_OFFSET 12 |
| 5725 | #define D18F2x09C_x0D0F_000F_AlwaysEnDllClks_WIDTH 3 |
| 5726 | #define D18F2x09C_x0D0F_000F_AlwaysEnDllClks_MASK 0x7000 |
| 5727 | #define D18F2x09C_x0D0F_000F_Reserved_31_15_OFFSET 15 |
| 5728 | #define D18F2x09C_x0D0F_000F_Reserved_31_15_WIDTH 17 |
| 5729 | #define D18F2x09C_x0D0F_000F_Reserved_31_15_MASK 0xffff8000 |
| 5730 | |
| 5731 | /// D18F2x09C_x0D0F_000F |
| 5732 | typedef union { |
| 5733 | struct { ///< |
| 5734 | UINT32 Reserved_11_0:12; ///< |
| 5735 | UINT32 AlwaysEnDllClks:3 ; ///< |
| 5736 | UINT32 Reserved_31_15:17; ///< |
| 5737 | } Field; ///< |
| 5738 | UINT32 Value; ///< |
| 5739 | } D18F2x09C_x0D0F_000F_STRUCT; |
| 5740 | |
| 5741 | // **** D18F2x09C_x0D0F_0010 Register Definition **** |
| 5742 | // Address |
| 5743 | #define D18F2x09C_x0D0F_0010_ADDRESS 0xd0f0010 |
| 5744 | |
| 5745 | // Type |
| 5746 | #define D18F2x09C_x0D0F_0010_TYPE TYPE_D18F2x09C |
| 5747 | // Field Data |
| 5748 | #define D18F2x09C_x0D0F_0010_Reserved_11_0_OFFSET 0 |
| 5749 | #define D18F2x09C_x0D0F_0010_Reserved_11_0_WIDTH 12 |
| 5750 | #define D18F2x09C_x0D0F_0010_Reserved_11_0_MASK 0xfff |
| 5751 | #define D18F2x09C_x0D0F_0010_EnRxPadStandby_OFFSET 12 |
| 5752 | #define D18F2x09C_x0D0F_0010_EnRxPadStandby_WIDTH 1 |
| 5753 | #define D18F2x09C_x0D0F_0010_EnRxPadStandby_MASK 0x1000 |
| 5754 | #define D18F2x09C_x0D0F_0010_Reserved_31_13_OFFSET 13 |
| 5755 | #define D18F2x09C_x0D0F_0010_Reserved_31_13_WIDTH 19 |
| 5756 | #define D18F2x09C_x0D0F_0010_Reserved_31_13_MASK 0xffffe000 |
| 5757 | |
| 5758 | /// D18F2x09C_x0D0F_0010 |
| 5759 | typedef union { |
| 5760 | struct { ///< |
| 5761 | UINT32 Reserved_11_0:12; ///< |
| 5762 | UINT32 EnRxPadStandby:1 ; ///< |
| 5763 | UINT32 Reserved_31_13:19; ///< |
| 5764 | } Field; ///< |
| 5765 | UINT32 Value; ///< |
| 5766 | } D18F2x09C_x0D0F_0010_STRUCT; |
| 5767 | |
| 5768 | |
| 5769 | |
| 5770 | |
| 5771 | // **** D18F2x09C_x0D0F_0102 Register Definition **** |
| 5772 | // Address |
| 5773 | #define D18F2x09C_x0D0F_0102_ADDRESS 0xd0f0102 |
| 5774 | |
| 5775 | // Type |
| 5776 | #define D18F2x09C_x0D0F_0102_TYPE TYPE_D18F2x09C |
| 5777 | // Field Data |
| 5778 | #define D18F2x09C_x0D0F_0102_TxPreN_OFFSET 0 |
| 5779 | #define D18F2x09C_x0D0F_0102_TxPreN_WIDTH 6 |
| 5780 | #define D18F2x09C_x0D0F_0102_TxPreN_MASK 0x3f |
| 5781 | #define D18F2x09C_x0D0F_0102_TxPreP_OFFSET 6 |
| 5782 | #define D18F2x09C_x0D0F_0102_TxPreP_WIDTH 6 |
| 5783 | #define D18F2x09C_x0D0F_0102_TxPreP_MASK 0xfc0 |
| 5784 | #define D18F2x09C_x0D0F_0102_Reserved_14_12_OFFSET 12 |
| 5785 | #define D18F2x09C_x0D0F_0102_Reserved_14_12_WIDTH 3 |
| 5786 | #define D18F2x09C_x0D0F_0102_Reserved_14_12_MASK 0x7000 |
| 5787 | #define D18F2x09C_x0D0F_0102_ValidTxAndPre_OFFSET 15 |
| 5788 | #define D18F2x09C_x0D0F_0102_ValidTxAndPre_WIDTH 1 |
| 5789 | #define D18F2x09C_x0D0F_0102_ValidTxAndPre_MASK 0x8000 |
| 5790 | #define D18F2x09C_x0D0F_0102_Reserved_31_16_OFFSET 16 |
| 5791 | #define D18F2x09C_x0D0F_0102_Reserved_31_16_WIDTH 16 |
| 5792 | #define D18F2x09C_x0D0F_0102_Reserved_31_16_MASK 0xffff0000 |
| 5793 | |
| 5794 | /// D18F2x09C_x0D0F_0102 |
| 5795 | typedef union { |
| 5796 | struct { ///< |
| 5797 | UINT32 TxPreN:6 ; ///< |
| 5798 | UINT32 TxPreP:6 ; ///< |
| 5799 | UINT32 Reserved_14_12:3 ; ///< |
| 5800 | UINT32 ValidTxAndPre:1 ; ///< |
| 5801 | UINT32 Reserved_31_16:16; ///< |
| 5802 | } Field; ///< |
| 5803 | UINT32 Value; ///< |
| 5804 | } D18F2x09C_x0D0F_0102_STRUCT; |
| 5805 | |
| 5806 | // **** D18F2x09C_x0D0F_0106 Register Definition **** |
| 5807 | // Address |
| 5808 | #define D18F2x09C_x0D0F_0106_ADDRESS 0xd0f0106 |
| 5809 | |
| 5810 | // Type |
| 5811 | #define D18F2x09C_x0D0F_0106_TYPE TYPE_D18F2x09C |
| 5812 | // Field Data |
| 5813 | #define D18F2x09C_x0D0F_0106_TxPreN_OFFSET 0 |
| 5814 | #define D18F2x09C_x0D0F_0106_TxPreN_WIDTH 6 |
| 5815 | #define D18F2x09C_x0D0F_0106_TxPreN_MASK 0x3f |
| 5816 | #define D18F2x09C_x0D0F_0106_TxPreP_OFFSET 6 |
| 5817 | #define D18F2x09C_x0D0F_0106_TxPreP_WIDTH 6 |
| 5818 | #define D18F2x09C_x0D0F_0106_TxPreP_MASK 0xfc0 |
| 5819 | #define D18F2x09C_x0D0F_0106_Reserved_31_12_OFFSET 12 |
| 5820 | #define D18F2x09C_x0D0F_0106_Reserved_31_12_WIDTH 20 |
| 5821 | #define D18F2x09C_x0D0F_0106_Reserved_31_12_MASK 0xfffff000 |
| 5822 | |
| 5823 | /// D18F2x09C_x0D0F_0106 |
| 5824 | typedef union { |
| 5825 | struct { ///< |
| 5826 | UINT32 TxPreN:6 ; ///< |
| 5827 | UINT32 TxPreP:6 ; ///< |
| 5828 | UINT32 Reserved_31_12:20; ///< |
| 5829 | } Field; ///< |
| 5830 | UINT32 Value; ///< |
| 5831 | } D18F2x09C_x0D0F_0106_STRUCT; |
| 5832 | |
| 5833 | // **** D18F2x09C_x0D0F_010A Register Definition **** |
| 5834 | // Address |
| 5835 | #define D18F2x09C_x0D0F_010A_ADDRESS 0xd0f010a |
| 5836 | |
| 5837 | // Type |
| 5838 | #define D18F2x09C_x0D0F_010A_TYPE TYPE_D18F2x09C |
| 5839 | // Field Data |
| 5840 | #define D18F2x09C_x0D0F_010A_TxPreN_OFFSET 0 |
| 5841 | #define D18F2x09C_x0D0F_010A_TxPreN_WIDTH 6 |
| 5842 | #define D18F2x09C_x0D0F_010A_TxPreN_MASK 0x3f |
| 5843 | #define D18F2x09C_x0D0F_010A_TxPreP_OFFSET 6 |
| 5844 | #define D18F2x09C_x0D0F_010A_TxPreP_WIDTH 6 |
| 5845 | #define D18F2x09C_x0D0F_010A_TxPreP_MASK 0xfc0 |
| 5846 | #define D18F2x09C_x0D0F_010A_Reserved_31_12_OFFSET 12 |
| 5847 | #define D18F2x09C_x0D0F_010A_Reserved_31_12_WIDTH 20 |
| 5848 | #define D18F2x09C_x0D0F_010A_Reserved_31_12_MASK 0xfffff000 |
| 5849 | |
| 5850 | /// D18F2x09C_x0D0F_010A |
| 5851 | typedef union { |
| 5852 | struct { ///< |
| 5853 | UINT32 TxPreN:6 ; ///< |
| 5854 | UINT32 TxPreP:6 ; ///< |
| 5855 | UINT32 Reserved_31_12:20; ///< |
| 5856 | } Field; ///< |
| 5857 | UINT32 Value; ///< |
| 5858 | } D18F2x09C_x0D0F_010A_STRUCT; |
| 5859 | |
| 5860 | // **** D18F2x09C_x0D0F_010F Register Definition **** |
| 5861 | // Address |
| 5862 | #define D18F2x09C_x0D0F_010F_ADDRESS 0xd0f010f |
| 5863 | |
| 5864 | // Type |
| 5865 | #define D18F2x09C_x0D0F_010F_TYPE TYPE_D18F2x09C |
| 5866 | // Field Data |
| 5867 | #define D18F2x09C_x0D0F_010F_Reserved_11_0_OFFSET 0 |
| 5868 | #define D18F2x09C_x0D0F_010F_Reserved_11_0_WIDTH 12 |
| 5869 | #define D18F2x09C_x0D0F_010F_Reserved_11_0_MASK 0xfff |
| 5870 | #define D18F2x09C_x0D0F_010F_AlwaysEnDllClks_OFFSET 12 |
| 5871 | #define D18F2x09C_x0D0F_010F_AlwaysEnDllClks_WIDTH 3 |
| 5872 | #define D18F2x09C_x0D0F_010F_AlwaysEnDllClks_MASK 0x7000 |
| 5873 | #define D18F2x09C_x0D0F_010F_Reserved_31_15_OFFSET 15 |
| 5874 | #define D18F2x09C_x0D0F_010F_Reserved_31_15_WIDTH 17 |
| 5875 | #define D18F2x09C_x0D0F_010F_Reserved_31_15_MASK 0xffff8000 |
| 5876 | |
| 5877 | /// D18F2x09C_x0D0F_010F |
| 5878 | typedef union { |
| 5879 | struct { ///< |
| 5880 | UINT32 Reserved_11_0:12; ///< |
| 5881 | UINT32 AlwaysEnDllClks:3 ; ///< |
| 5882 | UINT32 Reserved_31_15:17; ///< |
| 5883 | } Field; ///< |
| 5884 | UINT32 Value; ///< |
| 5885 | } D18F2x09C_x0D0F_010F_STRUCT; |
| 5886 | |
| 5887 | // **** D18F2x09C_x0D0F_0110 Register Definition **** |
| 5888 | // Address |
| 5889 | #define D18F2x09C_x0D0F_0110_ADDRESS 0xd0f0110 |
| 5890 | |
| 5891 | // Type |
| 5892 | #define D18F2x09C_x0D0F_0110_TYPE TYPE_D18F2x09C |
| 5893 | // Field Data |
| 5894 | #define D18F2x09C_x0D0F_0110_Reserved_11_0_OFFSET 0 |
| 5895 | #define D18F2x09C_x0D0F_0110_Reserved_11_0_WIDTH 12 |
| 5896 | #define D18F2x09C_x0D0F_0110_Reserved_11_0_MASK 0xfff |
| 5897 | #define D18F2x09C_x0D0F_0110_EnRxPadStandby_OFFSET 12 |
| 5898 | #define D18F2x09C_x0D0F_0110_EnRxPadStandby_WIDTH 1 |
| 5899 | #define D18F2x09C_x0D0F_0110_EnRxPadStandby_MASK 0x1000 |
| 5900 | #define D18F2x09C_x0D0F_0110_Reserved_31_13_OFFSET 13 |
| 5901 | #define D18F2x09C_x0D0F_0110_Reserved_31_13_WIDTH 19 |
| 5902 | #define D18F2x09C_x0D0F_0110_Reserved_31_13_MASK 0xffffe000 |
| 5903 | |
| 5904 | /// D18F2x09C_x0D0F_0110 |
| 5905 | typedef union { |
| 5906 | struct { ///< |
| 5907 | UINT32 Reserved_11_0:12; ///< |
| 5908 | UINT32 EnRxPadStandby:1 ; ///< |
| 5909 | UINT32 Reserved_31_13:19; ///< |
| 5910 | } Field; ///< |
| 5911 | UINT32 Value; ///< |
| 5912 | } D18F2x09C_x0D0F_0110_STRUCT; |
| 5913 | |
| 5914 | // **** D18F2x09C_x0D0F_011F Register Definition **** |
| 5915 | // Address |
| 5916 | #define D18F2x09C_x0D0F_011F_ADDRESS 0xd0f011f |
| 5917 | |
| 5918 | // Type |
| 5919 | #define D18F2x09C_x0D0F_011F_TYPE TYPE_D18F2x09C |
| 5920 | // Field Data |
| 5921 | #define D18F2x09C_x0D0F_011F_Reserved_2_0_OFFSET 0 |
| 5922 | #define D18F2x09C_x0D0F_011F_Reserved_2_0_WIDTH 3 |
| 5923 | #define D18F2x09C_x0D0F_011F_Reserved_2_0_MASK 0x7 |
| 5924 | #define D18F2x09C_x0D0F_011F_RxVioLvl_OFFSET 3 |
| 5925 | #define D18F2x09C_x0D0F_011F_RxVioLvl_WIDTH 2 |
| 5926 | #define D18F2x09C_x0D0F_011F_RxVioLvl_MASK 0x18 |
| 5927 | #define D18F2x09C_x0D0F_011F_Reserved_31_5_OFFSET 5 |
| 5928 | #define D18F2x09C_x0D0F_011F_Reserved_31_5_WIDTH 27 |
| 5929 | #define D18F2x09C_x0D0F_011F_Reserved_31_5_MASK 0xffffffe0 |
| 5930 | |
| 5931 | /// D18F2x09C_x0D0F_011F |
| 5932 | typedef union { |
| 5933 | struct { ///< |
| 5934 | UINT32 Reserved_2_0:3 ; ///< |
| 5935 | UINT32 RxVioLvl:2 ; ///< |
| 5936 | UINT32 Reserved_31_5:27; ///< |
| 5937 | } Field; ///< |
| 5938 | UINT32 Value; ///< |
| 5939 | } D18F2x09C_x0D0F_011F_STRUCT; |
| 5940 | |
| 5941 | |
| 5942 | |
| 5943 | // **** D18F2x09C_x0D0F_0202 Register Definition **** |
| 5944 | // Address |
| 5945 | #define D18F2x09C_x0D0F_0202_ADDRESS 0xd0f0202 |
| 5946 | |
| 5947 | // Type |
| 5948 | #define D18F2x09C_x0D0F_0202_TYPE TYPE_D18F2x09C |
| 5949 | // Field Data |
| 5950 | #define D18F2x09C_x0D0F_0202_TxPreN_OFFSET 0 |
| 5951 | #define D18F2x09C_x0D0F_0202_TxPreN_WIDTH 6 |
| 5952 | #define D18F2x09C_x0D0F_0202_TxPreN_MASK 0x3f |
| 5953 | #define D18F2x09C_x0D0F_0202_TxPreP_OFFSET 6 |
| 5954 | #define D18F2x09C_x0D0F_0202_TxPreP_WIDTH 6 |
| 5955 | #define D18F2x09C_x0D0F_0202_TxPreP_MASK 0xfc0 |
| 5956 | #define D18F2x09C_x0D0F_0202_Reserved_14_12_OFFSET 12 |
| 5957 | #define D18F2x09C_x0D0F_0202_Reserved_14_12_WIDTH 3 |
| 5958 | #define D18F2x09C_x0D0F_0202_Reserved_14_12_MASK 0x7000 |
| 5959 | #define D18F2x09C_x0D0F_0202_ValidTxAndPre_OFFSET 15 |
| 5960 | #define D18F2x09C_x0D0F_0202_ValidTxAndPre_WIDTH 1 |
| 5961 | #define D18F2x09C_x0D0F_0202_ValidTxAndPre_MASK 0x8000 |
| 5962 | #define D18F2x09C_x0D0F_0202_Reserved_31_16_OFFSET 16 |
| 5963 | #define D18F2x09C_x0D0F_0202_Reserved_31_16_WIDTH 16 |
| 5964 | #define D18F2x09C_x0D0F_0202_Reserved_31_16_MASK 0xffff0000 |
| 5965 | |
| 5966 | /// D18F2x09C_x0D0F_0202 |
| 5967 | typedef union { |
| 5968 | struct { ///< |
| 5969 | UINT32 TxPreN:6 ; ///< |
| 5970 | UINT32 TxPreP:6 ; ///< |
| 5971 | UINT32 Reserved_14_12:3 ; ///< |
| 5972 | UINT32 ValidTxAndPre:1 ; ///< |
| 5973 | UINT32 Reserved_31_16:16; ///< |
| 5974 | } Field; ///< |
| 5975 | UINT32 Value; ///< |
| 5976 | } D18F2x09C_x0D0F_0202_STRUCT; |
| 5977 | |
| 5978 | // **** D18F2x09C_x0D0F_0206 Register Definition **** |
| 5979 | // Address |
| 5980 | #define D18F2x09C_x0D0F_0206_ADDRESS 0xd0f0206 |
| 5981 | |
| 5982 | // Type |
| 5983 | #define D18F2x09C_x0D0F_0206_TYPE TYPE_D18F2x09C |
| 5984 | // Field Data |
| 5985 | #define D18F2x09C_x0D0F_0206_TxPreN_OFFSET 0 |
| 5986 | #define D18F2x09C_x0D0F_0206_TxPreN_WIDTH 6 |
| 5987 | #define D18F2x09C_x0D0F_0206_TxPreN_MASK 0x3f |
| 5988 | #define D18F2x09C_x0D0F_0206_TxPreP_OFFSET 6 |
| 5989 | #define D18F2x09C_x0D0F_0206_TxPreP_WIDTH 6 |
| 5990 | #define D18F2x09C_x0D0F_0206_TxPreP_MASK 0xfc0 |
| 5991 | #define D18F2x09C_x0D0F_0206_Reserved_31_12_OFFSET 12 |
| 5992 | #define D18F2x09C_x0D0F_0206_Reserved_31_12_WIDTH 20 |
| 5993 | #define D18F2x09C_x0D0F_0206_Reserved_31_12_MASK 0xfffff000 |
| 5994 | |
| 5995 | /// D18F2x09C_x0D0F_0206 |
| 5996 | typedef union { |
| 5997 | struct { ///< |
| 5998 | UINT32 TxPreN:6 ; ///< |
| 5999 | UINT32 TxPreP:6 ; ///< |
| 6000 | UINT32 Reserved_31_12:20; ///< |
| 6001 | } Field; ///< |
| 6002 | UINT32 Value; ///< |
| 6003 | } D18F2x09C_x0D0F_0206_STRUCT; |
| 6004 | |
| 6005 | // **** D18F2x09C_x0D0F_020A Register Definition **** |
| 6006 | // Address |
| 6007 | #define D18F2x09C_x0D0F_020A_ADDRESS 0xd0f020a |
| 6008 | |
| 6009 | // Type |
| 6010 | #define D18F2x09C_x0D0F_020A_TYPE TYPE_D18F2x09C |
| 6011 | // Field Data |
| 6012 | #define D18F2x09C_x0D0F_020A_TxPreN_OFFSET 0 |
| 6013 | #define D18F2x09C_x0D0F_020A_TxPreN_WIDTH 6 |
| 6014 | #define D18F2x09C_x0D0F_020A_TxPreN_MASK 0x3f |
| 6015 | #define D18F2x09C_x0D0F_020A_TxPreP_OFFSET 6 |
| 6016 | #define D18F2x09C_x0D0F_020A_TxPreP_WIDTH 6 |
| 6017 | #define D18F2x09C_x0D0F_020A_TxPreP_MASK 0xfc0 |
| 6018 | #define D18F2x09C_x0D0F_020A_Reserved_31_12_OFFSET 12 |
| 6019 | #define D18F2x09C_x0D0F_020A_Reserved_31_12_WIDTH 20 |
| 6020 | #define D18F2x09C_x0D0F_020A_Reserved_31_12_MASK 0xfffff000 |
| 6021 | |
| 6022 | /// D18F2x09C_x0D0F_020A |
| 6023 | typedef union { |
| 6024 | struct { ///< |
| 6025 | UINT32 TxPreN:6 ; ///< |
| 6026 | UINT32 TxPreP:6 ; ///< |
| 6027 | UINT32 Reserved_31_12:20; ///< |
| 6028 | } Field; ///< |
| 6029 | UINT32 Value; ///< |
| 6030 | } D18F2x09C_x0D0F_020A_STRUCT; |
| 6031 | |
| 6032 | // **** D18F2x09C_x0D0F_020F Register Definition **** |
| 6033 | // Address |
| 6034 | #define D18F2x09C_x0D0F_020F_ADDRESS 0xd0f020f |
| 6035 | |
| 6036 | // Type |
| 6037 | #define D18F2x09C_x0D0F_020F_TYPE TYPE_D18F2x09C |
| 6038 | // Field Data |
| 6039 | #define D18F2x09C_x0D0F_020F_Reserved_11_0_OFFSET 0 |
| 6040 | #define D18F2x09C_x0D0F_020F_Reserved_11_0_WIDTH 12 |
| 6041 | #define D18F2x09C_x0D0F_020F_Reserved_11_0_MASK 0xfff |
| 6042 | #define D18F2x09C_x0D0F_020F_AlwaysEnDllClks_OFFSET 12 |
| 6043 | #define D18F2x09C_x0D0F_020F_AlwaysEnDllClks_WIDTH 3 |
| 6044 | #define D18F2x09C_x0D0F_020F_AlwaysEnDllClks_MASK 0x7000 |
| 6045 | #define D18F2x09C_x0D0F_020F_Reserved_31_15_OFFSET 15 |
| 6046 | #define D18F2x09C_x0D0F_020F_Reserved_31_15_WIDTH 17 |
| 6047 | #define D18F2x09C_x0D0F_020F_Reserved_31_15_MASK 0xffff8000 |
| 6048 | |
| 6049 | /// D18F2x09C_x0D0F_020F |
| 6050 | typedef union { |
| 6051 | struct { ///< |
| 6052 | UINT32 Reserved_11_0:12; ///< |
| 6053 | UINT32 AlwaysEnDllClks:3 ; ///< |
| 6054 | UINT32 Reserved_31_15:17; ///< |
| 6055 | } Field; ///< |
| 6056 | UINT32 Value; ///< |
| 6057 | } D18F2x09C_x0D0F_020F_STRUCT; |
| 6058 | |
| 6059 | // **** D18F2x09C_x0D0F_0210 Register Definition **** |
| 6060 | // Address |
| 6061 | #define D18F2x09C_x0D0F_0210_ADDRESS 0xd0f0210 |
| 6062 | |
| 6063 | // Type |
| 6064 | #define D18F2x09C_x0D0F_0210_TYPE TYPE_D18F2x09C |
| 6065 | // Field Data |
| 6066 | #define D18F2x09C_x0D0F_0210_Reserved_11_0_OFFSET 0 |
| 6067 | #define D18F2x09C_x0D0F_0210_Reserved_11_0_WIDTH 12 |
| 6068 | #define D18F2x09C_x0D0F_0210_Reserved_11_0_MASK 0xfff |
| 6069 | #define D18F2x09C_x0D0F_0210_EnRxPadStandby_OFFSET 12 |
| 6070 | #define D18F2x09C_x0D0F_0210_EnRxPadStandby_WIDTH 1 |
| 6071 | #define D18F2x09C_x0D0F_0210_EnRxPadStandby_MASK 0x1000 |
| 6072 | #define D18F2x09C_x0D0F_0210_Reserved_31_13_OFFSET 13 |
| 6073 | #define D18F2x09C_x0D0F_0210_Reserved_31_13_WIDTH 19 |
| 6074 | #define D18F2x09C_x0D0F_0210_Reserved_31_13_MASK 0xffffe000 |
| 6075 | |
| 6076 | /// D18F2x09C_x0D0F_0210 |
| 6077 | typedef union { |
| 6078 | struct { ///< |
| 6079 | UINT32 Reserved_11_0:12; ///< |
| 6080 | UINT32 EnRxPadStandby:1 ; ///< |
| 6081 | UINT32 Reserved_31_13:19; ///< |
| 6082 | } Field; ///< |
| 6083 | UINT32 Value; ///< |
| 6084 | } D18F2x09C_x0D0F_0210_STRUCT; |
| 6085 | |
| 6086 | // **** D18F2x09C_x0D0F_021F Register Definition **** |
| 6087 | // Address |
| 6088 | #define D18F2x09C_x0D0F_021F_ADDRESS 0xd0f021f |
| 6089 | |
| 6090 | // Type |
| 6091 | #define D18F2x09C_x0D0F_021F_TYPE TYPE_D18F2x09C |
| 6092 | // Field Data |
| 6093 | #define D18F2x09C_x0D0F_021F_Reserved_2_0_OFFSET 0 |
| 6094 | #define D18F2x09C_x0D0F_021F_Reserved_2_0_WIDTH 3 |
| 6095 | #define D18F2x09C_x0D0F_021F_Reserved_2_0_MASK 0x7 |
| 6096 | #define D18F2x09C_x0D0F_021F_RxVioLvl_OFFSET 3 |
| 6097 | #define D18F2x09C_x0D0F_021F_RxVioLvl_WIDTH 2 |
| 6098 | #define D18F2x09C_x0D0F_021F_RxVioLvl_MASK 0x18 |
| 6099 | #define D18F2x09C_x0D0F_021F_Reserved_31_5_OFFSET 5 |
| 6100 | #define D18F2x09C_x0D0F_021F_Reserved_31_5_WIDTH 27 |
| 6101 | #define D18F2x09C_x0D0F_021F_Reserved_31_5_MASK 0xffffffe0 |
| 6102 | |
| 6103 | /// D18F2x09C_x0D0F_021F |
| 6104 | typedef union { |
| 6105 | struct { ///< |
| 6106 | UINT32 Reserved_2_0:3 ; ///< |
| 6107 | UINT32 RxVioLvl:2 ; ///< |
| 6108 | UINT32 Reserved_31_5:27; ///< |
| 6109 | } Field; ///< |
| 6110 | UINT32 Value; ///< |
| 6111 | } D18F2x09C_x0D0F_021F_STRUCT; |
| 6112 | |
| 6113 | |
| 6114 | |
| 6115 | // **** D18F2x09C_x0D0F_0302 Register Definition **** |
| 6116 | // Address |
| 6117 | #define D18F2x09C_x0D0F_0302_ADDRESS 0xd0f0302 |
| 6118 | |
| 6119 | // Type |
| 6120 | #define D18F2x09C_x0D0F_0302_TYPE TYPE_D18F2x09C |
| 6121 | // Field Data |
| 6122 | #define D18F2x09C_x0D0F_0302_TxPreN_OFFSET 0 |
| 6123 | #define D18F2x09C_x0D0F_0302_TxPreN_WIDTH 6 |
| 6124 | #define D18F2x09C_x0D0F_0302_TxPreN_MASK 0x3f |
| 6125 | #define D18F2x09C_x0D0F_0302_TxPreP_OFFSET 6 |
| 6126 | #define D18F2x09C_x0D0F_0302_TxPreP_WIDTH 6 |
| 6127 | #define D18F2x09C_x0D0F_0302_TxPreP_MASK 0xfc0 |
| 6128 | #define D18F2x09C_x0D0F_0302_Reserved_14_12_OFFSET 12 |
| 6129 | #define D18F2x09C_x0D0F_0302_Reserved_14_12_WIDTH 3 |
| 6130 | #define D18F2x09C_x0D0F_0302_Reserved_14_12_MASK 0x7000 |
| 6131 | #define D18F2x09C_x0D0F_0302_ValidTxAndPre_OFFSET 15 |
| 6132 | #define D18F2x09C_x0D0F_0302_ValidTxAndPre_WIDTH 1 |
| 6133 | #define D18F2x09C_x0D0F_0302_ValidTxAndPre_MASK 0x8000 |
| 6134 | #define D18F2x09C_x0D0F_0302_Reserved_31_16_OFFSET 16 |
| 6135 | #define D18F2x09C_x0D0F_0302_Reserved_31_16_WIDTH 16 |
| 6136 | #define D18F2x09C_x0D0F_0302_Reserved_31_16_MASK 0xffff0000 |
| 6137 | |
| 6138 | /// D18F2x09C_x0D0F_0302 |
| 6139 | typedef union { |
| 6140 | struct { ///< |
| 6141 | UINT32 TxPreN:6 ; ///< |
| 6142 | UINT32 TxPreP:6 ; ///< |
| 6143 | UINT32 Reserved_14_12:3 ; ///< |
| 6144 | UINT32 ValidTxAndPre:1 ; ///< |
| 6145 | UINT32 Reserved_31_16:16; ///< |
| 6146 | } Field; ///< |
| 6147 | UINT32 Value; ///< |
| 6148 | } D18F2x09C_x0D0F_0302_STRUCT; |
| 6149 | |
| 6150 | // **** D18F2x09C_x0D0F_0306 Register Definition **** |
| 6151 | // Address |
| 6152 | #define D18F2x09C_x0D0F_0306_ADDRESS 0xd0f0306 |
| 6153 | |
| 6154 | // Type |
| 6155 | #define D18F2x09C_x0D0F_0306_TYPE TYPE_D18F2x09C |
| 6156 | // Field Data |
| 6157 | #define D18F2x09C_x0D0F_0306_TxPreN_OFFSET 0 |
| 6158 | #define D18F2x09C_x0D0F_0306_TxPreN_WIDTH 6 |
| 6159 | #define D18F2x09C_x0D0F_0306_TxPreN_MASK 0x3f |
| 6160 | #define D18F2x09C_x0D0F_0306_TxPreP_OFFSET 6 |
| 6161 | #define D18F2x09C_x0D0F_0306_TxPreP_WIDTH 6 |
| 6162 | #define D18F2x09C_x0D0F_0306_TxPreP_MASK 0xfc0 |
| 6163 | #define D18F2x09C_x0D0F_0306_Reserved_31_12_OFFSET 12 |
| 6164 | #define D18F2x09C_x0D0F_0306_Reserved_31_12_WIDTH 20 |
| 6165 | #define D18F2x09C_x0D0F_0306_Reserved_31_12_MASK 0xfffff000 |
| 6166 | |
| 6167 | /// D18F2x09C_x0D0F_0306 |
| 6168 | typedef union { |
| 6169 | struct { ///< |
| 6170 | UINT32 TxPreN:6 ; ///< |
| 6171 | UINT32 TxPreP:6 ; ///< |
| 6172 | UINT32 Reserved_31_12:20; ///< |
| 6173 | } Field; ///< |
| 6174 | UINT32 Value; ///< |
| 6175 | } D18F2x09C_x0D0F_0306_STRUCT; |
| 6176 | |
| 6177 | // **** D18F2x09C_x0D0F_030A Register Definition **** |
| 6178 | // Address |
| 6179 | #define D18F2x09C_x0D0F_030A_ADDRESS 0xd0f030a |
| 6180 | |
| 6181 | // Type |
| 6182 | #define D18F2x09C_x0D0F_030A_TYPE TYPE_D18F2x09C |
| 6183 | // Field Data |
| 6184 | #define D18F2x09C_x0D0F_030A_TxPreN_OFFSET 0 |
| 6185 | #define D18F2x09C_x0D0F_030A_TxPreN_WIDTH 6 |
| 6186 | #define D18F2x09C_x0D0F_030A_TxPreN_MASK 0x3f |
| 6187 | #define D18F2x09C_x0D0F_030A_TxPreP_OFFSET 6 |
| 6188 | #define D18F2x09C_x0D0F_030A_TxPreP_WIDTH 6 |
| 6189 | #define D18F2x09C_x0D0F_030A_TxPreP_MASK 0xfc0 |
| 6190 | #define D18F2x09C_x0D0F_030A_Reserved_31_12_OFFSET 12 |
| 6191 | #define D18F2x09C_x0D0F_030A_Reserved_31_12_WIDTH 20 |
| 6192 | #define D18F2x09C_x0D0F_030A_Reserved_31_12_MASK 0xfffff000 |
| 6193 | |
| 6194 | /// D18F2x09C_x0D0F_030A |
| 6195 | typedef union { |
| 6196 | struct { ///< |
| 6197 | UINT32 TxPreN:6 ; ///< |
| 6198 | UINT32 TxPreP:6 ; ///< |
| 6199 | UINT32 Reserved_31_12:20; ///< |
| 6200 | } Field; ///< |
| 6201 | UINT32 Value; ///< |
| 6202 | } D18F2x09C_x0D0F_030A_STRUCT; |
| 6203 | |
| 6204 | // **** D18F2x09C_x0D0F_030F Register Definition **** |
| 6205 | // Address |
| 6206 | #define D18F2x09C_x0D0F_030F_ADDRESS 0xd0f030f |
| 6207 | |
| 6208 | // Type |
| 6209 | #define D18F2x09C_x0D0F_030F_TYPE TYPE_D18F2x09C |
| 6210 | // Field Data |
| 6211 | #define D18F2x09C_x0D0F_030F_Reserved_11_0_OFFSET 0 |
| 6212 | #define D18F2x09C_x0D0F_030F_Reserved_11_0_WIDTH 12 |
| 6213 | #define D18F2x09C_x0D0F_030F_Reserved_11_0_MASK 0xfff |
| 6214 | #define D18F2x09C_x0D0F_030F_AlwaysEnDllClks_OFFSET 12 |
| 6215 | #define D18F2x09C_x0D0F_030F_AlwaysEnDllClks_WIDTH 3 |
| 6216 | #define D18F2x09C_x0D0F_030F_AlwaysEnDllClks_MASK 0x7000 |
| 6217 | #define D18F2x09C_x0D0F_030F_Reserved_31_15_OFFSET 15 |
| 6218 | #define D18F2x09C_x0D0F_030F_Reserved_31_15_WIDTH 17 |
| 6219 | #define D18F2x09C_x0D0F_030F_Reserved_31_15_MASK 0xffff8000 |
| 6220 | |
| 6221 | /// D18F2x09C_x0D0F_030F |
| 6222 | typedef union { |
| 6223 | struct { ///< |
| 6224 | UINT32 Reserved_11_0:12; ///< |
| 6225 | UINT32 AlwaysEnDllClks:3 ; ///< |
| 6226 | UINT32 Reserved_31_15:17; ///< |
| 6227 | } Field; ///< |
| 6228 | UINT32 Value; ///< |
| 6229 | } D18F2x09C_x0D0F_030F_STRUCT; |
| 6230 | |
| 6231 | // **** D18F2x09C_x0D0F_0310 Register Definition **** |
| 6232 | // Address |
| 6233 | #define D18F2x09C_x0D0F_0310_ADDRESS 0xd0f0310 |
| 6234 | |
| 6235 | // Type |
| 6236 | #define D18F2x09C_x0D0F_0310_TYPE TYPE_D18F2x09C |
| 6237 | // Field Data |
| 6238 | #define D18F2x09C_x0D0F_0310_Reserved_11_0_OFFSET 0 |
| 6239 | #define D18F2x09C_x0D0F_0310_Reserved_11_0_WIDTH 12 |
| 6240 | #define D18F2x09C_x0D0F_0310_Reserved_11_0_MASK 0xfff |
| 6241 | #define D18F2x09C_x0D0F_0310_EnRxPadStandby_OFFSET 12 |
| 6242 | #define D18F2x09C_x0D0F_0310_EnRxPadStandby_WIDTH 1 |
| 6243 | #define D18F2x09C_x0D0F_0310_EnRxPadStandby_MASK 0x1000 |
| 6244 | #define D18F2x09C_x0D0F_0310_Reserved_31_13_OFFSET 13 |
| 6245 | #define D18F2x09C_x0D0F_0310_Reserved_31_13_WIDTH 19 |
| 6246 | #define D18F2x09C_x0D0F_0310_Reserved_31_13_MASK 0xffffe000 |
| 6247 | |
| 6248 | /// D18F2x09C_x0D0F_0310 |
| 6249 | typedef union { |
| 6250 | struct { ///< |
| 6251 | UINT32 Reserved_11_0:12; ///< |
| 6252 | UINT32 EnRxPadStandby:1 ; ///< |
| 6253 | UINT32 Reserved_31_13:19; ///< |
| 6254 | } Field; ///< |
| 6255 | UINT32 Value; ///< |
| 6256 | } D18F2x09C_x0D0F_0310_STRUCT; |
| 6257 | |
| 6258 | // **** D18F2x09C_x0D0F_031F Register Definition **** |
| 6259 | // Address |
| 6260 | #define D18F2x09C_x0D0F_031F_ADDRESS 0xd0f031f |
| 6261 | |
| 6262 | // Type |
| 6263 | #define D18F2x09C_x0D0F_031F_TYPE TYPE_D18F2x09C |
| 6264 | // Field Data |
| 6265 | #define D18F2x09C_x0D0F_031F_Reserved_2_0_OFFSET 0 |
| 6266 | #define D18F2x09C_x0D0F_031F_Reserved_2_0_WIDTH 3 |
| 6267 | #define D18F2x09C_x0D0F_031F_Reserved_2_0_MASK 0x7 |
| 6268 | #define D18F2x09C_x0D0F_031F_RxVioLvl_OFFSET 3 |
| 6269 | #define D18F2x09C_x0D0F_031F_RxVioLvl_WIDTH 2 |
| 6270 | #define D18F2x09C_x0D0F_031F_RxVioLvl_MASK 0x18 |
| 6271 | #define D18F2x09C_x0D0F_031F_Reserved_31_5_OFFSET 5 |
| 6272 | #define D18F2x09C_x0D0F_031F_Reserved_31_5_WIDTH 27 |
| 6273 | #define D18F2x09C_x0D0F_031F_Reserved_31_5_MASK 0xffffffe0 |
| 6274 | |
| 6275 | /// D18F2x09C_x0D0F_031F |
| 6276 | typedef union { |
| 6277 | struct { ///< |
| 6278 | UINT32 Reserved_2_0:3 ; ///< |
| 6279 | UINT32 RxVioLvl:2 ; ///< |
| 6280 | UINT32 Reserved_31_5:27; ///< |
| 6281 | } Field; ///< |
| 6282 | UINT32 Value; ///< |
| 6283 | } D18F2x09C_x0D0F_031F_STRUCT; |
| 6284 | |
| 6285 | |
| 6286 | |
| 6287 | // **** D18F2x09C_x0D0F_0402 Register Definition **** |
| 6288 | // Address |
| 6289 | #define D18F2x09C_x0D0F_0402_ADDRESS 0xd0f0402 |
| 6290 | |
| 6291 | // Type |
| 6292 | #define D18F2x09C_x0D0F_0402_TYPE TYPE_D18F2x09C |
| 6293 | // Field Data |
| 6294 | #define D18F2x09C_x0D0F_0402_TxPreN_OFFSET 0 |
| 6295 | #define D18F2x09C_x0D0F_0402_TxPreN_WIDTH 6 |
| 6296 | #define D18F2x09C_x0D0F_0402_TxPreN_MASK 0x3f |
| 6297 | #define D18F2x09C_x0D0F_0402_TxPreP_OFFSET 6 |
| 6298 | #define D18F2x09C_x0D0F_0402_TxPreP_WIDTH 6 |
| 6299 | #define D18F2x09C_x0D0F_0402_TxPreP_MASK 0xfc0 |
| 6300 | #define D18F2x09C_x0D0F_0402_Reserved_14_12_OFFSET 12 |
| 6301 | #define D18F2x09C_x0D0F_0402_Reserved_14_12_WIDTH 3 |
| 6302 | #define D18F2x09C_x0D0F_0402_Reserved_14_12_MASK 0x7000 |
| 6303 | #define D18F2x09C_x0D0F_0402_ValidTxAndPre_OFFSET 15 |
| 6304 | #define D18F2x09C_x0D0F_0402_ValidTxAndPre_WIDTH 1 |
| 6305 | #define D18F2x09C_x0D0F_0402_ValidTxAndPre_MASK 0x8000 |
| 6306 | #define D18F2x09C_x0D0F_0402_Reserved_31_16_OFFSET 16 |
| 6307 | #define D18F2x09C_x0D0F_0402_Reserved_31_16_WIDTH 16 |
| 6308 | #define D18F2x09C_x0D0F_0402_Reserved_31_16_MASK 0xffff0000 |
| 6309 | |
| 6310 | /// D18F2x09C_x0D0F_0402 |
| 6311 | typedef union { |
| 6312 | struct { ///< |
| 6313 | UINT32 TxPreN:6 ; ///< |
| 6314 | UINT32 TxPreP:6 ; ///< |
| 6315 | UINT32 Reserved_14_12:3 ; ///< |
| 6316 | UINT32 ValidTxAndPre:1 ; ///< |
| 6317 | UINT32 Reserved_31_16:16; ///< |
| 6318 | } Field; ///< |
| 6319 | UINT32 Value; ///< |
| 6320 | } D18F2x09C_x0D0F_0402_STRUCT; |
| 6321 | |
| 6322 | // **** D18F2x09C_x0D0F_0406 Register Definition **** |
| 6323 | // Address |
| 6324 | #define D18F2x09C_x0D0F_0406_ADDRESS 0xd0f0406 |
| 6325 | |
| 6326 | // Type |
| 6327 | #define D18F2x09C_x0D0F_0406_TYPE TYPE_D18F2x09C |
| 6328 | // Field Data |
| 6329 | #define D18F2x09C_x0D0F_0406_TxPreN_OFFSET 0 |
| 6330 | #define D18F2x09C_x0D0F_0406_TxPreN_WIDTH 6 |
| 6331 | #define D18F2x09C_x0D0F_0406_TxPreN_MASK 0x3f |
| 6332 | #define D18F2x09C_x0D0F_0406_TxPreP_OFFSET 6 |
| 6333 | #define D18F2x09C_x0D0F_0406_TxPreP_WIDTH 6 |
| 6334 | #define D18F2x09C_x0D0F_0406_TxPreP_MASK 0xfc0 |
| 6335 | #define D18F2x09C_x0D0F_0406_Reserved_31_12_OFFSET 12 |
| 6336 | #define D18F2x09C_x0D0F_0406_Reserved_31_12_WIDTH 20 |
| 6337 | #define D18F2x09C_x0D0F_0406_Reserved_31_12_MASK 0xfffff000 |
| 6338 | |
| 6339 | /// D18F2x09C_x0D0F_0406 |
| 6340 | typedef union { |
| 6341 | struct { ///< |
| 6342 | UINT32 TxPreN:6 ; ///< |
| 6343 | UINT32 TxPreP:6 ; ///< |
| 6344 | UINT32 Reserved_31_12:20; ///< |
| 6345 | } Field; ///< |
| 6346 | UINT32 Value; ///< |
| 6347 | } D18F2x09C_x0D0F_0406_STRUCT; |
| 6348 | |
| 6349 | // **** D18F2x09C_x0D0F_040A Register Definition **** |
| 6350 | // Address |
| 6351 | #define D18F2x09C_x0D0F_040A_ADDRESS 0xd0f040a |
| 6352 | |
| 6353 | // Type |
| 6354 | #define D18F2x09C_x0D0F_040A_TYPE TYPE_D18F2x09C |
| 6355 | // Field Data |
| 6356 | #define D18F2x09C_x0D0F_040A_TxPreN_OFFSET 0 |
| 6357 | #define D18F2x09C_x0D0F_040A_TxPreN_WIDTH 6 |
| 6358 | #define D18F2x09C_x0D0F_040A_TxPreN_MASK 0x3f |
| 6359 | #define D18F2x09C_x0D0F_040A_TxPreP_OFFSET 6 |
| 6360 | #define D18F2x09C_x0D0F_040A_TxPreP_WIDTH 6 |
| 6361 | #define D18F2x09C_x0D0F_040A_TxPreP_MASK 0xfc0 |
| 6362 | #define D18F2x09C_x0D0F_040A_Reserved_31_12_OFFSET 12 |
| 6363 | #define D18F2x09C_x0D0F_040A_Reserved_31_12_WIDTH 20 |
| 6364 | #define D18F2x09C_x0D0F_040A_Reserved_31_12_MASK 0xfffff000 |
| 6365 | |
| 6366 | /// D18F2x09C_x0D0F_040A |
| 6367 | typedef union { |
| 6368 | struct { ///< |
| 6369 | UINT32 TxPreN:6 ; ///< |
| 6370 | UINT32 TxPreP:6 ; ///< |
| 6371 | UINT32 Reserved_31_12:20; ///< |
| 6372 | } Field; ///< |
| 6373 | UINT32 Value; ///< |
| 6374 | } D18F2x09C_x0D0F_040A_STRUCT; |
| 6375 | |
| 6376 | // **** D18F2x09C_x0D0F_040F Register Definition **** |
| 6377 | // Address |
| 6378 | #define D18F2x09C_x0D0F_040F_ADDRESS 0xd0f040f |
| 6379 | |
| 6380 | // Type |
| 6381 | #define D18F2x09C_x0D0F_040F_TYPE TYPE_D18F2x09C |
| 6382 | // Field Data |
| 6383 | #define D18F2x09C_x0D0F_040F_Reserved_11_0_OFFSET 0 |
| 6384 | #define D18F2x09C_x0D0F_040F_Reserved_11_0_WIDTH 12 |
| 6385 | #define D18F2x09C_x0D0F_040F_Reserved_11_0_MASK 0xfff |
| 6386 | #define D18F2x09C_x0D0F_040F_AlwaysEnDllClks_OFFSET 12 |
| 6387 | #define D18F2x09C_x0D0F_040F_AlwaysEnDllClks_WIDTH 3 |
| 6388 | #define D18F2x09C_x0D0F_040F_AlwaysEnDllClks_MASK 0x7000 |
| 6389 | #define D18F2x09C_x0D0F_040F_Reserved_31_15_OFFSET 15 |
| 6390 | #define D18F2x09C_x0D0F_040F_Reserved_31_15_WIDTH 17 |
| 6391 | #define D18F2x09C_x0D0F_040F_Reserved_31_15_MASK 0xffff8000 |
| 6392 | |
| 6393 | /// D18F2x09C_x0D0F_040F |
| 6394 | typedef union { |
| 6395 | struct { ///< |
| 6396 | UINT32 Reserved_11_0:12; ///< |
| 6397 | UINT32 AlwaysEnDllClks:3 ; ///< |
| 6398 | UINT32 Reserved_31_15:17; ///< |
| 6399 | } Field; ///< |
| 6400 | UINT32 Value; ///< |
| 6401 | } D18F2x09C_x0D0F_040F_STRUCT; |
| 6402 | |
| 6403 | // **** D18F2x09C_x0D0F_0410 Register Definition **** |
| 6404 | // Address |
| 6405 | #define D18F2x09C_x0D0F_0410_ADDRESS 0xd0f0410 |
| 6406 | |
| 6407 | // Type |
| 6408 | #define D18F2x09C_x0D0F_0410_TYPE TYPE_D18F2x09C |
| 6409 | // Field Data |
| 6410 | #define D18F2x09C_x0D0F_0410_Reserved_11_0_OFFSET 0 |
| 6411 | #define D18F2x09C_x0D0F_0410_Reserved_11_0_WIDTH 12 |
| 6412 | #define D18F2x09C_x0D0F_0410_Reserved_11_0_MASK 0xfff |
| 6413 | #define D18F2x09C_x0D0F_0410_EnRxPadStandby_OFFSET 12 |
| 6414 | #define D18F2x09C_x0D0F_0410_EnRxPadStandby_WIDTH 1 |
| 6415 | #define D18F2x09C_x0D0F_0410_EnRxPadStandby_MASK 0x1000 |
| 6416 | #define D18F2x09C_x0D0F_0410_Reserved_31_13_OFFSET 13 |
| 6417 | #define D18F2x09C_x0D0F_0410_Reserved_31_13_WIDTH 19 |
| 6418 | #define D18F2x09C_x0D0F_0410_Reserved_31_13_MASK 0xffffe000 |
| 6419 | |
| 6420 | /// D18F2x09C_x0D0F_0410 |
| 6421 | typedef union { |
| 6422 | struct { ///< |
| 6423 | UINT32 Reserved_11_0:12; ///< |
| 6424 | UINT32 EnRxPadStandby:1 ; ///< |
| 6425 | UINT32 Reserved_31_13:19; ///< |
| 6426 | } Field; ///< |
| 6427 | UINT32 Value; ///< |
| 6428 | } D18F2x09C_x0D0F_0410_STRUCT; |
| 6429 | |
| 6430 | // **** D18F2x09C_x0D0F_041F Register Definition **** |
| 6431 | // Address |
| 6432 | #define D18F2x09C_x0D0F_041F_ADDRESS 0xd0f041f |
| 6433 | |
| 6434 | // Type |
| 6435 | #define D18F2x09C_x0D0F_041F_TYPE TYPE_D18F2x09C |
| 6436 | // Field Data |
| 6437 | #define D18F2x09C_x0D0F_041F_Reserved_2_0_OFFSET 0 |
| 6438 | #define D18F2x09C_x0D0F_041F_Reserved_2_0_WIDTH 3 |
| 6439 | #define D18F2x09C_x0D0F_041F_Reserved_2_0_MASK 0x7 |
| 6440 | #define D18F2x09C_x0D0F_041F_RxVioLvl_OFFSET 3 |
| 6441 | #define D18F2x09C_x0D0F_041F_RxVioLvl_WIDTH 2 |
| 6442 | #define D18F2x09C_x0D0F_041F_RxVioLvl_MASK 0x18 |
| 6443 | #define D18F2x09C_x0D0F_041F_Reserved_31_5_OFFSET 5 |
| 6444 | #define D18F2x09C_x0D0F_041F_Reserved_31_5_WIDTH 27 |
| 6445 | #define D18F2x09C_x0D0F_041F_Reserved_31_5_MASK 0xffffffe0 |
| 6446 | |
| 6447 | /// D18F2x09C_x0D0F_041F |
| 6448 | typedef union { |
| 6449 | struct { ///< |
| 6450 | UINT32 Reserved_2_0:3 ; ///< |
| 6451 | UINT32 RxVioLvl:2 ; ///< |
| 6452 | UINT32 Reserved_31_5:27; ///< |
| 6453 | } Field; ///< |
| 6454 | UINT32 Value; ///< |
| 6455 | } D18F2x09C_x0D0F_041F_STRUCT; |
| 6456 | |
| 6457 | |
| 6458 | |
| 6459 | // **** D18F2x09C_x0D0F_0502 Register Definition **** |
| 6460 | // Address |
| 6461 | #define D18F2x09C_x0D0F_0502_ADDRESS 0xd0f0502 |
| 6462 | |
| 6463 | // Type |
| 6464 | #define D18F2x09C_x0D0F_0502_TYPE TYPE_D18F2x09C |
| 6465 | // Field Data |
| 6466 | #define D18F2x09C_x0D0F_0502_TxPreN_OFFSET 0 |
| 6467 | #define D18F2x09C_x0D0F_0502_TxPreN_WIDTH 6 |
| 6468 | #define D18F2x09C_x0D0F_0502_TxPreN_MASK 0x3f |
| 6469 | #define D18F2x09C_x0D0F_0502_TxPreP_OFFSET 6 |
| 6470 | #define D18F2x09C_x0D0F_0502_TxPreP_WIDTH 6 |
| 6471 | #define D18F2x09C_x0D0F_0502_TxPreP_MASK 0xfc0 |
| 6472 | #define D18F2x09C_x0D0F_0502_Reserved_14_12_OFFSET 12 |
| 6473 | #define D18F2x09C_x0D0F_0502_Reserved_14_12_WIDTH 3 |
| 6474 | #define D18F2x09C_x0D0F_0502_Reserved_14_12_MASK 0x7000 |
| 6475 | #define D18F2x09C_x0D0F_0502_ValidTxAndPre_OFFSET 15 |
| 6476 | #define D18F2x09C_x0D0F_0502_ValidTxAndPre_WIDTH 1 |
| 6477 | #define D18F2x09C_x0D0F_0502_ValidTxAndPre_MASK 0x8000 |
| 6478 | #define D18F2x09C_x0D0F_0502_Reserved_31_16_OFFSET 16 |
| 6479 | #define D18F2x09C_x0D0F_0502_Reserved_31_16_WIDTH 16 |
| 6480 | #define D18F2x09C_x0D0F_0502_Reserved_31_16_MASK 0xffff0000 |
| 6481 | |
| 6482 | /// D18F2x09C_x0D0F_0502 |
| 6483 | typedef union { |
| 6484 | struct { ///< |
| 6485 | UINT32 TxPreN:6 ; ///< |
| 6486 | UINT32 TxPreP:6 ; ///< |
| 6487 | UINT32 Reserved_14_12:3 ; ///< |
| 6488 | UINT32 ValidTxAndPre:1 ; ///< |
| 6489 | UINT32 Reserved_31_16:16; ///< |
| 6490 | } Field; ///< |
| 6491 | UINT32 Value; ///< |
| 6492 | } D18F2x09C_x0D0F_0502_STRUCT; |
| 6493 | |
| 6494 | // **** D18F2x09C_x0D0F_0506 Register Definition **** |
| 6495 | // Address |
| 6496 | #define D18F2x09C_x0D0F_0506_ADDRESS 0xd0f0506 |
| 6497 | |
| 6498 | // Type |
| 6499 | #define D18F2x09C_x0D0F_0506_TYPE TYPE_D18F2x09C |
| 6500 | // Field Data |
| 6501 | #define D18F2x09C_x0D0F_0506_TxPreN_OFFSET 0 |
| 6502 | #define D18F2x09C_x0D0F_0506_TxPreN_WIDTH 6 |
| 6503 | #define D18F2x09C_x0D0F_0506_TxPreN_MASK 0x3f |
| 6504 | #define D18F2x09C_x0D0F_0506_TxPreP_OFFSET 6 |
| 6505 | #define D18F2x09C_x0D0F_0506_TxPreP_WIDTH 6 |
| 6506 | #define D18F2x09C_x0D0F_0506_TxPreP_MASK 0xfc0 |
| 6507 | #define D18F2x09C_x0D0F_0506_Reserved_31_12_OFFSET 12 |
| 6508 | #define D18F2x09C_x0D0F_0506_Reserved_31_12_WIDTH 20 |
| 6509 | #define D18F2x09C_x0D0F_0506_Reserved_31_12_MASK 0xfffff000 |
| 6510 | |
| 6511 | /// D18F2x09C_x0D0F_0506 |
| 6512 | typedef union { |
| 6513 | struct { ///< |
| 6514 | UINT32 TxPreN:6 ; ///< |
| 6515 | UINT32 TxPreP:6 ; ///< |
| 6516 | UINT32 Reserved_31_12:20; ///< |
| 6517 | } Field; ///< |
| 6518 | UINT32 Value; ///< |
| 6519 | } D18F2x09C_x0D0F_0506_STRUCT; |
| 6520 | |
| 6521 | // **** D18F2x09C_x0D0F_050A Register Definition **** |
| 6522 | // Address |
| 6523 | #define D18F2x09C_x0D0F_050A_ADDRESS 0xd0f050a |
| 6524 | |
| 6525 | // Type |
| 6526 | #define D18F2x09C_x0D0F_050A_TYPE TYPE_D18F2x09C |
| 6527 | // Field Data |
| 6528 | #define D18F2x09C_x0D0F_050A_TxPreN_OFFSET 0 |
| 6529 | #define D18F2x09C_x0D0F_050A_TxPreN_WIDTH 6 |
| 6530 | #define D18F2x09C_x0D0F_050A_TxPreN_MASK 0x3f |
| 6531 | #define D18F2x09C_x0D0F_050A_TxPreP_OFFSET 6 |
| 6532 | #define D18F2x09C_x0D0F_050A_TxPreP_WIDTH 6 |
| 6533 | #define D18F2x09C_x0D0F_050A_TxPreP_MASK 0xfc0 |
| 6534 | #define D18F2x09C_x0D0F_050A_Reserved_31_12_OFFSET 12 |
| 6535 | #define D18F2x09C_x0D0F_050A_Reserved_31_12_WIDTH 20 |
| 6536 | #define D18F2x09C_x0D0F_050A_Reserved_31_12_MASK 0xfffff000 |
| 6537 | |
| 6538 | /// D18F2x09C_x0D0F_050A |
| 6539 | typedef union { |
| 6540 | struct { ///< |
| 6541 | UINT32 TxPreN:6 ; ///< |
| 6542 | UINT32 TxPreP:6 ; ///< |
| 6543 | UINT32 Reserved_31_12:20; ///< |
| 6544 | } Field; ///< |
| 6545 | UINT32 Value; ///< |
| 6546 | } D18F2x09C_x0D0F_050A_STRUCT; |
| 6547 | |
| 6548 | // **** D18F2x09C_x0D0F_050F Register Definition **** |
| 6549 | // Address |
| 6550 | #define D18F2x09C_x0D0F_050F_ADDRESS 0xd0f050f |
| 6551 | |
| 6552 | // Type |
| 6553 | #define D18F2x09C_x0D0F_050F_TYPE TYPE_D18F2x09C |
| 6554 | // Field Data |
| 6555 | #define D18F2x09C_x0D0F_050F_Reserved_11_0_OFFSET 0 |
| 6556 | #define D18F2x09C_x0D0F_050F_Reserved_11_0_WIDTH 12 |
| 6557 | #define D18F2x09C_x0D0F_050F_Reserved_11_0_MASK 0xfff |
| 6558 | #define D18F2x09C_x0D0F_050F_AlwaysEnDllClks_OFFSET 12 |
| 6559 | #define D18F2x09C_x0D0F_050F_AlwaysEnDllClks_WIDTH 3 |
| 6560 | #define D18F2x09C_x0D0F_050F_AlwaysEnDllClks_MASK 0x7000 |
| 6561 | #define D18F2x09C_x0D0F_050F_Reserved_31_15_OFFSET 15 |
| 6562 | #define D18F2x09C_x0D0F_050F_Reserved_31_15_WIDTH 17 |
| 6563 | #define D18F2x09C_x0D0F_050F_Reserved_31_15_MASK 0xffff8000 |
| 6564 | |
| 6565 | /// D18F2x09C_x0D0F_050F |
| 6566 | typedef union { |
| 6567 | struct { ///< |
| 6568 | UINT32 Reserved_11_0:12; ///< |
| 6569 | UINT32 AlwaysEnDllClks:3 ; ///< |
| 6570 | UINT32 Reserved_31_15:17; ///< |
| 6571 | } Field; ///< |
| 6572 | UINT32 Value; ///< |
| 6573 | } D18F2x09C_x0D0F_050F_STRUCT; |
| 6574 | |
| 6575 | // **** D18F2x09C_x0D0F_0510 Register Definition **** |
| 6576 | // Address |
| 6577 | #define D18F2x09C_x0D0F_0510_ADDRESS 0xd0f0510 |
| 6578 | |
| 6579 | // Type |
| 6580 | #define D18F2x09C_x0D0F_0510_TYPE TYPE_D18F2x09C |
| 6581 | // Field Data |
| 6582 | #define D18F2x09C_x0D0F_0510_Reserved_11_0_OFFSET 0 |
| 6583 | #define D18F2x09C_x0D0F_0510_Reserved_11_0_WIDTH 12 |
| 6584 | #define D18F2x09C_x0D0F_0510_Reserved_11_0_MASK 0xfff |
| 6585 | #define D18F2x09C_x0D0F_0510_EnRxPadStandby_OFFSET 12 |
| 6586 | #define D18F2x09C_x0D0F_0510_EnRxPadStandby_WIDTH 1 |
| 6587 | #define D18F2x09C_x0D0F_0510_EnRxPadStandby_MASK 0x1000 |
| 6588 | #define D18F2x09C_x0D0F_0510_Reserved_31_13_OFFSET 13 |
| 6589 | #define D18F2x09C_x0D0F_0510_Reserved_31_13_WIDTH 19 |
| 6590 | #define D18F2x09C_x0D0F_0510_Reserved_31_13_MASK 0xffffe000 |
| 6591 | |
| 6592 | /// D18F2x09C_x0D0F_0510 |
| 6593 | typedef union { |
| 6594 | struct { ///< |
| 6595 | UINT32 Reserved_11_0:12; ///< |
| 6596 | UINT32 EnRxPadStandby:1 ; ///< |
| 6597 | UINT32 Reserved_31_13:19; ///< |
| 6598 | } Field; ///< |
| 6599 | UINT32 Value; ///< |
| 6600 | } D18F2x09C_x0D0F_0510_STRUCT; |
| 6601 | |
| 6602 | // **** D18F2x09C_x0D0F_051F Register Definition **** |
| 6603 | // Address |
| 6604 | #define D18F2x09C_x0D0F_051F_ADDRESS 0xd0f051f |
| 6605 | |
| 6606 | // Type |
| 6607 | #define D18F2x09C_x0D0F_051F_TYPE TYPE_D18F2x09C |
| 6608 | // Field Data |
| 6609 | #define D18F2x09C_x0D0F_051F_Reserved_2_0_OFFSET 0 |
| 6610 | #define D18F2x09C_x0D0F_051F_Reserved_2_0_WIDTH 3 |
| 6611 | #define D18F2x09C_x0D0F_051F_Reserved_2_0_MASK 0x7 |
| 6612 | #define D18F2x09C_x0D0F_051F_RxVioLvl_OFFSET 3 |
| 6613 | #define D18F2x09C_x0D0F_051F_RxVioLvl_WIDTH 2 |
| 6614 | #define D18F2x09C_x0D0F_051F_RxVioLvl_MASK 0x18 |
| 6615 | #define D18F2x09C_x0D0F_051F_Reserved_31_5_OFFSET 5 |
| 6616 | #define D18F2x09C_x0D0F_051F_Reserved_31_5_WIDTH 27 |
| 6617 | #define D18F2x09C_x0D0F_051F_Reserved_31_5_MASK 0xffffffe0 |
| 6618 | |
| 6619 | /// D18F2x09C_x0D0F_051F |
| 6620 | typedef union { |
| 6621 | struct { ///< |
| 6622 | UINT32 Reserved_2_0:3 ; ///< |
| 6623 | UINT32 RxVioLvl:2 ; ///< |
| 6624 | UINT32 Reserved_31_5:27; ///< |
| 6625 | } Field; ///< |
| 6626 | UINT32 Value; ///< |
| 6627 | } D18F2x09C_x0D0F_051F_STRUCT; |
| 6628 | |
| 6629 | |
| 6630 | |
| 6631 | // **** D18F2x09C_x0D0F_0602 Register Definition **** |
| 6632 | // Address |
| 6633 | #define D18F2x09C_x0D0F_0602_ADDRESS 0xd0f0602 |
| 6634 | |
| 6635 | // Type |
| 6636 | #define D18F2x09C_x0D0F_0602_TYPE TYPE_D18F2x09C |
| 6637 | // Field Data |
| 6638 | #define D18F2x09C_x0D0F_0602_TxPreN_OFFSET 0 |
| 6639 | #define D18F2x09C_x0D0F_0602_TxPreN_WIDTH 6 |
| 6640 | #define D18F2x09C_x0D0F_0602_TxPreN_MASK 0x3f |
| 6641 | #define D18F2x09C_x0D0F_0602_TxPreP_OFFSET 6 |
| 6642 | #define D18F2x09C_x0D0F_0602_TxPreP_WIDTH 6 |
| 6643 | #define D18F2x09C_x0D0F_0602_TxPreP_MASK 0xfc0 |
| 6644 | #define D18F2x09C_x0D0F_0602_Reserved_14_12_OFFSET 12 |
| 6645 | #define D18F2x09C_x0D0F_0602_Reserved_14_12_WIDTH 3 |
| 6646 | #define D18F2x09C_x0D0F_0602_Reserved_14_12_MASK 0x7000 |
| 6647 | #define D18F2x09C_x0D0F_0602_ValidTxAndPre_OFFSET 15 |
| 6648 | #define D18F2x09C_x0D0F_0602_ValidTxAndPre_WIDTH 1 |
| 6649 | #define D18F2x09C_x0D0F_0602_ValidTxAndPre_MASK 0x8000 |
| 6650 | #define D18F2x09C_x0D0F_0602_Reserved_31_16_OFFSET 16 |
| 6651 | #define D18F2x09C_x0D0F_0602_Reserved_31_16_WIDTH 16 |
| 6652 | #define D18F2x09C_x0D0F_0602_Reserved_31_16_MASK 0xffff0000 |
| 6653 | |
| 6654 | /// D18F2x09C_x0D0F_0602 |
| 6655 | typedef union { |
| 6656 | struct { ///< |
| 6657 | UINT32 TxPreN:6 ; ///< |
| 6658 | UINT32 TxPreP:6 ; ///< |
| 6659 | UINT32 Reserved_14_12:3 ; ///< |
| 6660 | UINT32 ValidTxAndPre:1 ; ///< |
| 6661 | UINT32 Reserved_31_16:16; ///< |
| 6662 | } Field; ///< |
| 6663 | UINT32 Value; ///< |
| 6664 | } D18F2x09C_x0D0F_0602_STRUCT; |
| 6665 | |
| 6666 | // **** D18F2x09C_x0D0F_0606 Register Definition **** |
| 6667 | // Address |
| 6668 | #define D18F2x09C_x0D0F_0606_ADDRESS 0xd0f0606 |
| 6669 | |
| 6670 | // Type |
| 6671 | #define D18F2x09C_x0D0F_0606_TYPE TYPE_D18F2x09C |
| 6672 | // Field Data |
| 6673 | #define D18F2x09C_x0D0F_0606_TxPreN_OFFSET 0 |
| 6674 | #define D18F2x09C_x0D0F_0606_TxPreN_WIDTH 6 |
| 6675 | #define D18F2x09C_x0D0F_0606_TxPreN_MASK 0x3f |
| 6676 | #define D18F2x09C_x0D0F_0606_TxPreP_OFFSET 6 |
| 6677 | #define D18F2x09C_x0D0F_0606_TxPreP_WIDTH 6 |
| 6678 | #define D18F2x09C_x0D0F_0606_TxPreP_MASK 0xfc0 |
| 6679 | #define D18F2x09C_x0D0F_0606_Reserved_31_12_OFFSET 12 |
| 6680 | #define D18F2x09C_x0D0F_0606_Reserved_31_12_WIDTH 20 |
| 6681 | #define D18F2x09C_x0D0F_0606_Reserved_31_12_MASK 0xfffff000 |
| 6682 | |
| 6683 | /// D18F2x09C_x0D0F_0606 |
| 6684 | typedef union { |
| 6685 | struct { ///< |
| 6686 | UINT32 TxPreN:6 ; ///< |
| 6687 | UINT32 TxPreP:6 ; ///< |
| 6688 | UINT32 Reserved_31_12:20; ///< |
| 6689 | } Field; ///< |
| 6690 | UINT32 Value; ///< |
| 6691 | } D18F2x09C_x0D0F_0606_STRUCT; |
| 6692 | |
| 6693 | // **** D18F2x09C_x0D0F_060A Register Definition **** |
| 6694 | // Address |
| 6695 | #define D18F2x09C_x0D0F_060A_ADDRESS 0xd0f060a |
| 6696 | |
| 6697 | // Type |
| 6698 | #define D18F2x09C_x0D0F_060A_TYPE TYPE_D18F2x09C |
| 6699 | // Field Data |
| 6700 | #define D18F2x09C_x0D0F_060A_TxPreN_OFFSET 0 |
| 6701 | #define D18F2x09C_x0D0F_060A_TxPreN_WIDTH 6 |
| 6702 | #define D18F2x09C_x0D0F_060A_TxPreN_MASK 0x3f |
| 6703 | #define D18F2x09C_x0D0F_060A_TxPreP_OFFSET 6 |
| 6704 | #define D18F2x09C_x0D0F_060A_TxPreP_WIDTH 6 |
| 6705 | #define D18F2x09C_x0D0F_060A_TxPreP_MASK 0xfc0 |
| 6706 | #define D18F2x09C_x0D0F_060A_Reserved_31_12_OFFSET 12 |
| 6707 | #define D18F2x09C_x0D0F_060A_Reserved_31_12_WIDTH 20 |
| 6708 | #define D18F2x09C_x0D0F_060A_Reserved_31_12_MASK 0xfffff000 |
| 6709 | |
| 6710 | /// D18F2x09C_x0D0F_060A |
| 6711 | typedef union { |
| 6712 | struct { ///< |
| 6713 | UINT32 TxPreN:6 ; ///< |
| 6714 | UINT32 TxPreP:6 ; ///< |
| 6715 | UINT32 Reserved_31_12:20; ///< |
| 6716 | } Field; ///< |
| 6717 | UINT32 Value; ///< |
| 6718 | } D18F2x09C_x0D0F_060A_STRUCT; |
| 6719 | |
| 6720 | // **** D18F2x09C_x0D0F_060F Register Definition **** |
| 6721 | // Address |
| 6722 | #define D18F2x09C_x0D0F_060F_ADDRESS 0xd0f060f |
| 6723 | |
| 6724 | // Type |
| 6725 | #define D18F2x09C_x0D0F_060F_TYPE TYPE_D18F2x09C |
| 6726 | // Field Data |
| 6727 | #define D18F2x09C_x0D0F_060F_Reserved_11_0_OFFSET 0 |
| 6728 | #define D18F2x09C_x0D0F_060F_Reserved_11_0_WIDTH 12 |
| 6729 | #define D18F2x09C_x0D0F_060F_Reserved_11_0_MASK 0xfff |
| 6730 | #define D18F2x09C_x0D0F_060F_AlwaysEnDllClks_OFFSET 12 |
| 6731 | #define D18F2x09C_x0D0F_060F_AlwaysEnDllClks_WIDTH 3 |
| 6732 | #define D18F2x09C_x0D0F_060F_AlwaysEnDllClks_MASK 0x7000 |
| 6733 | #define D18F2x09C_x0D0F_060F_Reserved_31_15_OFFSET 15 |
| 6734 | #define D18F2x09C_x0D0F_060F_Reserved_31_15_WIDTH 17 |
| 6735 | #define D18F2x09C_x0D0F_060F_Reserved_31_15_MASK 0xffff8000 |
| 6736 | |
| 6737 | /// D18F2x09C_x0D0F_060F |
| 6738 | typedef union { |
| 6739 | struct { ///< |
| 6740 | UINT32 Reserved_11_0:12; ///< |
| 6741 | UINT32 AlwaysEnDllClks:3 ; ///< |
| 6742 | UINT32 Reserved_31_15:17; ///< |
| 6743 | } Field; ///< |
| 6744 | UINT32 Value; ///< |
| 6745 | } D18F2x09C_x0D0F_060F_STRUCT; |
| 6746 | |
| 6747 | // **** D18F2x09C_x0D0F_0610 Register Definition **** |
| 6748 | // Address |
| 6749 | #define D18F2x09C_x0D0F_0610_ADDRESS 0xd0f0610 |
| 6750 | |
| 6751 | // Type |
| 6752 | #define D18F2x09C_x0D0F_0610_TYPE TYPE_D18F2x09C |
| 6753 | // Field Data |
| 6754 | #define D18F2x09C_x0D0F_0610_Reserved_11_0_OFFSET 0 |
| 6755 | #define D18F2x09C_x0D0F_0610_Reserved_11_0_WIDTH 12 |
| 6756 | #define D18F2x09C_x0D0F_0610_Reserved_11_0_MASK 0xfff |
| 6757 | #define D18F2x09C_x0D0F_0610_EnRxPadStandby_OFFSET 12 |
| 6758 | #define D18F2x09C_x0D0F_0610_EnRxPadStandby_WIDTH 1 |
| 6759 | #define D18F2x09C_x0D0F_0610_EnRxPadStandby_MASK 0x1000 |
| 6760 | #define D18F2x09C_x0D0F_0610_Reserved_31_13_OFFSET 13 |
| 6761 | #define D18F2x09C_x0D0F_0610_Reserved_31_13_WIDTH 19 |
| 6762 | #define D18F2x09C_x0D0F_0610_Reserved_31_13_MASK 0xffffe000 |
| 6763 | |
| 6764 | /// D18F2x09C_x0D0F_0610 |
| 6765 | typedef union { |
| 6766 | struct { ///< |
| 6767 | UINT32 Reserved_11_0:12; ///< |
| 6768 | UINT32 EnRxPadStandby:1 ; ///< |
| 6769 | UINT32 Reserved_31_13:19; ///< |
| 6770 | } Field; ///< |
| 6771 | UINT32 Value; ///< |
| 6772 | } D18F2x09C_x0D0F_0610_STRUCT; |
| 6773 | |
| 6774 | // **** D18F2x09C_x0D0F_061F Register Definition **** |
| 6775 | // Address |
| 6776 | #define D18F2x09C_x0D0F_061F_ADDRESS 0xd0f061f |
| 6777 | |
| 6778 | // Type |
| 6779 | #define D18F2x09C_x0D0F_061F_TYPE TYPE_D18F2x09C |
| 6780 | // Field Data |
| 6781 | #define D18F2x09C_x0D0F_061F_Reserved_2_0_OFFSET 0 |
| 6782 | #define D18F2x09C_x0D0F_061F_Reserved_2_0_WIDTH 3 |
| 6783 | #define D18F2x09C_x0D0F_061F_Reserved_2_0_MASK 0x7 |
| 6784 | #define D18F2x09C_x0D0F_061F_RxVioLvl_OFFSET 3 |
| 6785 | #define D18F2x09C_x0D0F_061F_RxVioLvl_WIDTH 2 |
| 6786 | #define D18F2x09C_x0D0F_061F_RxVioLvl_MASK 0x18 |
| 6787 | #define D18F2x09C_x0D0F_061F_Reserved_31_5_OFFSET 5 |
| 6788 | #define D18F2x09C_x0D0F_061F_Reserved_31_5_WIDTH 27 |
| 6789 | #define D18F2x09C_x0D0F_061F_Reserved_31_5_MASK 0xffffffe0 |
| 6790 | |
| 6791 | /// D18F2x09C_x0D0F_061F |
| 6792 | typedef union { |
| 6793 | struct { ///< |
| 6794 | UINT32 Reserved_2_0:3 ; ///< |
| 6795 | UINT32 RxVioLvl:2 ; ///< |
| 6796 | UINT32 Reserved_31_5:27; ///< |
| 6797 | } Field; ///< |
| 6798 | UINT32 Value; ///< |
| 6799 | } D18F2x09C_x0D0F_061F_STRUCT; |
| 6800 | |
| 6801 | |
| 6802 | |
| 6803 | // **** D18F2x09C_x0D0F_0702 Register Definition **** |
| 6804 | // Address |
| 6805 | #define D18F2x09C_x0D0F_0702_ADDRESS 0xd0f0702 |
| 6806 | |
| 6807 | // Type |
| 6808 | #define D18F2x09C_x0D0F_0702_TYPE TYPE_D18F2x09C |
| 6809 | // Field Data |
| 6810 | #define D18F2x09C_x0D0F_0702_TxPreN_OFFSET 0 |
| 6811 | #define D18F2x09C_x0D0F_0702_TxPreN_WIDTH 6 |
| 6812 | #define D18F2x09C_x0D0F_0702_TxPreN_MASK 0x3f |
| 6813 | #define D18F2x09C_x0D0F_0702_TxPreP_OFFSET 6 |
| 6814 | #define D18F2x09C_x0D0F_0702_TxPreP_WIDTH 6 |
| 6815 | #define D18F2x09C_x0D0F_0702_TxPreP_MASK 0xfc0 |
| 6816 | #define D18F2x09C_x0D0F_0702_Reserved_14_12_OFFSET 12 |
| 6817 | #define D18F2x09C_x0D0F_0702_Reserved_14_12_WIDTH 3 |
| 6818 | #define D18F2x09C_x0D0F_0702_Reserved_14_12_MASK 0x7000 |
| 6819 | #define D18F2x09C_x0D0F_0702_ValidTxAndPre_OFFSET 15 |
| 6820 | #define D18F2x09C_x0D0F_0702_ValidTxAndPre_WIDTH 1 |
| 6821 | #define D18F2x09C_x0D0F_0702_ValidTxAndPre_MASK 0x8000 |
| 6822 | #define D18F2x09C_x0D0F_0702_Reserved_31_16_OFFSET 16 |
| 6823 | #define D18F2x09C_x0D0F_0702_Reserved_31_16_WIDTH 16 |
| 6824 | #define D18F2x09C_x0D0F_0702_Reserved_31_16_MASK 0xffff0000 |
| 6825 | |
| 6826 | /// D18F2x09C_x0D0F_0702 |
| 6827 | typedef union { |
| 6828 | struct { ///< |
| 6829 | UINT32 TxPreN:6 ; ///< |
| 6830 | UINT32 TxPreP:6 ; ///< |
| 6831 | UINT32 Reserved_14_12:3 ; ///< |
| 6832 | UINT32 ValidTxAndPre:1 ; ///< |
| 6833 | UINT32 Reserved_31_16:16; ///< |
| 6834 | } Field; ///< |
| 6835 | UINT32 Value; ///< |
| 6836 | } D18F2x09C_x0D0F_0702_STRUCT; |
| 6837 | |
| 6838 | // **** D18F2x09C_x0D0F_0706 Register Definition **** |
| 6839 | // Address |
| 6840 | #define D18F2x09C_x0D0F_0706_ADDRESS 0xd0f0706 |
| 6841 | |
| 6842 | // Type |
| 6843 | #define D18F2x09C_x0D0F_0706_TYPE TYPE_D18F2x09C |
| 6844 | // Field Data |
| 6845 | #define D18F2x09C_x0D0F_0706_TxPreN_OFFSET 0 |
| 6846 | #define D18F2x09C_x0D0F_0706_TxPreN_WIDTH 6 |
| 6847 | #define D18F2x09C_x0D0F_0706_TxPreN_MASK 0x3f |
| 6848 | #define D18F2x09C_x0D0F_0706_TxPreP_OFFSET 6 |
| 6849 | #define D18F2x09C_x0D0F_0706_TxPreP_WIDTH 6 |
| 6850 | #define D18F2x09C_x0D0F_0706_TxPreP_MASK 0xfc0 |
| 6851 | #define D18F2x09C_x0D0F_0706_Reserved_31_12_OFFSET 12 |
| 6852 | #define D18F2x09C_x0D0F_0706_Reserved_31_12_WIDTH 20 |
| 6853 | #define D18F2x09C_x0D0F_0706_Reserved_31_12_MASK 0xfffff000 |
| 6854 | |
| 6855 | /// D18F2x09C_x0D0F_0706 |
| 6856 | typedef union { |
| 6857 | struct { ///< |
| 6858 | UINT32 TxPreN:6 ; ///< |
| 6859 | UINT32 TxPreP:6 ; ///< |
| 6860 | UINT32 Reserved_31_12:20; ///< |
| 6861 | } Field; ///< |
| 6862 | UINT32 Value; ///< |
| 6863 | } D18F2x09C_x0D0F_0706_STRUCT; |
| 6864 | |
| 6865 | // **** D18F2x09C_x0D0F_070A Register Definition **** |
| 6866 | // Address |
| 6867 | #define D18F2x09C_x0D0F_070A_ADDRESS 0xd0f070a |
| 6868 | |
| 6869 | // Type |
| 6870 | #define D18F2x09C_x0D0F_070A_TYPE TYPE_D18F2x09C |
| 6871 | // Field Data |
| 6872 | #define D18F2x09C_x0D0F_070A_TxPreN_OFFSET 0 |
| 6873 | #define D18F2x09C_x0D0F_070A_TxPreN_WIDTH 6 |
| 6874 | #define D18F2x09C_x0D0F_070A_TxPreN_MASK 0x3f |
| 6875 | #define D18F2x09C_x0D0F_070A_TxPreP_OFFSET 6 |
| 6876 | #define D18F2x09C_x0D0F_070A_TxPreP_WIDTH 6 |
| 6877 | #define D18F2x09C_x0D0F_070A_TxPreP_MASK 0xfc0 |
| 6878 | #define D18F2x09C_x0D0F_070A_Reserved_31_12_OFFSET 12 |
| 6879 | #define D18F2x09C_x0D0F_070A_Reserved_31_12_WIDTH 20 |
| 6880 | #define D18F2x09C_x0D0F_070A_Reserved_31_12_MASK 0xfffff000 |
| 6881 | |
| 6882 | /// D18F2x09C_x0D0F_070A |
| 6883 | typedef union { |
| 6884 | struct { ///< |
| 6885 | UINT32 TxPreN:6 ; ///< |
| 6886 | UINT32 TxPreP:6 ; ///< |
| 6887 | UINT32 Reserved_31_12:20; ///< |
| 6888 | } Field; ///< |
| 6889 | UINT32 Value; ///< |
| 6890 | } D18F2x09C_x0D0F_070A_STRUCT; |
| 6891 | |
| 6892 | // **** D18F2x09C_x0D0F_070F Register Definition **** |
| 6893 | // Address |
| 6894 | #define D18F2x09C_x0D0F_070F_ADDRESS 0xd0f070f |
| 6895 | |
| 6896 | // Type |
| 6897 | #define D18F2x09C_x0D0F_070F_TYPE TYPE_D18F2x09C |
| 6898 | // Field Data |
| 6899 | #define D18F2x09C_x0D0F_070F_Reserved_11_0_OFFSET 0 |
| 6900 | #define D18F2x09C_x0D0F_070F_Reserved_11_0_WIDTH 12 |
| 6901 | #define D18F2x09C_x0D0F_070F_Reserved_11_0_MASK 0xfff |
| 6902 | #define D18F2x09C_x0D0F_070F_AlwaysEnDllClks_OFFSET 12 |
| 6903 | #define D18F2x09C_x0D0F_070F_AlwaysEnDllClks_WIDTH 3 |
| 6904 | #define D18F2x09C_x0D0F_070F_AlwaysEnDllClks_MASK 0x7000 |
| 6905 | #define D18F2x09C_x0D0F_070F_Reserved_31_15_OFFSET 15 |
| 6906 | #define D18F2x09C_x0D0F_070F_Reserved_31_15_WIDTH 17 |
| 6907 | #define D18F2x09C_x0D0F_070F_Reserved_31_15_MASK 0xffff8000 |
| 6908 | |
| 6909 | /// D18F2x09C_x0D0F_070F |
| 6910 | typedef union { |
| 6911 | struct { ///< |
| 6912 | UINT32 Reserved_11_0:12; ///< |
| 6913 | UINT32 AlwaysEnDllClks:3 ; ///< |
| 6914 | UINT32 Reserved_31_15:17; ///< |
| 6915 | } Field; ///< |
| 6916 | UINT32 Value; ///< |
| 6917 | } D18F2x09C_x0D0F_070F_STRUCT; |
| 6918 | |
| 6919 | // **** D18F2x09C_x0D0F_0710 Register Definition **** |
| 6920 | // Address |
| 6921 | #define D18F2x09C_x0D0F_0710_ADDRESS 0xd0f0710 |
| 6922 | |
| 6923 | // Type |
| 6924 | #define D18F2x09C_x0D0F_0710_TYPE TYPE_D18F2x09C |
| 6925 | // Field Data |
| 6926 | #define D18F2x09C_x0D0F_0710_Reserved_11_0_OFFSET 0 |
| 6927 | #define D18F2x09C_x0D0F_0710_Reserved_11_0_WIDTH 12 |
| 6928 | #define D18F2x09C_x0D0F_0710_Reserved_11_0_MASK 0xfff |
| 6929 | #define D18F2x09C_x0D0F_0710_EnRxPadStandby_OFFSET 12 |
| 6930 | #define D18F2x09C_x0D0F_0710_EnRxPadStandby_WIDTH 1 |
| 6931 | #define D18F2x09C_x0D0F_0710_EnRxPadStandby_MASK 0x1000 |
| 6932 | #define D18F2x09C_x0D0F_0710_Reserved_31_13_OFFSET 13 |
| 6933 | #define D18F2x09C_x0D0F_0710_Reserved_31_13_WIDTH 19 |
| 6934 | #define D18F2x09C_x0D0F_0710_Reserved_31_13_MASK 0xffffe000 |
| 6935 | |
| 6936 | /// D18F2x09C_x0D0F_0710 |
| 6937 | typedef union { |
| 6938 | struct { ///< |
| 6939 | UINT32 Reserved_11_0:12; ///< |
| 6940 | UINT32 EnRxPadStandby:1 ; ///< |
| 6941 | UINT32 Reserved_31_13:19; ///< |
| 6942 | } Field; ///< |
| 6943 | UINT32 Value; ///< |
| 6944 | } D18F2x09C_x0D0F_0710_STRUCT; |
| 6945 | |
| 6946 | // **** D18F2x09C_x0D0F_071F Register Definition **** |
| 6947 | // Address |
| 6948 | #define D18F2x09C_x0D0F_071F_ADDRESS 0xd0f071f |
| 6949 | |
| 6950 | // Type |
| 6951 | #define D18F2x09C_x0D0F_071F_TYPE TYPE_D18F2x09C |
| 6952 | // Field Data |
| 6953 | #define D18F2x09C_x0D0F_071F_Reserved_2_0_OFFSET 0 |
| 6954 | #define D18F2x09C_x0D0F_071F_Reserved_2_0_WIDTH 3 |
| 6955 | #define D18F2x09C_x0D0F_071F_Reserved_2_0_MASK 0x7 |
| 6956 | #define D18F2x09C_x0D0F_071F_RxVioLvl_OFFSET 3 |
| 6957 | #define D18F2x09C_x0D0F_071F_RxVioLvl_WIDTH 2 |
| 6958 | #define D18F2x09C_x0D0F_071F_RxVioLvl_MASK 0x18 |
| 6959 | #define D18F2x09C_x0D0F_071F_Reserved_31_5_OFFSET 5 |
| 6960 | #define D18F2x09C_x0D0F_071F_Reserved_31_5_WIDTH 27 |
| 6961 | #define D18F2x09C_x0D0F_071F_Reserved_31_5_MASK 0xffffffe0 |
| 6962 | |
| 6963 | /// D18F2x09C_x0D0F_071F |
| 6964 | typedef union { |
| 6965 | struct { ///< |
| 6966 | UINT32 Reserved_2_0:3 ; ///< |
| 6967 | UINT32 RxVioLvl:2 ; ///< |
| 6968 | UINT32 Reserved_31_5:27; ///< |
| 6969 | } Field; ///< |
| 6970 | UINT32 Value; ///< |
| 6971 | } D18F2x09C_x0D0F_071F_STRUCT; |
| 6972 | |
| 6973 | |
| 6974 | |
| 6975 | // **** D18F2x09C_x0D0F_0F02 Register Definition **** |
| 6976 | // Address |
| 6977 | #define D18F2x09C_x0D0F_0F02_ADDRESS 0xd0f0f02 |
| 6978 | |
| 6979 | // Type |
| 6980 | #define D18F2x09C_x0D0F_0F02_TYPE TYPE_D18F2x09C |
| 6981 | // Field Data |
| 6982 | #define D18F2x09C_x0D0F_0F02_TxPreN_OFFSET 0 |
| 6983 | #define D18F2x09C_x0D0F_0F02_TxPreN_WIDTH 6 |
| 6984 | #define D18F2x09C_x0D0F_0F02_TxPreN_MASK 0x3f |
| 6985 | #define D18F2x09C_x0D0F_0F02_TxPreP_OFFSET 6 |
| 6986 | #define D18F2x09C_x0D0F_0F02_TxPreP_WIDTH 6 |
| 6987 | #define D18F2x09C_x0D0F_0F02_TxPreP_MASK 0xfc0 |
| 6988 | #define D18F2x09C_x0D0F_0F02_Reserved_14_12_OFFSET 12 |
| 6989 | #define D18F2x09C_x0D0F_0F02_Reserved_14_12_WIDTH 3 |
| 6990 | #define D18F2x09C_x0D0F_0F02_Reserved_14_12_MASK 0x7000 |
| 6991 | #define D18F2x09C_x0D0F_0F02_ValidTxAndPre_OFFSET 15 |
| 6992 | #define D18F2x09C_x0D0F_0F02_ValidTxAndPre_WIDTH 1 |
| 6993 | #define D18F2x09C_x0D0F_0F02_ValidTxAndPre_MASK 0x8000 |
| 6994 | #define D18F2x09C_x0D0F_0F02_Reserved_31_16_OFFSET 16 |
| 6995 | #define D18F2x09C_x0D0F_0F02_Reserved_31_16_WIDTH 16 |
| 6996 | #define D18F2x09C_x0D0F_0F02_Reserved_31_16_MASK 0xffff0000 |
| 6997 | |
| 6998 | /// D18F2x09C_x0D0F_0F02 |
| 6999 | typedef union { |
| 7000 | struct { ///< |
| 7001 | UINT32 TxPreN:6 ; ///< |
| 7002 | UINT32 TxPreP:6 ; ///< |
| 7003 | UINT32 Reserved_14_12:3 ; ///< |
| 7004 | UINT32 ValidTxAndPre:1 ; ///< |
| 7005 | UINT32 Reserved_31_16:16; ///< |
| 7006 | } Field; ///< |
| 7007 | UINT32 Value; ///< |
| 7008 | } D18F2x09C_x0D0F_0F02_STRUCT; |
| 7009 | |
| 7010 | // **** D18F2x09C_x0D0F_0F06 Register Definition **** |
| 7011 | // Address |
| 7012 | #define D18F2x09C_x0D0F_0F06_ADDRESS 0xd0f0f06 |
| 7013 | |
| 7014 | // Type |
| 7015 | #define D18F2x09C_x0D0F_0F06_TYPE TYPE_D18F2x09C |
| 7016 | // Field Data |
| 7017 | #define D18F2x09C_x0D0F_0F06_TxPreN_OFFSET 0 |
| 7018 | #define D18F2x09C_x0D0F_0F06_TxPreN_WIDTH 6 |
| 7019 | #define D18F2x09C_x0D0F_0F06_TxPreN_MASK 0x3f |
| 7020 | #define D18F2x09C_x0D0F_0F06_TxPreP_OFFSET 6 |
| 7021 | #define D18F2x09C_x0D0F_0F06_TxPreP_WIDTH 6 |
| 7022 | #define D18F2x09C_x0D0F_0F06_TxPreP_MASK 0xfc0 |
| 7023 | #define D18F2x09C_x0D0F_0F06_Reserved_31_12_OFFSET 12 |
| 7024 | #define D18F2x09C_x0D0F_0F06_Reserved_31_12_WIDTH 20 |
| 7025 | #define D18F2x09C_x0D0F_0F06_Reserved_31_12_MASK 0xfffff000 |
| 7026 | |
| 7027 | /// D18F2x09C_x0D0F_0F06 |
| 7028 | typedef union { |
| 7029 | struct { ///< |
| 7030 | UINT32 TxPreN:6 ; ///< |
| 7031 | UINT32 TxPreP:6 ; ///< |
| 7032 | UINT32 Reserved_31_12:20; ///< |
| 7033 | } Field; ///< |
| 7034 | UINT32 Value; ///< |
| 7035 | } D18F2x09C_x0D0F_0F06_STRUCT; |
| 7036 | |
| 7037 | // **** D18F2x09C_x0D0F_0F0A Register Definition **** |
| 7038 | // Address |
| 7039 | #define D18F2x09C_x0D0F_0F0A_ADDRESS 0xd0f0f0a |
| 7040 | |
| 7041 | // Type |
| 7042 | #define D18F2x09C_x0D0F_0F0A_TYPE TYPE_D18F2x09C |
| 7043 | // Field Data |
| 7044 | #define D18F2x09C_x0D0F_0F0A_TxPreN_OFFSET 0 |
| 7045 | #define D18F2x09C_x0D0F_0F0A_TxPreN_WIDTH 6 |
| 7046 | #define D18F2x09C_x0D0F_0F0A_TxPreN_MASK 0x3f |
| 7047 | #define D18F2x09C_x0D0F_0F0A_TxPreP_OFFSET 6 |
| 7048 | #define D18F2x09C_x0D0F_0F0A_TxPreP_WIDTH 6 |
| 7049 | #define D18F2x09C_x0D0F_0F0A_TxPreP_MASK 0xfc0 |
| 7050 | #define D18F2x09C_x0D0F_0F0A_Reserved_31_12_OFFSET 12 |
| 7051 | #define D18F2x09C_x0D0F_0F0A_Reserved_31_12_WIDTH 20 |
| 7052 | #define D18F2x09C_x0D0F_0F0A_Reserved_31_12_MASK 0xfffff000 |
| 7053 | |
| 7054 | /// D18F2x09C_x0D0F_0F0A |
| 7055 | typedef union { |
| 7056 | struct { ///< |
| 7057 | UINT32 TxPreN:6 ; ///< |
| 7058 | UINT32 TxPreP:6 ; ///< |
| 7059 | UINT32 Reserved_31_12:20; ///< |
| 7060 | } Field; ///< |
| 7061 | UINT32 Value; ///< |
| 7062 | } D18F2x09C_x0D0F_0F0A_STRUCT; |
| 7063 | |
| 7064 | // **** D18F2x09C_x0D0F_0F0F Register Definition **** |
| 7065 | // Address |
| 7066 | #define D18F2x09C_x0D0F_0F0F_ADDRESS 0xd0f0f0f |
| 7067 | |
| 7068 | // Type |
| 7069 | #define D18F2x09C_x0D0F_0F0F_TYPE TYPE_D18F2x09C |
| 7070 | // Field Data |
| 7071 | #define D18F2x09C_x0D0F_0F0F_Reserved_11_0_OFFSET 0 |
| 7072 | #define D18F2x09C_x0D0F_0F0F_Reserved_11_0_WIDTH 12 |
| 7073 | #define D18F2x09C_x0D0F_0F0F_Reserved_11_0_MASK 0xfff |
| 7074 | #define D18F2x09C_x0D0F_0F0F_AlwaysEnDllClks_OFFSET 12 |
| 7075 | #define D18F2x09C_x0D0F_0F0F_AlwaysEnDllClks_WIDTH 3 |
| 7076 | #define D18F2x09C_x0D0F_0F0F_AlwaysEnDllClks_MASK 0x7000 |
| 7077 | #define D18F2x09C_x0D0F_0F0F_Reserved_31_15_OFFSET 15 |
| 7078 | #define D18F2x09C_x0D0F_0F0F_Reserved_31_15_WIDTH 17 |
| 7079 | #define D18F2x09C_x0D0F_0F0F_Reserved_31_15_MASK 0xffff8000 |
| 7080 | |
| 7081 | /// D18F2x09C_x0D0F_0F0F |
| 7082 | typedef union { |
| 7083 | struct { ///< |
| 7084 | UINT32 Reserved_11_0:12; ///< |
| 7085 | UINT32 AlwaysEnDllClks:3 ; ///< |
| 7086 | UINT32 Reserved_31_15:17; ///< |
| 7087 | } Field; ///< |
| 7088 | UINT32 Value; ///< |
| 7089 | } D18F2x09C_x0D0F_0F0F_STRUCT; |
| 7090 | |
| 7091 | // **** D18F2x09C_x0D0F_0F10 Register Definition **** |
| 7092 | // Address |
| 7093 | #define D18F2x09C_x0D0F_0F10_ADDRESS 0xd0f0f10 |
| 7094 | |
| 7095 | // Type |
| 7096 | #define D18F2x09C_x0D0F_0F10_TYPE TYPE_D18F2x09C |
| 7097 | // Field Data |
| 7098 | #define D18F2x09C_x0D0F_0F10_Reserved_11_0_OFFSET 0 |
| 7099 | #define D18F2x09C_x0D0F_0F10_Reserved_11_0_WIDTH 12 |
| 7100 | #define D18F2x09C_x0D0F_0F10_Reserved_11_0_MASK 0xfff |
| 7101 | #define D18F2x09C_x0D0F_0F10_EnRxPadStandby_OFFSET 12 |
| 7102 | #define D18F2x09C_x0D0F_0F10_EnRxPadStandby_WIDTH 1 |
| 7103 | #define D18F2x09C_x0D0F_0F10_EnRxPadStandby_MASK 0x1000 |
| 7104 | #define D18F2x09C_x0D0F_0F10_Reserved_31_13_OFFSET 13 |
| 7105 | #define D18F2x09C_x0D0F_0F10_Reserved_31_13_WIDTH 19 |
| 7106 | #define D18F2x09C_x0D0F_0F10_Reserved_31_13_MASK 0xffffe000 |
| 7107 | |
| 7108 | /// D18F2x09C_x0D0F_0F10 |
| 7109 | typedef union { |
| 7110 | struct { ///< |
| 7111 | UINT32 Reserved_11_0:12; ///< |
| 7112 | UINT32 EnRxPadStandby:1 ; ///< |
| 7113 | UINT32 Reserved_31_13:19; ///< |
| 7114 | } Field; ///< |
| 7115 | UINT32 Value; ///< |
| 7116 | } D18F2x09C_x0D0F_0F10_STRUCT; |
| 7117 | |
| 7118 | // **** D18F2x09C_x0D0F_0F13 Register Definition **** |
| 7119 | // Address |
| 7120 | #define D18F2x09C_x0D0F_0F13_ADDRESS 0xd0f0f13 |
| 7121 | |
| 7122 | // Type |
| 7123 | #define D18F2x09C_x0D0F_0F13_TYPE TYPE_D18F2x09C |
| 7124 | // Field Data |
| 7125 | #define D18F2x09C_x0D0F_0F13_DllDisEarlyL_OFFSET 0 |
| 7126 | #define D18F2x09C_x0D0F_0F13_DllDisEarlyL_WIDTH 1 |
| 7127 | #define D18F2x09C_x0D0F_0F13_DllDisEarlyL_MASK 0x1 |
| 7128 | #define D18F2x09C_x0D0F_0F13_DllDisEarlyU_OFFSET 1 |
| 7129 | #define D18F2x09C_x0D0F_0F13_DllDisEarlyU_WIDTH 1 |
| 7130 | #define D18F2x09C_x0D0F_0F13_DllDisEarlyU_MASK 0x2 |
| 7131 | #define D18F2x09C_x0D0F_0F13_Reserved_6_2_OFFSET 2 |
| 7132 | #define D18F2x09C_x0D0F_0F13_Reserved_6_2_WIDTH 5 |
| 7133 | #define D18F2x09C_x0D0F_0F13_Reserved_6_2_MASK 0x7c |
| 7134 | #define D18F2x09C_x0D0F_0F13_RxDqsUDllPowerDown_OFFSET 7 |
| 7135 | #define D18F2x09C_x0D0F_0F13_RxDqsUDllPowerDown_WIDTH 1 |
| 7136 | #define D18F2x09C_x0D0F_0F13_RxDqsUDllPowerDown_MASK 0x80 |
| 7137 | #define D18F2x09C_x0D0F_0F13_Reserved_13_8_OFFSET 8 |
| 7138 | #define D18F2x09C_x0D0F_0F13_Reserved_13_8_WIDTH 6 |
| 7139 | #define D18F2x09C_x0D0F_0F13_Reserved_13_8_MASK 0x3f00 |
| 7140 | #define D18F2x09C_x0D0F_0F13_ProcOdtAdv_OFFSET 14 |
| 7141 | #define D18F2x09C_x0D0F_0F13_ProcOdtAdv_WIDTH 1 |
| 7142 | #define D18F2x09C_x0D0F_0F13_ProcOdtAdv_MASK 0x4000 |
| 7143 | #define D18F2x09C_x0D0F_0F13_Reserved_31_15_OFFSET 15 |
| 7144 | #define D18F2x09C_x0D0F_0F13_Reserved_31_15_WIDTH 17 |
| 7145 | #define D18F2x09C_x0D0F_0F13_Reserved_31_15_MASK 0xffff8000 |
| 7146 | |
| 7147 | /// D18F2x09C_x0D0F_0F13 |
| 7148 | typedef union { |
| 7149 | struct { ///< |
| 7150 | UINT32 DllDisEarlyL:1 ; ///< |
| 7151 | UINT32 DllDisEarlyU:1 ; ///< |
| 7152 | UINT32 Reserved_6_2:5 ; ///< |
| 7153 | UINT32 RxDqsUDllPowerDown:1 ; ///< |
| 7154 | UINT32 Reserved_13_8:6 ; ///< |
| 7155 | UINT32 ProcOdtAdv:1 ; ///< |
| 7156 | UINT32 Reserved_31_15:17; ///< |
| 7157 | } Field; ///< |
| 7158 | UINT32 Value; ///< |
| 7159 | } D18F2x09C_x0D0F_0F13_STRUCT; |
| 7160 | |
| 7161 | // **** D18F2x09C_x0D0F_0F1F Register Definition **** |
| 7162 | // Address |
| 7163 | #define D18F2x09C_x0D0F_0F1F_ADDRESS 0xd0f0f1f |
| 7164 | |
| 7165 | // Type |
| 7166 | #define D18F2x09C_x0D0F_0F1F_TYPE TYPE_D18F2x09C |
| 7167 | // Field Data |
| 7168 | #define D18F2x09C_x0D0F_0F1F_Reserved_2_0_OFFSET 0 |
| 7169 | #define D18F2x09C_x0D0F_0F1F_Reserved_2_0_WIDTH 3 |
| 7170 | #define D18F2x09C_x0D0F_0F1F_Reserved_2_0_MASK 0x7 |
| 7171 | #define D18F2x09C_x0D0F_0F1F_RxVioLvl_OFFSET 3 |
| 7172 | #define D18F2x09C_x0D0F_0F1F_RxVioLvl_WIDTH 2 |
| 7173 | #define D18F2x09C_x0D0F_0F1F_RxVioLvl_MASK 0x18 |
| 7174 | #define D18F2x09C_x0D0F_0F1F_Reserved_31_5_OFFSET 5 |
| 7175 | #define D18F2x09C_x0D0F_0F1F_Reserved_31_5_WIDTH 27 |
| 7176 | #define D18F2x09C_x0D0F_0F1F_Reserved_31_5_MASK 0xffffffe0 |
| 7177 | |
| 7178 | /// D18F2x09C_x0D0F_0F1F |
| 7179 | typedef union { |
| 7180 | struct { ///< |
| 7181 | UINT32 Reserved_2_0:3 ; ///< |
| 7182 | UINT32 RxVioLvl:2 ; ///< |
| 7183 | UINT32 Reserved_31_5:27; ///< |
| 7184 | } Field; ///< |
| 7185 | UINT32 Value; ///< |
| 7186 | } D18F2x09C_x0D0F_0F1F_STRUCT; |
| 7187 | |
| 7188 | |
| 7189 | |
| 7190 | // **** D18F2x09C_x0D0F_2002 Register Definition **** |
| 7191 | // Address |
| 7192 | #define D18F2x09C_x0D0F_2002_ADDRESS 0xd0f2002 |
| 7193 | |
| 7194 | // Type |
| 7195 | #define D18F2x09C_x0D0F_2002_TYPE TYPE_D18F2x09C |
| 7196 | // Field Data |
| 7197 | #define D18F2x09C_x0D0F_2002_TxPreN_OFFSET 0 |
| 7198 | #define D18F2x09C_x0D0F_2002_TxPreN_WIDTH 6 |
| 7199 | #define D18F2x09C_x0D0F_2002_TxPreN_MASK 0x3f |
| 7200 | #define D18F2x09C_x0D0F_2002_TxPreP_OFFSET 6 |
| 7201 | #define D18F2x09C_x0D0F_2002_TxPreP_WIDTH 6 |
| 7202 | #define D18F2x09C_x0D0F_2002_TxPreP_MASK 0xfc0 |
| 7203 | #define D18F2x09C_x0D0F_2002_Reserved_14_12_OFFSET 12 |
| 7204 | #define D18F2x09C_x0D0F_2002_Reserved_14_12_WIDTH 3 |
| 7205 | #define D18F2x09C_x0D0F_2002_Reserved_14_12_MASK 0x7000 |
| 7206 | #define D18F2x09C_x0D0F_2002_ValidTxAndPre_OFFSET 15 |
| 7207 | #define D18F2x09C_x0D0F_2002_ValidTxAndPre_WIDTH 1 |
| 7208 | #define D18F2x09C_x0D0F_2002_ValidTxAndPre_MASK 0x8000 |
| 7209 | #define D18F2x09C_x0D0F_2002_Reserved_31_16_OFFSET 16 |
| 7210 | #define D18F2x09C_x0D0F_2002_Reserved_31_16_WIDTH 16 |
| 7211 | #define D18F2x09C_x0D0F_2002_Reserved_31_16_MASK 0xffff0000 |
| 7212 | |
| 7213 | /// D18F2x09C_x0D0F_2002 |
| 7214 | typedef union { |
| 7215 | struct { ///< |
| 7216 | UINT32 TxPreN:6 ; ///< |
| 7217 | UINT32 TxPreP:6 ; ///< |
| 7218 | UINT32 Reserved_14_12:3 ; ///< |
| 7219 | UINT32 ValidTxAndPre:1 ; ///< |
| 7220 | UINT32 Reserved_31_16:16; ///< |
| 7221 | } Field; ///< |
| 7222 | UINT32 Value; ///< |
| 7223 | } D18F2x09C_x0D0F_2002_STRUCT; |
| 7224 | |
| 7225 | // **** D18F2x09C_x0D0F_201F Register Definition **** |
| 7226 | // Address |
| 7227 | #define D18F2x09C_x0D0F_201F_ADDRESS 0xd0f201f |
| 7228 | |
| 7229 | // Type |
| 7230 | #define D18F2x09C_x0D0F_201F_TYPE TYPE_D18F2x09C |
| 7231 | // Field Data |
| 7232 | #define D18F2x09C_x0D0F_201F_Reserved_2_0_OFFSET 0 |
| 7233 | #define D18F2x09C_x0D0F_201F_Reserved_2_0_WIDTH 3 |
| 7234 | #define D18F2x09C_x0D0F_201F_Reserved_2_0_MASK 0x7 |
| 7235 | #define D18F2x09C_x0D0F_201F_RxVioLvl_OFFSET 3 |
| 7236 | #define D18F2x09C_x0D0F_201F_RxVioLvl_WIDTH 2 |
| 7237 | #define D18F2x09C_x0D0F_201F_RxVioLvl_MASK 0x18 |
| 7238 | #define D18F2x09C_x0D0F_201F_Reserved_31_5_OFFSET 5 |
| 7239 | #define D18F2x09C_x0D0F_201F_Reserved_31_5_WIDTH 27 |
| 7240 | #define D18F2x09C_x0D0F_201F_Reserved_31_5_MASK 0xffffffe0 |
| 7241 | |
| 7242 | /// D18F2x09C_x0D0F_201F |
| 7243 | typedef union { |
| 7244 | struct { ///< |
| 7245 | UINT32 Reserved_2_0:3 ; ///< |
| 7246 | UINT32 RxVioLvl:2 ; ///< |
| 7247 | UINT32 Reserved_31_5:27; ///< |
| 7248 | } Field; ///< |
| 7249 | UINT32 Value; ///< |
| 7250 | } D18F2x09C_x0D0F_201F_STRUCT; |
| 7251 | |
| 7252 | |
| 7253 | // **** D18F2x09C_x0D0F_2030 Register Definition **** |
| 7254 | // Address |
| 7255 | #define D18F2x09C_x0D0F_2030_ADDRESS 0xd0f2030 |
| 7256 | |
| 7257 | // Type |
| 7258 | #define D18F2x09C_x0D0F_2030_TYPE TYPE_D18F2x09C |
| 7259 | // Field Data |
| 7260 | #define D18F2x09C_x0D0F_2030_Reserved_3_0_OFFSET 0 |
| 7261 | #define D18F2x09C_x0D0F_2030_Reserved_3_0_WIDTH 4 |
| 7262 | #define D18F2x09C_x0D0F_2030_Reserved_3_0_MASK 0xf |
| 7263 | #define D18F2x09C_x0D0F_2030_PwrDn_OFFSET 4 |
| 7264 | #define D18F2x09C_x0D0F_2030_PwrDn_WIDTH 1 |
| 7265 | #define D18F2x09C_x0D0F_2030_PwrDn_MASK 0x10 |
| 7266 | #define D18F2x09C_x0D0F_2030_Reserved_31_5_OFFSET 5 |
| 7267 | #define D18F2x09C_x0D0F_2030_Reserved_31_5_WIDTH 27 |
| 7268 | #define D18F2x09C_x0D0F_2030_Reserved_31_5_MASK 0xffffffe0 |
| 7269 | |
| 7270 | /// D18F2x09C_x0D0F_2030 |
| 7271 | typedef union { |
| 7272 | struct { ///< |
| 7273 | UINT32 Reserved_3_0:4 ; ///< |
| 7274 | UINT32 PwrDn:1 ; ///< |
| 7275 | UINT32 Reserved_31_5:27; ///< |
| 7276 | } Field; ///< |
| 7277 | UINT32 Value; ///< |
| 7278 | } D18F2x09C_x0D0F_2030_STRUCT; |
| 7279 | |
| 7280 | |
| 7281 | // **** D18F2x09C_x0D0F_2102 Register Definition **** |
| 7282 | // Address |
| 7283 | #define D18F2x09C_x0D0F_2102_ADDRESS 0xd0f2102 |
| 7284 | |
| 7285 | // Type |
| 7286 | #define D18F2x09C_x0D0F_2102_TYPE TYPE_D18F2x09C |
| 7287 | // Field Data |
| 7288 | #define D18F2x09C_x0D0F_2102_TxPreN_OFFSET 0 |
| 7289 | #define D18F2x09C_x0D0F_2102_TxPreN_WIDTH 6 |
| 7290 | #define D18F2x09C_x0D0F_2102_TxPreN_MASK 0x3f |
| 7291 | #define D18F2x09C_x0D0F_2102_TxPreP_OFFSET 6 |
| 7292 | #define D18F2x09C_x0D0F_2102_TxPreP_WIDTH 6 |
| 7293 | #define D18F2x09C_x0D0F_2102_TxPreP_MASK 0xfc0 |
| 7294 | #define D18F2x09C_x0D0F_2102_Reserved_14_12_OFFSET 12 |
| 7295 | #define D18F2x09C_x0D0F_2102_Reserved_14_12_WIDTH 3 |
| 7296 | #define D18F2x09C_x0D0F_2102_Reserved_14_12_MASK 0x7000 |
| 7297 | #define D18F2x09C_x0D0F_2102_ValidTxAndPre_OFFSET 15 |
| 7298 | #define D18F2x09C_x0D0F_2102_ValidTxAndPre_WIDTH 1 |
| 7299 | #define D18F2x09C_x0D0F_2102_ValidTxAndPre_MASK 0x8000 |
| 7300 | #define D18F2x09C_x0D0F_2102_Reserved_31_16_OFFSET 16 |
| 7301 | #define D18F2x09C_x0D0F_2102_Reserved_31_16_WIDTH 16 |
| 7302 | #define D18F2x09C_x0D0F_2102_Reserved_31_16_MASK 0xffff0000 |
| 7303 | |
| 7304 | /// D18F2x09C_x0D0F_2102 |
| 7305 | typedef union { |
| 7306 | struct { ///< |
| 7307 | UINT32 TxPreN:6 ; ///< |
| 7308 | UINT32 TxPreP:6 ; ///< |
| 7309 | UINT32 Reserved_14_12:3 ; ///< |
| 7310 | UINT32 ValidTxAndPre:1 ; ///< |
| 7311 | UINT32 Reserved_31_16:16; ///< |
| 7312 | } Field; ///< |
| 7313 | UINT32 Value; ///< |
| 7314 | } D18F2x09C_x0D0F_2102_STRUCT; |
| 7315 | |
| 7316 | // **** D18F2x09C_x0D0F_211F Register Definition **** |
| 7317 | // Address |
| 7318 | #define D18F2x09C_x0D0F_211F_ADDRESS 0xd0f211f |
| 7319 | |
| 7320 | // Type |
| 7321 | #define D18F2x09C_x0D0F_211F_TYPE TYPE_D18F2x09C |
| 7322 | // Field Data |
| 7323 | #define D18F2x09C_x0D0F_211F_Reserved_2_0_OFFSET 0 |
| 7324 | #define D18F2x09C_x0D0F_211F_Reserved_2_0_WIDTH 3 |
| 7325 | #define D18F2x09C_x0D0F_211F_Reserved_2_0_MASK 0x7 |
| 7326 | #define D18F2x09C_x0D0F_211F_RxVioLvl_OFFSET 3 |
| 7327 | #define D18F2x09C_x0D0F_211F_RxVioLvl_WIDTH 2 |
| 7328 | #define D18F2x09C_x0D0F_211F_RxVioLvl_MASK 0x18 |
| 7329 | #define D18F2x09C_x0D0F_211F_Reserved_31_5_OFFSET 5 |
| 7330 | #define D18F2x09C_x0D0F_211F_Reserved_31_5_WIDTH 27 |
| 7331 | #define D18F2x09C_x0D0F_211F_Reserved_31_5_MASK 0xffffffe0 |
| 7332 | |
| 7333 | /// D18F2x09C_x0D0F_211F |
| 7334 | typedef union { |
| 7335 | struct { ///< |
| 7336 | UINT32 Reserved_2_0:3 ; ///< |
| 7337 | UINT32 RxVioLvl:2 ; ///< |
| 7338 | UINT32 Reserved_31_5:27; ///< |
| 7339 | } Field; ///< |
| 7340 | UINT32 Value; ///< |
| 7341 | } D18F2x09C_x0D0F_211F_STRUCT; |
| 7342 | |
| 7343 | |
| 7344 | // **** D18F2x09C_x0D0F_2130 Register Definition **** |
| 7345 | // Address |
| 7346 | #define D18F2x09C_x0D0F_2130_ADDRESS 0xd0f2130 |
| 7347 | |
| 7348 | // Type |
| 7349 | #define D18F2x09C_x0D0F_2130_TYPE TYPE_D18F2x09C |
| 7350 | // Field Data |
| 7351 | #define D18F2x09C_x0D0F_2130_Reserved_3_0_OFFSET 0 |
| 7352 | #define D18F2x09C_x0D0F_2130_Reserved_3_0_WIDTH 4 |
| 7353 | #define D18F2x09C_x0D0F_2130_Reserved_3_0_MASK 0xf |
| 7354 | #define D18F2x09C_x0D0F_2130_PwrDn_OFFSET 4 |
| 7355 | #define D18F2x09C_x0D0F_2130_PwrDn_WIDTH 1 |
| 7356 | #define D18F2x09C_x0D0F_2130_PwrDn_MASK 0x10 |
| 7357 | #define D18F2x09C_x0D0F_2130_Reserved_31_5_OFFSET 5 |
| 7358 | #define D18F2x09C_x0D0F_2130_Reserved_31_5_WIDTH 27 |
| 7359 | #define D18F2x09C_x0D0F_2130_Reserved_31_5_MASK 0xffffffe0 |
| 7360 | |
| 7361 | /// D18F2x09C_x0D0F_2130 |
| 7362 | typedef union { |
| 7363 | struct { ///< |
| 7364 | UINT32 Reserved_3_0:4 ; ///< |
| 7365 | UINT32 PwrDn:1 ; ///< |
| 7366 | UINT32 Reserved_31_5:27; ///< |
| 7367 | } Field; ///< |
| 7368 | UINT32 Value; ///< |
| 7369 | } D18F2x09C_x0D0F_2130_STRUCT; |
| 7370 | |
| 7371 | // Field Data |
| 7372 | #define D18F2x09C_x0D0F_4009_Reserved_1_0_OFFSET 0 |
| 7373 | #define D18F2x09C_x0D0F_4009_Reserved_1_0_WIDTH 2 |
| 7374 | #define D18F2x09C_x0D0F_4009_Reserved_1_0_MASK 0x3 |
| 7375 | #define D18F2x09C_x0D0F_4009_ComparatorAdjust_OFFSET 2 |
| 7376 | #define D18F2x09C_x0D0F_4009_ComparatorAdjust_WIDTH 2 |
| 7377 | #define D18F2x09C_x0D0F_4009_ComparatorAdjust_MASK 0xc |
| 7378 | #define D18F2x09C_x0D0F_4009_Reserved_13_4_OFFSET 4 |
| 7379 | #define D18F2x09C_x0D0F_4009_Reserved_13_4_WIDTH 10 |
| 7380 | #define D18F2x09C_x0D0F_4009_Reserved_13_4_MASK 0x3ff0 |
| 7381 | #define D18F2x09C_x0D0F_4009_CmpVioLvl_OFFSET 14 |
| 7382 | #define D18F2x09C_x0D0F_4009_CmpVioLvl_WIDTH 2 |
| 7383 | #define D18F2x09C_x0D0F_4009_CmpVioLvl_MASK 0xc000 |
| 7384 | #define D18F2x09C_x0D0F_4009_Reserved_31_16_OFFSET 16 |
| 7385 | #define D18F2x09C_x0D0F_4009_Reserved_31_16_WIDTH 16 |
| 7386 | #define D18F2x09C_x0D0F_4009_Reserved_31_16_MASK 0xffff0000 |
| 7387 | |
| 7388 | /// D18F2x09C_x0D0F_4009 |
| 7389 | typedef union { |
| 7390 | struct { ///< |
| 7391 | UINT32 Reserved_1_0:2 ; ///< |
| 7392 | UINT32 ComparatorAdjust:2 ; ///< |
| 7393 | UINT32 Reserved_13_4:10; ///< |
| 7394 | UINT32 CmpVioLvl:2 ; ///< |
| 7395 | UINT32 Reserved_31_16:16; ///< |
| 7396 | } Field; ///< |
| 7397 | UINT32 Value; ///< |
| 7398 | } D18F2x09C_x0D0F_4009_STRUCT; |
| 7399 | |
| 7400 | // **** D18F2x09C_x0D0F_8002 Register Definition **** |
| 7401 | // Address |
| 7402 | #define D18F2x09C_x0D0F_8002_ADDRESS 0xd0f8002 |
| 7403 | |
| 7404 | // Type |
| 7405 | #define D18F2x09C_x0D0F_8002_TYPE TYPE_D18F2x09C |
| 7406 | // Field Data |
| 7407 | #define D18F2x09C_x0D0F_8002_TxPreN_OFFSET 0 |
| 7408 | #define D18F2x09C_x0D0F_8002_TxPreN_WIDTH 6 |
| 7409 | #define D18F2x09C_x0D0F_8002_TxPreN_MASK 0x3f |
| 7410 | #define D18F2x09C_x0D0F_8002_TxPreP_OFFSET 6 |
| 7411 | #define D18F2x09C_x0D0F_8002_TxPreP_WIDTH 6 |
| 7412 | #define D18F2x09C_x0D0F_8002_TxPreP_MASK 0xfc0 |
| 7413 | #define D18F2x09C_x0D0F_8002_Reserved_14_12_OFFSET 12 |
| 7414 | #define D18F2x09C_x0D0F_8002_Reserved_14_12_WIDTH 3 |
| 7415 | #define D18F2x09C_x0D0F_8002_Reserved_14_12_MASK 0x7000 |
| 7416 | #define D18F2x09C_x0D0F_8002_ValidTxAndPre_OFFSET 15 |
| 7417 | #define D18F2x09C_x0D0F_8002_ValidTxAndPre_WIDTH 1 |
| 7418 | #define D18F2x09C_x0D0F_8002_ValidTxAndPre_MASK 0x8000 |
| 7419 | #define D18F2x09C_x0D0F_8002_Reserved_31_16_OFFSET 16 |
| 7420 | #define D18F2x09C_x0D0F_8002_Reserved_31_16_WIDTH 16 |
| 7421 | #define D18F2x09C_x0D0F_8002_Reserved_31_16_MASK 0xffff0000 |
| 7422 | |
| 7423 | /// D18F2x09C_x0D0F_8002 |
| 7424 | typedef union { |
| 7425 | struct { ///< |
| 7426 | UINT32 TxPreN:6 ; ///< |
| 7427 | UINT32 TxPreP:6 ; ///< |
| 7428 | UINT32 Reserved_14_12:3 ; ///< |
| 7429 | UINT32 ValidTxAndPre:1 ; ///< |
| 7430 | UINT32 Reserved_31_16:16; ///< |
| 7431 | } Field; ///< |
| 7432 | UINT32 Value; ///< |
| 7433 | } D18F2x09C_x0D0F_8002_STRUCT; |
| 7434 | |
| 7435 | // **** D18F2x09C_x0D0F_8006 Register Definition **** |
| 7436 | // Address |
| 7437 | #define D18F2x09C_x0D0F_8006_ADDRESS 0xd0f8006 |
| 7438 | |
| 7439 | // Type |
| 7440 | #define D18F2x09C_x0D0F_8006_TYPE TYPE_D18F2x09C |
| 7441 | // Field Data |
| 7442 | #define D18F2x09C_x0D0F_8006_TxPreN_OFFSET 0 |
| 7443 | #define D18F2x09C_x0D0F_8006_TxPreN_WIDTH 6 |
| 7444 | #define D18F2x09C_x0D0F_8006_TxPreN_MASK 0x3f |
| 7445 | #define D18F2x09C_x0D0F_8006_TxPreP_OFFSET 6 |
| 7446 | #define D18F2x09C_x0D0F_8006_TxPreP_WIDTH 6 |
| 7447 | #define D18F2x09C_x0D0F_8006_TxPreP_MASK 0xfc0 |
| 7448 | #define D18F2x09C_x0D0F_8006_Reserved_31_12_OFFSET 12 |
| 7449 | #define D18F2x09C_x0D0F_8006_Reserved_31_12_WIDTH 20 |
| 7450 | #define D18F2x09C_x0D0F_8006_Reserved_31_12_MASK 0xfffff000 |
| 7451 | |
| 7452 | /// D18F2x09C_x0D0F_8006 |
| 7453 | typedef union { |
| 7454 | struct { ///< |
| 7455 | UINT32 TxPreN:6 ; ///< |
| 7456 | UINT32 TxPreP:6 ; ///< |
| 7457 | UINT32 Reserved_31_12:20; ///< |
| 7458 | } Field; ///< |
| 7459 | UINT32 Value; ///< |
| 7460 | } D18F2x09C_x0D0F_8006_STRUCT; |
| 7461 | |
| 7462 | // **** D18F2x09C_x0D0F_800A Register Definition **** |
| 7463 | // Address |
| 7464 | #define D18F2x09C_x0D0F_800A_ADDRESS 0xd0f800a |
| 7465 | |
| 7466 | // Type |
| 7467 | #define D18F2x09C_x0D0F_800A_TYPE TYPE_D18F2x09C |
| 7468 | // Field Data |
| 7469 | #define D18F2x09C_x0D0F_800A_TxPreN_OFFSET 0 |
| 7470 | #define D18F2x09C_x0D0F_800A_TxPreN_WIDTH 6 |
| 7471 | #define D18F2x09C_x0D0F_800A_TxPreN_MASK 0x3f |
| 7472 | #define D18F2x09C_x0D0F_800A_TxPreP_OFFSET 6 |
| 7473 | #define D18F2x09C_x0D0F_800A_TxPreP_WIDTH 6 |
| 7474 | #define D18F2x09C_x0D0F_800A_TxPreP_MASK 0xfc0 |
| 7475 | #define D18F2x09C_x0D0F_800A_Reserved_31_12_OFFSET 12 |
| 7476 | #define D18F2x09C_x0D0F_800A_Reserved_31_12_WIDTH 20 |
| 7477 | #define D18F2x09C_x0D0F_800A_Reserved_31_12_MASK 0xfffff000 |
| 7478 | |
| 7479 | /// D18F2x09C_x0D0F_800A |
| 7480 | typedef union { |
| 7481 | struct { ///< |
| 7482 | UINT32 TxPreN:6 ; ///< |
| 7483 | UINT32 TxPreP:6 ; ///< |
| 7484 | UINT32 Reserved_31_12:20; ///< |
| 7485 | } Field; ///< |
| 7486 | UINT32 Value; ///< |
| 7487 | } D18F2x09C_x0D0F_800A_STRUCT; |
| 7488 | |
| 7489 | |
| 7490 | |
| 7491 | // **** D18F2x09C_x0D0F_8102 Register Definition **** |
| 7492 | // Address |
| 7493 | #define D18F2x09C_x0D0F_8102_ADDRESS 0xd0f8102 |
| 7494 | |
| 7495 | // Type |
| 7496 | #define D18F2x09C_x0D0F_8102_TYPE TYPE_D18F2x09C |
| 7497 | // Field Data |
| 7498 | #define D18F2x09C_x0D0F_8102_TxPreN_OFFSET 0 |
| 7499 | #define D18F2x09C_x0D0F_8102_TxPreN_WIDTH 6 |
| 7500 | #define D18F2x09C_x0D0F_8102_TxPreN_MASK 0x3f |
| 7501 | #define D18F2x09C_x0D0F_8102_TxPreP_OFFSET 6 |
| 7502 | #define D18F2x09C_x0D0F_8102_TxPreP_WIDTH 6 |
| 7503 | #define D18F2x09C_x0D0F_8102_TxPreP_MASK 0xfc0 |
| 7504 | #define D18F2x09C_x0D0F_8102_Reserved_14_12_OFFSET 12 |
| 7505 | #define D18F2x09C_x0D0F_8102_Reserved_14_12_WIDTH 3 |
| 7506 | #define D18F2x09C_x0D0F_8102_Reserved_14_12_MASK 0x7000 |
| 7507 | #define D18F2x09C_x0D0F_8102_ValidTxAndPre_OFFSET 15 |
| 7508 | #define D18F2x09C_x0D0F_8102_ValidTxAndPre_WIDTH 1 |
| 7509 | #define D18F2x09C_x0D0F_8102_ValidTxAndPre_MASK 0x8000 |
| 7510 | #define D18F2x09C_x0D0F_8102_Reserved_31_16_OFFSET 16 |
| 7511 | #define D18F2x09C_x0D0F_8102_Reserved_31_16_WIDTH 16 |
| 7512 | #define D18F2x09C_x0D0F_8102_Reserved_31_16_MASK 0xffff0000 |
| 7513 | |
| 7514 | /// D18F2x09C_x0D0F_8102 |
| 7515 | typedef union { |
| 7516 | struct { ///< |
| 7517 | UINT32 TxPreN:6 ; ///< |
| 7518 | UINT32 TxPreP:6 ; ///< |
| 7519 | UINT32 Reserved_14_12:3 ; ///< |
| 7520 | UINT32 ValidTxAndPre:1 ; ///< |
| 7521 | UINT32 Reserved_31_16:16; ///< |
| 7522 | } Field; ///< |
| 7523 | UINT32 Value; ///< |
| 7524 | } D18F2x09C_x0D0F_8102_STRUCT; |
| 7525 | |
| 7526 | // **** D18F2x09C_x0D0F_8106 Register Definition **** |
| 7527 | // Address |
| 7528 | #define D18F2x09C_x0D0F_8106_ADDRESS 0xd0f8106 |
| 7529 | |
| 7530 | // Type |
| 7531 | #define D18F2x09C_x0D0F_8106_TYPE TYPE_D18F2x09C |
| 7532 | // Field Data |
| 7533 | #define D18F2x09C_x0D0F_8106_TxPreN_OFFSET 0 |
| 7534 | #define D18F2x09C_x0D0F_8106_TxPreN_WIDTH 6 |
| 7535 | #define D18F2x09C_x0D0F_8106_TxPreN_MASK 0x3f |
| 7536 | #define D18F2x09C_x0D0F_8106_TxPreP_OFFSET 6 |
| 7537 | #define D18F2x09C_x0D0F_8106_TxPreP_WIDTH 6 |
| 7538 | #define D18F2x09C_x0D0F_8106_TxPreP_MASK 0xfc0 |
| 7539 | #define D18F2x09C_x0D0F_8106_Reserved_31_12_OFFSET 12 |
| 7540 | #define D18F2x09C_x0D0F_8106_Reserved_31_12_WIDTH 20 |
| 7541 | #define D18F2x09C_x0D0F_8106_Reserved_31_12_MASK 0xfffff000 |
| 7542 | |
| 7543 | /// D18F2x09C_x0D0F_8106 |
| 7544 | typedef union { |
| 7545 | struct { ///< |
| 7546 | UINT32 TxPreN:6 ; ///< |
| 7547 | UINT32 TxPreP:6 ; ///< |
| 7548 | UINT32 Reserved_31_12:20; ///< |
| 7549 | } Field; ///< |
| 7550 | UINT32 Value; ///< |
| 7551 | } D18F2x09C_x0D0F_8106_STRUCT; |
| 7552 | |
| 7553 | // **** D18F2x09C_x0D0F_810A Register Definition **** |
| 7554 | // Address |
| 7555 | #define D18F2x09C_x0D0F_810A_ADDRESS 0xd0f810a |
| 7556 | |
| 7557 | // Type |
| 7558 | #define D18F2x09C_x0D0F_810A_TYPE TYPE_D18F2x09C |
| 7559 | // Field Data |
| 7560 | #define D18F2x09C_x0D0F_810A_TxPreN_OFFSET 0 |
| 7561 | #define D18F2x09C_x0D0F_810A_TxPreN_WIDTH 6 |
| 7562 | #define D18F2x09C_x0D0F_810A_TxPreN_MASK 0x3f |
| 7563 | #define D18F2x09C_x0D0F_810A_TxPreP_OFFSET 6 |
| 7564 | #define D18F2x09C_x0D0F_810A_TxPreP_WIDTH 6 |
| 7565 | #define D18F2x09C_x0D0F_810A_TxPreP_MASK 0xfc0 |
| 7566 | #define D18F2x09C_x0D0F_810A_Reserved_31_12_OFFSET 12 |
| 7567 | #define D18F2x09C_x0D0F_810A_Reserved_31_12_WIDTH 20 |
| 7568 | #define D18F2x09C_x0D0F_810A_Reserved_31_12_MASK 0xfffff000 |
| 7569 | |
| 7570 | /// D18F2x09C_x0D0F_810A |
| 7571 | typedef union { |
| 7572 | struct { ///< |
| 7573 | UINT32 TxPreN:6 ; ///< |
| 7574 | UINT32 TxPreP:6 ; ///< |
| 7575 | UINT32 Reserved_31_12:20; ///< |
| 7576 | } Field; ///< |
| 7577 | UINT32 Value; ///< |
| 7578 | } D18F2x09C_x0D0F_810A_STRUCT; |
| 7579 | |
| 7580 | |
| 7581 | |
| 7582 | |
| 7583 | // **** D18F2x09C_x0D0F_C000 Register Definition **** |
| 7584 | // Address |
| 7585 | #define D18F2x09C_x0D0F_C000_ADDRESS 0xd0fc000 |
| 7586 | |
| 7587 | // Type |
| 7588 | #define D18F2x09C_x0D0F_C000_TYPE TYPE_D18F2x09C |
| 7589 | // Field Data |
| 7590 | #define D18F2x09C_x0D0F_C000_Reserved_7_0_OFFSET 0 |
| 7591 | #define D18F2x09C_x0D0F_C000_Reserved_7_0_WIDTH 8 |
| 7592 | #define D18F2x09C_x0D0F_C000_Reserved_7_0_MASK 0xff |
| 7593 | #define D18F2x09C_x0D0F_C000_LowPowerDrvStrengthEn_OFFSET 8 |
| 7594 | #define D18F2x09C_x0D0F_C000_LowPowerDrvStrengthEn_WIDTH 1 |
| 7595 | #define D18F2x09C_x0D0F_C000_LowPowerDrvStrengthEn_MASK 0x100 |
| 7596 | #define D18F2x09C_x0D0F_C000_Reserved_31_9_OFFSET 9 |
| 7597 | #define D18F2x09C_x0D0F_C000_Reserved_31_9_WIDTH 23 |
| 7598 | #define D18F2x09C_x0D0F_C000_Reserved_31_9_MASK 0xfffffe00 |
| 7599 | |
| 7600 | /// D18F2x09C_x0D0F_C000 |
| 7601 | typedef union { |
| 7602 | struct { ///< |
| 7603 | UINT32 Reserved_7_0:8 ; ///< |
| 7604 | UINT32 LowPowerDrvStrengthEn:1 ; ///< |
| 7605 | UINT32 Reserved_31_9:23; ///< |
| 7606 | } Field; ///< |
| 7607 | UINT32 Value; ///< |
| 7608 | } D18F2x09C_x0D0F_C000_STRUCT; |
| 7609 | |
| 7610 | // **** D18F2x09C_x0D0F_C002 Register Definition **** |
| 7611 | // Address |
| 7612 | #define D18F2x09C_x0D0F_C002_ADDRESS 0xd0fc002 |
| 7613 | |
| 7614 | // Type |
| 7615 | #define D18F2x09C_x0D0F_C002_TYPE TYPE_D18F2x09C |
| 7616 | // Field Data |
| 7617 | #define D18F2x09C_x0D0F_C002_TxPreN_OFFSET 0 |
| 7618 | #define D18F2x09C_x0D0F_C002_TxPreN_WIDTH 6 |
| 7619 | #define D18F2x09C_x0D0F_C002_TxPreN_MASK 0x3f |
| 7620 | #define D18F2x09C_x0D0F_C002_TxPreP_OFFSET 6 |
| 7621 | #define D18F2x09C_x0D0F_C002_TxPreP_WIDTH 6 |
| 7622 | #define D18F2x09C_x0D0F_C002_TxPreP_MASK 0xfc0 |
| 7623 | #define D18F2x09C_x0D0F_C002_Reserved_14_12_OFFSET 12 |
| 7624 | #define D18F2x09C_x0D0F_C002_Reserved_14_12_WIDTH 3 |
| 7625 | #define D18F2x09C_x0D0F_C002_Reserved_14_12_MASK 0x7000 |
| 7626 | #define D18F2x09C_x0D0F_C002_ValidTxAndPre_OFFSET 15 |
| 7627 | #define D18F2x09C_x0D0F_C002_ValidTxAndPre_WIDTH 1 |
| 7628 | #define D18F2x09C_x0D0F_C002_ValidTxAndPre_MASK 0x8000 |
| 7629 | #define D18F2x09C_x0D0F_C002_Reserved_31_16_OFFSET 16 |
| 7630 | #define D18F2x09C_x0D0F_C002_Reserved_31_16_WIDTH 16 |
| 7631 | #define D18F2x09C_x0D0F_C002_Reserved_31_16_MASK 0xffff0000 |
| 7632 | |
| 7633 | /// D18F2x09C_x0D0F_C002 |
| 7634 | typedef union { |
| 7635 | struct { ///< |
| 7636 | UINT32 TxPreN:6 ; ///< |
| 7637 | UINT32 TxPreP:6 ; ///< |
| 7638 | UINT32 Reserved_14_12:3 ; ///< |
| 7639 | UINT32 ValidTxAndPre:1 ; ///< |
| 7640 | UINT32 Reserved_31_16:16; ///< |
| 7641 | } Field; ///< |
| 7642 | UINT32 Value; ///< |
| 7643 | } D18F2x09C_x0D0F_C002_STRUCT; |
| 7644 | |
| 7645 | // **** D18F2x09C_x0D0F_C006 Register Definition **** |
| 7646 | // Address |
| 7647 | #define D18F2x09C_x0D0F_C006_ADDRESS 0xd0fc006 |
| 7648 | |
| 7649 | // Type |
| 7650 | #define D18F2x09C_x0D0F_C006_TYPE TYPE_D18F2x09C |
| 7651 | // Field Data |
| 7652 | #define D18F2x09C_x0D0F_C006_TxPreN_OFFSET 0 |
| 7653 | #define D18F2x09C_x0D0F_C006_TxPreN_WIDTH 6 |
| 7654 | #define D18F2x09C_x0D0F_C006_TxPreN_MASK 0x3f |
| 7655 | #define D18F2x09C_x0D0F_C006_TxPreP_OFFSET 6 |
| 7656 | #define D18F2x09C_x0D0F_C006_TxPreP_WIDTH 6 |
| 7657 | #define D18F2x09C_x0D0F_C006_TxPreP_MASK 0xfc0 |
| 7658 | #define D18F2x09C_x0D0F_C006_Reserved_31_12_OFFSET 12 |
| 7659 | #define D18F2x09C_x0D0F_C006_Reserved_31_12_WIDTH 20 |
| 7660 | #define D18F2x09C_x0D0F_C006_Reserved_31_12_MASK 0xfffff000 |
| 7661 | |
| 7662 | /// D18F2x09C_x0D0F_C006 |
| 7663 | typedef union { |
| 7664 | struct { ///< |
| 7665 | UINT32 TxPreN:6 ; ///< |
| 7666 | UINT32 TxPreP:6 ; ///< |
| 7667 | UINT32 Reserved_31_12:20; ///< |
| 7668 | } Field; ///< |
| 7669 | UINT32 Value; ///< |
| 7670 | } D18F2x09C_x0D0F_C006_STRUCT; |
| 7671 | |
| 7672 | // **** D18F2x09C_x0D0F_C00A Register Definition **** |
| 7673 | // Address |
| 7674 | #define D18F2x09C_x0D0F_C00A_ADDRESS 0xd0fc00a |
| 7675 | |
| 7676 | // Type |
| 7677 | #define D18F2x09C_x0D0F_C00A_TYPE TYPE_D18F2x09C |
| 7678 | // Field Data |
| 7679 | #define D18F2x09C_x0D0F_C00A_TxPreN_OFFSET 0 |
| 7680 | #define D18F2x09C_x0D0F_C00A_TxPreN_WIDTH 6 |
| 7681 | #define D18F2x09C_x0D0F_C00A_TxPreN_MASK 0x3f |
| 7682 | #define D18F2x09C_x0D0F_C00A_TxPreP_OFFSET 6 |
| 7683 | #define D18F2x09C_x0D0F_C00A_TxPreP_WIDTH 6 |
| 7684 | #define D18F2x09C_x0D0F_C00A_TxPreP_MASK 0xfc0 |
| 7685 | #define D18F2x09C_x0D0F_C00A_Reserved_31_12_OFFSET 12 |
| 7686 | #define D18F2x09C_x0D0F_C00A_Reserved_31_12_WIDTH 20 |
| 7687 | #define D18F2x09C_x0D0F_C00A_Reserved_31_12_MASK 0xfffff000 |
| 7688 | |
| 7689 | /// D18F2x09C_x0D0F_C00A |
| 7690 | typedef union { |
| 7691 | struct { ///< |
| 7692 | UINT32 TxPreN:6 ; ///< |
| 7693 | UINT32 TxPreP:6 ; ///< |
| 7694 | UINT32 Reserved_31_12:20; ///< |
| 7695 | } Field; ///< |
| 7696 | UINT32 Value; ///< |
| 7697 | } D18F2x09C_x0D0F_C00A_STRUCT; |
| 7698 | |
| 7699 | // **** D18F2x09C_x0D0F_C00E Register Definition **** |
| 7700 | // Address |
| 7701 | #define D18F2x09C_x0D0F_C00E_ADDRESS 0xd0fc00e |
| 7702 | |
| 7703 | // Type |
| 7704 | #define D18F2x09C_x0D0F_C00E_TYPE TYPE_D18F2x09C |
| 7705 | // Field Data |
| 7706 | #define D18F2x09C_x0D0F_C00E_TxPreN_OFFSET 0 |
| 7707 | #define D18F2x09C_x0D0F_C00E_TxPreN_WIDTH 6 |
| 7708 | #define D18F2x09C_x0D0F_C00E_TxPreN_MASK 0x3f |
| 7709 | #define D18F2x09C_x0D0F_C00E_TxPreP_OFFSET 6 |
| 7710 | #define D18F2x09C_x0D0F_C00E_TxPreP_WIDTH 6 |
| 7711 | #define D18F2x09C_x0D0F_C00E_TxPreP_MASK 0xfc0 |
| 7712 | #define D18F2x09C_x0D0F_C00E_Reserved_31_12_OFFSET 12 |
| 7713 | #define D18F2x09C_x0D0F_C00E_Reserved_31_12_WIDTH 20 |
| 7714 | #define D18F2x09C_x0D0F_C00E_Reserved_31_12_MASK 0xfffff000 |
| 7715 | |
| 7716 | /// D18F2x09C_x0D0F_C00E |
| 7717 | typedef union { |
| 7718 | struct { ///< |
| 7719 | UINT32 TxPreN:6 ; ///< |
| 7720 | UINT32 TxPreP:6 ; ///< |
| 7721 | UINT32 Reserved_31_12:20; ///< |
| 7722 | } Field; ///< |
| 7723 | UINT32 Value; ///< |
| 7724 | } D18F2x09C_x0D0F_C00E_STRUCT; |
| 7725 | |
| 7726 | // **** D18F2x09C_x0D0F_C012 Register Definition **** |
| 7727 | // Address |
| 7728 | #define D18F2x09C_x0D0F_C012_ADDRESS 0xd0fc012 |
| 7729 | |
| 7730 | // Type |
| 7731 | #define D18F2x09C_x0D0F_C012_TYPE TYPE_D18F2x09C |
| 7732 | // Field Data |
| 7733 | #define D18F2x09C_x0D0F_C012_TxPreN_OFFSET 0 |
| 7734 | #define D18F2x09C_x0D0F_C012_TxPreN_WIDTH 6 |
| 7735 | #define D18F2x09C_x0D0F_C012_TxPreN_MASK 0x3f |
| 7736 | #define D18F2x09C_x0D0F_C012_TxPreP_OFFSET 6 |
| 7737 | #define D18F2x09C_x0D0F_C012_TxPreP_WIDTH 6 |
| 7738 | #define D18F2x09C_x0D0F_C012_TxPreP_MASK 0xfc0 |
| 7739 | #define D18F2x09C_x0D0F_C012_Reserved_31_12_OFFSET 12 |
| 7740 | #define D18F2x09C_x0D0F_C012_Reserved_31_12_WIDTH 20 |
| 7741 | #define D18F2x09C_x0D0F_C012_Reserved_31_12_MASK 0xfffff000 |
| 7742 | |
| 7743 | /// D18F2x09C_x0D0F_C012 |
| 7744 | typedef union { |
| 7745 | struct { ///< |
| 7746 | UINT32 TxPreN:6 ; ///< |
| 7747 | UINT32 TxPreP:6 ; ///< |
| 7748 | UINT32 Reserved_31_12:20; ///< |
| 7749 | } Field; ///< |
| 7750 | UINT32 Value; ///< |
| 7751 | } D18F2x09C_x0D0F_C012_STRUCT; |
| 7752 | |
| 7753 | |
| 7754 | |
| 7755 | |
| 7756 | // **** D18F2x09C_x0D0F_E006 Register Definition **** |
| 7757 | // Address |
| 7758 | #define D18F2x09C_x0D0F_E006_ADDRESS 0xd0fe006 |
| 7759 | |
| 7760 | // Type |
| 7761 | #define D18F2x09C_x0D0F_E006_TYPE TYPE_D18F2x09C |
| 7762 | // Field Data |
| 7763 | #define D18F2x09C_x0D0F_E006_PllLockTime_OFFSET 0 |
| 7764 | #define D18F2x09C_x0D0F_E006_PllLockTime_WIDTH 16 |
| 7765 | #define D18F2x09C_x0D0F_E006_PllLockTime_MASK 0xffff |
| 7766 | #define D18F2x09C_x0D0F_E006_Reserved_31_16_OFFSET 16 |
| 7767 | #define D18F2x09C_x0D0F_E006_Reserved_31_16_WIDTH 16 |
| 7768 | #define D18F2x09C_x0D0F_E006_Reserved_31_16_MASK 0xffff0000 |
| 7769 | |
| 7770 | /// D18F2x09C_x0D0F_E006 |
| 7771 | typedef union { |
| 7772 | struct { ///< |
| 7773 | UINT32 PllLockTime:16; ///< |
| 7774 | UINT32 Reserved_31_16:16; ///< |
| 7775 | } Field; ///< |
| 7776 | UINT32 Value; ///< |
| 7777 | } D18F2x09C_x0D0F_E006_STRUCT; |
| 7778 | |
| 7779 | |
| 7780 | // **** D18F2x09C_x0D0F_E013 Register Definition **** |
| 7781 | // Address |
| 7782 | #define D18F2x09C_x0D0F_E013_ADDRESS 0xd0fe013 |
| 7783 | |
| 7784 | // Type |
| 7785 | #define D18F2x09C_x0D0F_E013_TYPE TYPE_D18F2x09C |
| 7786 | // Field Data |
| 7787 | #define D18F2x09C_x0D0F_E013_PllRegWaitTime_OFFSET 0 |
| 7788 | #define D18F2x09C_x0D0F_E013_PllRegWaitTime_WIDTH 16 |
| 7789 | #define D18F2x09C_x0D0F_E013_PllRegWaitTime_MASK 0xffff |
| 7790 | #define D18F2x09C_x0D0F_E013_Reserved_31_16_OFFSET 16 |
| 7791 | #define D18F2x09C_x0D0F_E013_Reserved_31_16_WIDTH 16 |
| 7792 | #define D18F2x09C_x0D0F_E013_Reserved_31_16_MASK 0xffff0000 |
| 7793 | |
| 7794 | /// D18F2x09C_x0D0F_E013 |
| 7795 | typedef union { |
| 7796 | struct { ///< |
| 7797 | UINT32 PllRegWaitTime:16; ///< |
| 7798 | UINT32 Reserved_31_16:16; ///< |
| 7799 | } Field; ///< |
| 7800 | UINT32 Value; ///< |
| 7801 | } D18F2x09C_x0D0F_E013_STRUCT; |
| 7802 | |
| 7803 | |
| 7804 | // **** DxF0xE4_x02 Register Definition **** |
| 7805 | // Address |
| 7806 | #define DxF0xE4_x02_ADDRESS 0x2 |
| 7807 | |
| 7808 | // Type |
| 7809 | #define DxF0xE4_x02_TYPE TYPE_D4F0xE4 |
| 7810 | // Field Data |
| 7811 | #define DxF0xE4_x02_Reserved_14_0_OFFSET 0 |
| 7812 | #define DxF0xE4_x02_Reserved_14_0_WIDTH 15 |
| 7813 | #define DxF0xE4_x02_Reserved_14_0_MASK 0x7fff |
| 7814 | #define DxF0xE4_x02_RegsLcAllowTxL1Control_OFFSET 15 |
| 7815 | #define DxF0xE4_x02_RegsLcAllowTxL1Control_WIDTH 1 |
| 7816 | #define DxF0xE4_x02_RegsLcAllowTxL1Control_MASK 0x8000 |
| 7817 | #define DxF0xE4_x02_Reserved_31_16_OFFSET 16 |
| 7818 | #define DxF0xE4_x02_Reserved_31_16_WIDTH 16 |
| 7819 | #define DxF0xE4_x02_Reserved_31_16_MASK 0xffff0000 |
| 7820 | |
| 7821 | /// DxF0xE4_x02 |
| 7822 | typedef union { |
| 7823 | struct { ///< |
| 7824 | UINT32 Reserved_14_0:15; ///< |
| 7825 | UINT32 RegsLcAllowTxL1Control:1 ; ///< |
| 7826 | UINT32 Reserved_31_16:16; ///< |
| 7827 | } Field; ///< |
| 7828 | UINT32 Value; ///< |
| 7829 | } DxF0xE4_x02_STRUCT; |
| 7830 | |
| 7831 | // **** DxF0xE4_x20 Register Definition **** |
| 7832 | // Address |
| 7833 | #define DxF0xE4_x20_ADDRESS 0x20 |
| 7834 | |
| 7835 | // Type |
| 7836 | #define DxF0xE4_x20_TYPE TYPE_D4F0xE4 |
| 7837 | // Field Data |
| 7838 | #define DxF0xE4_x20_Reserved_14_0_OFFSET 0 |
| 7839 | #define DxF0xE4_x20_Reserved_14_0_WIDTH 15 |
| 7840 | #define DxF0xE4_x20_Reserved_14_0_MASK 0x7fff |
| 7841 | #define DxF0xE4_x20_TxFlushTlpDis_OFFSET 15 |
| 7842 | #define DxF0xE4_x20_TxFlushTlpDis_WIDTH 1 |
| 7843 | #define DxF0xE4_x20_TxFlushTlpDis_MASK 0x8000 |
| 7844 | #define DxF0xE4_x20_Reserved_31_16_OFFSET 16 |
| 7845 | #define DxF0xE4_x20_Reserved_31_16_WIDTH 16 |
| 7846 | #define DxF0xE4_x20_Reserved_31_16_MASK 0xffff0000 |
| 7847 | |
| 7848 | /// DxF0xE4_x20 |
| 7849 | typedef union { |
| 7850 | struct { ///< |
| 7851 | UINT32 Reserved_14_0:15; ///< |
| 7852 | UINT32 TxFlushTlpDis:1 ; ///< |
| 7853 | UINT32 Reserved_31_16:16; ///< |
| 7854 | } Field; ///< |
| 7855 | UINT32 Value; ///< |
| 7856 | } DxF0xE4_x20_STRUCT; |
| 7857 | |
| 7858 | // **** DxF0xE4_x50 Register Definition **** |
| 7859 | // Address |
| 7860 | #define DxF0xE4_x50_ADDRESS 0x50 |
| 7861 | |
| 7862 | // Type |
| 7863 | #define DxF0xE4_x50_TYPE TYPE_D4F0xE4 |
| 7864 | // Field Data |
| 7865 | #define DxF0xE4_x50_PortLaneReversal_OFFSET 0 |
| 7866 | #define DxF0xE4_x50_PortLaneReversal_WIDTH 1 |
| 7867 | #define DxF0xE4_x50_PortLaneReversal_MASK 0x1 |
| 7868 | #define DxF0xE4_x50_PhyLinkWidth_OFFSET 1 |
| 7869 | #define DxF0xE4_x50_PhyLinkWidth_WIDTH 6 |
| 7870 | #define DxF0xE4_x50_PhyLinkWidth_MASK 0x7e |
| 7871 | #define DxF0xE4_x50_Reserved_31_7_OFFSET 7 |
| 7872 | #define DxF0xE4_x50_Reserved_31_7_WIDTH 25 |
| 7873 | #define DxF0xE4_x50_Reserved_31_7_MASK 0xffffff80 |
| 7874 | |
| 7875 | /// DxF0xE4_x50 |
| 7876 | typedef union { |
| 7877 | struct { ///< |
| 7878 | UINT32 PortLaneReversal:1 ; ///< |
| 7879 | UINT32 PhyLinkWidth:6 ; ///< |
| 7880 | UINT32 Reserved_31_7:25; ///< |
| 7881 | } Field; ///< |
| 7882 | UINT32 Value; ///< |
| 7883 | } DxF0xE4_x50_STRUCT; |
| 7884 | |
| 7885 | // **** DxF0xE4_x70 Register Definition **** |
| 7886 | // Address |
| 7887 | #define DxF0xE4_x70_ADDRESS 0x70 |
| 7888 | |
| 7889 | // Type |
| 7890 | #define DxF0xE4_x70_TYPE TYPE_D4F0xE4 |
| 7891 | // Field Data |
| 7892 | #define DxF0xE4_x70_Reserved_15_0_OFFSET 0 |
| 7893 | #define DxF0xE4_x70_Reserved_15_0_WIDTH 16 |
| 7894 | #define DxF0xE4_x70_Reserved_15_0_MASK 0xffff |
| 7895 | #define DxF0xE4_x70_RxRcbCplTimeout_OFFSET 16 |
| 7896 | #define DxF0xE4_x70_RxRcbCplTimeout_WIDTH 3 |
| 7897 | #define DxF0xE4_x70_RxRcbCplTimeout_MASK 0x70000 |
| 7898 | #define DxF0xE4_x70_RxRcbCplTimeoutMode_OFFSET 19 |
| 7899 | #define DxF0xE4_x70_RxRcbCplTimeoutMode_WIDTH 1 |
| 7900 | #define DxF0xE4_x70_RxRcbCplTimeoutMode_MASK 0x80000 |
| 7901 | #define DxF0xE4_x70_Reserved_31_20_OFFSET 20 |
| 7902 | #define DxF0xE4_x70_Reserved_31_20_WIDTH 12 |
| 7903 | #define DxF0xE4_x70_Reserved_31_20_MASK 0xfff00000 |
| 7904 | |
| 7905 | /// DxF0xE4_x70 |
| 7906 | typedef union { |
| 7907 | struct { ///< |
| 7908 | UINT32 Reserved_15_0:16; ///< |
| 7909 | UINT32 RxRcbCplTimeout:3 ; ///< |
| 7910 | UINT32 RxRcbCplTimeoutMode:1 ; ///< |
| 7911 | UINT32 Reserved_31_20:12; ///< |
| 7912 | } Field; ///< |
| 7913 | UINT32 Value; ///< |
| 7914 | } DxF0xE4_x70_STRUCT; |
| 7915 | |
| 7916 | // **** DxF0xE4_xA0 Register Definition **** |
| 7917 | // Address |
| 7918 | #define DxF0xE4_xA0_ADDRESS 0xa0 |
| 7919 | |
| 7920 | // Type |
| 7921 | #define DxF0xE4_xA0_TYPE TYPE_D4F0xE4 |
| 7922 | // Field Data |
| 7923 | #define DxF0xE4_xA0_Reserved_3_0_OFFSET 0 |
| 7924 | #define DxF0xE4_xA0_Reserved_3_0_WIDTH 4 |
| 7925 | #define DxF0xE4_xA0_Reserved_3_0_MASK 0xf |
| 7926 | #define DxF0xE4_xA0_Lc16xClearTxPipe_OFFSET 4 |
| 7927 | #define DxF0xE4_xA0_Lc16xClearTxPipe_WIDTH 4 |
| 7928 | #define DxF0xE4_xA0_Lc16xClearTxPipe_MASK 0xf0 |
| 7929 | #define DxF0xE4_xA0_LcL0sInactivity_OFFSET 8 |
| 7930 | #define DxF0xE4_xA0_LcL0sInactivity_WIDTH 4 |
| 7931 | #define DxF0xE4_xA0_LcL0sInactivity_MASK 0xf00 |
| 7932 | #define DxF0xE4_xA0_LcL1Inactivity_OFFSET 12 |
| 7933 | #define DxF0xE4_xA0_LcL1Inactivity_WIDTH 4 |
| 7934 | #define DxF0xE4_xA0_LcL1Inactivity_MASK 0xf000 |
| 7935 | #define DxF0xE4_xA0_Reserved_22_16_OFFSET 16 |
| 7936 | #define DxF0xE4_xA0_Reserved_22_16_WIDTH 7 |
| 7937 | #define DxF0xE4_xA0_Reserved_22_16_MASK 0x7f0000 |
| 7938 | #define DxF0xE4_xA0_LcL1ImmediateAck_OFFSET 23 |
| 7939 | #define DxF0xE4_xA0_LcL1ImmediateAck_WIDTH 1 |
| 7940 | #define DxF0xE4_xA0_LcL1ImmediateAck_MASK 0x800000 |
| 7941 | #define DxF0xE4_xA0_Reserved_31_24_OFFSET 24 |
| 7942 | #define DxF0xE4_xA0_Reserved_31_24_WIDTH 8 |
| 7943 | #define DxF0xE4_xA0_Reserved_31_24_MASK 0xff000000 |
| 7944 | |
| 7945 | /// DxF0xE4_xA0 |
| 7946 | typedef union { |
| 7947 | struct { ///< |
| 7948 | UINT32 Reserved_3_0:4 ; ///< |
| 7949 | UINT32 Lc16xClearTxPipe:4 ; ///< |
| 7950 | UINT32 LcL0sInactivity:4 ; ///< |
| 7951 | UINT32 LcL1Inactivity:4 ; ///< |
| 7952 | UINT32 Reserved_22_16:7 ; ///< |
| 7953 | UINT32 LcL1ImmediateAck:1 ; ///< |
| 7954 | UINT32 Reserved_31_24:8 ; ///< |
| 7955 | } Field; ///< |
| 7956 | UINT32 Value; ///< |
| 7957 | } DxF0xE4_xA0_STRUCT; |
| 7958 | |
| 7959 | // **** DxF0xE4_xA1 Register Definition **** |
| 7960 | // Address |
| 7961 | #define DxF0xE4_xA1_ADDRESS 0xa1 |
| 7962 | |
| 7963 | // Type |
| 7964 | #define DxF0xE4_xA1_TYPE TYPE_D4F0xE4 |
| 7965 | // Field Data |
| 7966 | #define DxF0xE4_xA1_Reserved_10_0_OFFSET 0 |
| 7967 | #define DxF0xE4_xA1_Reserved_10_0_WIDTH 11 |
| 7968 | #define DxF0xE4_xA1_Reserved_10_0_MASK 0x7ff |
| 7969 | #define DxF0xE4_xA1_LcDontGotoL0sifL1Armed_OFFSET 11 |
| 7970 | #define DxF0xE4_xA1_LcDontGotoL0sifL1Armed_WIDTH 1 |
| 7971 | #define DxF0xE4_xA1_LcDontGotoL0sifL1Armed_MASK 0x800 |
| 7972 | #define DxF0xE4_xA1_LcInitSpdChgWithCsrEn_OFFSET 12 |
| 7973 | #define DxF0xE4_xA1_LcInitSpdChgWithCsrEn_WIDTH 1 |
| 7974 | #define DxF0xE4_xA1_LcInitSpdChgWithCsrEn_MASK 0x1000 |
| 7975 | #define DxF0xE4_xA1_Reserved_31_13_OFFSET 13 |
| 7976 | #define DxF0xE4_xA1_Reserved_31_13_WIDTH 19 |
| 7977 | #define DxF0xE4_xA1_Reserved_31_13_MASK 0xffffe000 |
| 7978 | |
| 7979 | /// DxF0xE4_xA1 |
| 7980 | typedef union { |
| 7981 | struct { ///< |
| 7982 | UINT32 Reserved_10_0:11; ///< |
| 7983 | UINT32 LcDontGotoL0sifL1Armed:1 ; ///< |
| 7984 | UINT32 LcInitSpdChgWithCsrEn:1 ; ///< |
| 7985 | UINT32 Reserved_31_13:19; ///< |
| 7986 | } Field; ///< |
| 7987 | UINT32 Value; ///< |
| 7988 | } DxF0xE4_xA1_STRUCT; |
| 7989 | |
| 7990 | // **** DxF0xE4_xA2 Register Definition **** |
| 7991 | // Address |
| 7992 | #define DxF0xE4_xA2_ADDRESS 0xa2 |
| 7993 | |
| 7994 | // Type |
| 7995 | #define DxF0xE4_xA2_TYPE TYPE_D4F0xE4 |
| 7996 | // Field Data |
| 7997 | #define DxF0xE4_xA2_LcLinkWidth_OFFSET 0 |
| 7998 | #define DxF0xE4_xA2_LcLinkWidth_WIDTH 3 |
| 7999 | #define DxF0xE4_xA2_LcLinkWidth_MASK 0x7 |
| 8000 | #define DxF0xE4_xA2_Reserved_3_3_OFFSET 3 |
| 8001 | #define DxF0xE4_xA2_Reserved_3_3_WIDTH 1 |
| 8002 | #define DxF0xE4_xA2_Reserved_3_3_MASK 0x8 |
| 8003 | #define DxF0xE4_xA2_LcLinkWidthRd_OFFSET 4 |
| 8004 | #define DxF0xE4_xA2_LcLinkWidthRd_WIDTH 3 |
| 8005 | #define DxF0xE4_xA2_LcLinkWidthRd_MASK 0x70 |
| 8006 | #define DxF0xE4_xA2_LcReconfigArcMissingEscape_OFFSET 7 |
| 8007 | #define DxF0xE4_xA2_LcReconfigArcMissingEscape_WIDTH 1 |
| 8008 | #define DxF0xE4_xA2_LcReconfigArcMissingEscape_MASK 0x80 |
| 8009 | #define DxF0xE4_xA2_LcReconfigNow_OFFSET 8 |
| 8010 | #define DxF0xE4_xA2_LcReconfigNow_WIDTH 1 |
| 8011 | #define DxF0xE4_xA2_LcReconfigNow_MASK 0x100 |
| 8012 | #define DxF0xE4_xA2_LcRenegotiationSupport_OFFSET 9 |
| 8013 | #define DxF0xE4_xA2_LcRenegotiationSupport_WIDTH 1 |
| 8014 | #define DxF0xE4_xA2_LcRenegotiationSupport_MASK 0x200 |
| 8015 | #define DxF0xE4_xA2_LcRenegotiateEn_OFFSET 10 |
| 8016 | #define DxF0xE4_xA2_LcRenegotiateEn_WIDTH 1 |
| 8017 | #define DxF0xE4_xA2_LcRenegotiateEn_MASK 0x400 |
| 8018 | #define DxF0xE4_xA2_LcShortReconfigEn_OFFSET 11 |
| 8019 | #define DxF0xE4_xA2_LcShortReconfigEn_WIDTH 1 |
| 8020 | #define DxF0xE4_xA2_LcShortReconfigEn_MASK 0x800 |
| 8021 | #define DxF0xE4_xA2_LcUpconfigureSupport_OFFSET 12 |
| 8022 | #define DxF0xE4_xA2_LcUpconfigureSupport_WIDTH 1 |
| 8023 | #define DxF0xE4_xA2_LcUpconfigureSupport_MASK 0x1000 |
| 8024 | #define DxF0xE4_xA2_LcUpconfigureDis_OFFSET 13 |
| 8025 | #define DxF0xE4_xA2_LcUpconfigureDis_WIDTH 1 |
| 8026 | #define DxF0xE4_xA2_LcUpconfigureDis_MASK 0x2000 |
| 8027 | #define DxF0xE4_xA2_Reserved_19_14_OFFSET 14 |
| 8028 | #define DxF0xE4_xA2_Reserved_19_14_WIDTH 6 |
| 8029 | #define DxF0xE4_xA2_Reserved_19_14_MASK 0xfc000 |
| 8030 | #define DxF0xE4_xA2_LcUpconfigCapable_OFFSET 20 |
| 8031 | #define DxF0xE4_xA2_LcUpconfigCapable_WIDTH 1 |
| 8032 | #define DxF0xE4_xA2_LcUpconfigCapable_MASK 0x100000 |
| 8033 | #define DxF0xE4_xA2_LcDynLanesPwrState_OFFSET 21 |
| 8034 | #define DxF0xE4_xA2_LcDynLanesPwrState_WIDTH 2 |
| 8035 | #define DxF0xE4_xA2_LcDynLanesPwrState_MASK 0x600000 |
| 8036 | #define DxF0xE4_xA2_Reserved_31_23_OFFSET 23 |
| 8037 | #define DxF0xE4_xA2_Reserved_31_23_WIDTH 9 |
| 8038 | #define DxF0xE4_xA2_Reserved_31_23_MASK 0xff800000 |
| 8039 | |
| 8040 | /// DxF0xE4_xA2 |
| 8041 | typedef union { |
| 8042 | struct { ///< |
| 8043 | UINT32 LcLinkWidth:3 ; ///< |
| 8044 | UINT32 Reserved_3_3:1 ; ///< |
| 8045 | UINT32 LcLinkWidthRd:3 ; ///< |
| 8046 | UINT32 LcReconfigArcMissingEscape:1 ; ///< |
| 8047 | UINT32 LcReconfigNow:1 ; ///< |
| 8048 | UINT32 LcRenegotiationSupport:1 ; ///< |
| 8049 | UINT32 LcRenegotiateEn:1 ; ///< |
| 8050 | UINT32 LcShortReconfigEn:1 ; ///< |
| 8051 | UINT32 LcUpconfigureSupport:1 ; ///< |
| 8052 | UINT32 LcUpconfigureDis:1 ; ///< |
| 8053 | UINT32 Reserved_19_14:6 ; ///< |
| 8054 | UINT32 LcUpconfigCapable:1 ; ///< |
| 8055 | UINT32 LcDynLanesPwrState:2 ; ///< |
| 8056 | UINT32 Reserved_31_23:9 ; ///< |
| 8057 | } Field; ///< |
| 8058 | UINT32 Value; ///< |
| 8059 | } DxF0xE4_xA2_STRUCT; |
| 8060 | |
| 8061 | // **** DxF0xE4_xA3 Register Definition **** |
| 8062 | // Address |
| 8063 | #define DxF0xE4_xA3_ADDRESS 0xa3 |
| 8064 | |
| 8065 | // Type |
| 8066 | #define DxF0xE4_xA3_TYPE TYPE_D4F0xE4 |
| 8067 | // Field Data |
| 8068 | #define DxF0xE4_xA3_Reserved_8_0_OFFSET 0 |
| 8069 | #define DxF0xE4_xA3_Reserved_8_0_WIDTH 9 |
| 8070 | #define DxF0xE4_xA3_Reserved_8_0_MASK 0x1ff |
| 8071 | #define DxF0xE4_xA3_LcXmitFtsBeforeRecovery_OFFSET 9 |
| 8072 | #define DxF0xE4_xA3_LcXmitFtsBeforeRecovery_WIDTH 1 |
| 8073 | #define DxF0xE4_xA3_LcXmitFtsBeforeRecovery_MASK 0x200 |
| 8074 | #define DxF0xE4_xA3_Reserved_31_10_OFFSET 10 |
| 8075 | #define DxF0xE4_xA3_Reserved_31_10_WIDTH 22 |
| 8076 | #define DxF0xE4_xA3_Reserved_31_10_MASK 0xfffffc00 |
| 8077 | |
| 8078 | /// DxF0xE4_xA3 |
| 8079 | typedef union { |
| 8080 | struct { ///< |
| 8081 | UINT32 Reserved_8_0:9 ; ///< |
| 8082 | UINT32 LcXmitFtsBeforeRecovery:1 ; ///< |
| 8083 | UINT32 Reserved_31_10:22; ///< |
| 8084 | } Field; ///< |
| 8085 | UINT32 Value; ///< |
| 8086 | } DxF0xE4_xA3_STRUCT; |
| 8087 | |
| 8088 | /// DxF0xE4_xA4 |
| 8089 | typedef union { |
| 8090 | struct { ///< |
| 8091 | UINT32 LcGen2EnStrap:1 ; ///< |
| 8092 | UINT32 Reserved_3_1:3 ; ///< |
| 8093 | UINT32 LcForceDisSwSpeedChange:1 ; ///< |
| 8094 | UINT32 Reserved_6_5:2 ; ///< |
| 8095 | UINT32 LcInitiateLinkSpeedChange:1 ; ///< |
| 8096 | UINT32 Reserved_9_8:2 ; ///< |
| 8097 | UINT32 LcSpeedChangeAttemptFailed:1 ; ///< |
| 8098 | UINT32 Reserved_17_11:7 ; ///< |
| 8099 | UINT32 LcGoToRecovery:1 ; ///< |
| 8100 | UINT32 Reserved_23_19:5 ; ///< |
| 8101 | UINT32 LcOtherSideSupportsGen2:1 ; ///< |
| 8102 | UINT32 Reserved_28_25:4 ; ///< |
| 8103 | UINT32 LcMultUpstreamAutoSpdChngEn:1 ; ///< |
| 8104 | UINT32 Reserved_31_30:2 ; ///< |
| 8105 | } Field; ///< |
| 8106 | UINT32 Value; ///< |
| 8107 | } ex548_STRUCT; |
| 8108 | |
| 8109 | // **** DxF0xE4_xA5 Register Definition **** |
| 8110 | // Address |
| 8111 | #define DxF0xE4_xA5_ADDRESS 0xa5 |
| 8112 | |
| 8113 | // Type |
| 8114 | #define DxF0xE4_xA5_TYPE TYPE_D4F0xE4 |
| 8115 | // Field Data |
| 8116 | #define DxF0xE4_xA5_LcCurrentState_OFFSET 0 |
| 8117 | #define DxF0xE4_xA5_LcCurrentState_WIDTH 6 |
| 8118 | #define DxF0xE4_xA5_LcCurrentState_MASK 0x3f |
| 8119 | #define DxF0xE4_xA5_Reserved_7_6_OFFSET 6 |
| 8120 | #define DxF0xE4_xA5_Reserved_7_6_WIDTH 2 |
| 8121 | #define DxF0xE4_xA5_Reserved_7_6_MASK 0xc0 |
| 8122 | #define DxF0xE4_xA5_LcPrevState1_OFFSET 8 |
| 8123 | #define DxF0xE4_xA5_LcPrevState1_WIDTH 6 |
| 8124 | #define DxF0xE4_xA5_LcPrevState1_MASK 0x3f00 |
| 8125 | #define DxF0xE4_xA5_Reserved_15_14_OFFSET 14 |
| 8126 | #define DxF0xE4_xA5_Reserved_15_14_WIDTH 2 |
| 8127 | #define DxF0xE4_xA5_Reserved_15_14_MASK 0xc000 |
| 8128 | #define DxF0xE4_xA5_LcPrevState2_OFFSET 16 |
| 8129 | #define DxF0xE4_xA5_LcPrevState2_WIDTH 6 |
| 8130 | #define DxF0xE4_xA5_LcPrevState2_MASK 0x3f0000 |
| 8131 | #define DxF0xE4_xA5_Reserved_23_22_OFFSET 22 |
| 8132 | #define DxF0xE4_xA5_Reserved_23_22_WIDTH 2 |
| 8133 | #define DxF0xE4_xA5_Reserved_23_22_MASK 0xc00000 |
| 8134 | #define DxF0xE4_xA5_LcPrevState3_OFFSET 24 |
| 8135 | #define DxF0xE4_xA5_LcPrevState3_WIDTH 6 |
| 8136 | #define DxF0xE4_xA5_LcPrevState3_MASK 0x3f000000 |
| 8137 | #define DxF0xE4_xA5_Reserved_31_30_OFFSET 30 |
| 8138 | #define DxF0xE4_xA5_Reserved_31_30_WIDTH 2 |
| 8139 | #define DxF0xE4_xA5_Reserved_31_30_MASK 0xc0000000 |
| 8140 | |
| 8141 | /// DxF0xE4_xA5 |
| 8142 | typedef union { |
| 8143 | struct { ///< |
| 8144 | UINT32 LcCurrentState:6 ; ///< |
| 8145 | UINT32 Reserved_7_6:2 ; ///< |
| 8146 | UINT32 LcPrevState1:6 ; ///< |
| 8147 | UINT32 Reserved_15_14:2 ; ///< |
| 8148 | UINT32 LcPrevState2:6 ; ///< |
| 8149 | UINT32 Reserved_23_22:2 ; ///< |
| 8150 | UINT32 LcPrevState3:6 ; ///< |
| 8151 | UINT32 Reserved_31_30:2 ; ///< |
| 8152 | } Field; ///< |
| 8153 | UINT32 Value; ///< |
| 8154 | } DxF0xE4_xA5_STRUCT; |
| 8155 | |
| 8156 | // **** DxF0xE4_xB1 Register Definition **** |
| 8157 | // Address |
| 8158 | #define DxF0xE4_xB1_ADDRESS 0xb1 |
| 8159 | |
| 8160 | // Type |
| 8161 | #define DxF0xE4_xB1_TYPE TYPE_D4F0xE4 |
| 8162 | // Field Data |
| 8163 | #define DxF0xE4_xB1_Reserved_18_0_OFFSET 0 |
| 8164 | #define DxF0xE4_xB1_Reserved_18_0_WIDTH 19 |
| 8165 | #define DxF0xE4_xB1_Reserved_18_0_MASK 0x7ffff |
| 8166 | #define DxF0xE4_xB1_LcDeassertRxEnInL0s_OFFSET 19 |
| 8167 | #define DxF0xE4_xB1_LcDeassertRxEnInL0s_WIDTH 1 |
| 8168 | #define DxF0xE4_xB1_LcDeassertRxEnInL0s_MASK 0x80000 |
| 8169 | #define DxF0xE4_xB1_LcBlockElIdleinL0_OFFSET 20 |
| 8170 | #define DxF0xE4_xB1_LcBlockElIdleinL0_WIDTH 1 |
| 8171 | #define DxF0xE4_xB1_LcBlockElIdleinL0_MASK 0x100000 |
| 8172 | #define DxF0xE4_xB1_Reserved_31_21_OFFSET 21 |
| 8173 | #define DxF0xE4_xB1_Reserved_31_21_WIDTH 11 |
| 8174 | #define DxF0xE4_xB1_Reserved_31_21_MASK 0xffe00000 |
| 8175 | |
| 8176 | /// DxF0xE4_xB1 |
| 8177 | typedef union { |
| 8178 | struct { ///< |
| 8179 | UINT32 Reserved_18_0:19; ///< |
| 8180 | UINT32 LcDeassertRxEnInL0s:1 ; ///< |
| 8181 | UINT32 LcBlockElIdleinL0:1 ; ///< |
| 8182 | UINT32 Reserved_31_21:11; ///< |
| 8183 | } Field; ///< |
| 8184 | UINT32 Value; ///< |
| 8185 | } DxF0xE4_xB1_STRUCT; |
| 8186 | |
| 8187 | // **** DxF0xE4_xC0 Register Definition **** |
| 8188 | // Address |
| 8189 | #define DxF0xE4_xC0_ADDRESS 0xc0 |
| 8190 | |
| 8191 | // Type |
| 8192 | #define DxF0xE4_xC0_TYPE TYPE_D4F0xE4 |
| 8193 | // Field Data |
| 8194 | #define DxF0xE4_xC0_Reserved_12_0_OFFSET 0 |
| 8195 | #define DxF0xE4_xC0_Reserved_12_0_WIDTH 13 |
| 8196 | #define DxF0xE4_xC0_Reserved_12_0_MASK 0x1fff |
| 8197 | #define DxF0xE4_xC0_StrapForceCompliance_OFFSET 13 |
| 8198 | #define DxF0xE4_xC0_StrapForceCompliance_WIDTH 1 |
| 8199 | #define DxF0xE4_xC0_StrapForceCompliance_MASK 0x2000 |
| 8200 | #define DxF0xE4_xC0_Reserved_14_14_OFFSET 14 |
| 8201 | #define DxF0xE4_xC0_Reserved_14_14_WIDTH 1 |
| 8202 | #define DxF0xE4_xC0_Reserved_14_14_MASK 0x4000 |
| 8203 | #define DxF0xE4_xC0_StrapAutoRcSpeedNegotiationDis_OFFSET 15 |
| 8204 | #define DxF0xE4_xC0_StrapAutoRcSpeedNegotiationDis_WIDTH 1 |
| 8205 | #define DxF0xE4_xC0_StrapAutoRcSpeedNegotiationDis_MASK 0x8000 |
| 8206 | #define DxF0xE4_xC0_Reserved_31_16_OFFSET 16 |
| 8207 | #define DxF0xE4_xC0_Reserved_31_16_WIDTH 16 |
| 8208 | #define DxF0xE4_xC0_Reserved_31_16_MASK 0xffff0000 |
| 8209 | |
| 8210 | /// DxF0xE4_xC0 |
| 8211 | typedef union { |
| 8212 | struct { ///< |
| 8213 | UINT32 Reserved_12_0:13; ///< |
| 8214 | UINT32 StrapForceCompliance:1 ; ///< |
| 8215 | UINT32 Reserved_14_14:1 ; ///< |
| 8216 | UINT32 StrapAutoRcSpeedNegotiationDis:1 ; ///< |
| 8217 | UINT32 Reserved_31_16:16; ///< |
| 8218 | } Field; ///< |
| 8219 | UINT32 Value; ///< |
| 8220 | } DxF0xE4_xC0_STRUCT; |
| 8221 | |
| 8222 | |
| 8223 | |
| 8224 | // **** GMMx4D0 Register Definition **** |
| 8225 | // Address |
| 8226 | #define GMMx4D0_ADDRESS 0x4d0 |
| 8227 | |
| 8228 | // Type |
| 8229 | #define GMMx4D0_TYPE TYPE_GMM |
| 8230 | // Field Data |
| 8231 | #define GMMx4D0_DispclkDccgGateDisable_OFFSET 0 |
| 8232 | #define GMMx4D0_DispclkDccgGateDisable_WIDTH 1 |
| 8233 | #define GMMx4D0_DispclkDccgGateDisable_MASK 0x1 |
| 8234 | #define GMMx4D0_DispclkRDccgGateDisable_OFFSET 1 |
| 8235 | #define GMMx4D0_DispclkRDccgGateDisable_WIDTH 1 |
| 8236 | #define GMMx4D0_DispclkRDccgGateDisable_MASK 0x2 |
| 8237 | #define GMMx4D0_SclkGateDisable_OFFSET 2 |
| 8238 | #define GMMx4D0_SclkGateDisable_WIDTH 1 |
| 8239 | #define GMMx4D0_SclkGateDisable_MASK 0x4 |
| 8240 | #define GMMx4D0_Reserved_7_3_OFFSET 3 |
| 8241 | #define GMMx4D0_Reserved_7_3_WIDTH 5 |
| 8242 | #define GMMx4D0_Reserved_7_3_MASK 0xf8 |
| 8243 | #define GMMx4D0_SymclkaGateDisable_OFFSET 8 |
| 8244 | #define GMMx4D0_SymclkaGateDisable_WIDTH 1 |
| 8245 | #define GMMx4D0_SymclkaGateDisable_MASK 0x100 |
| 8246 | #define GMMx4D0_SymclkbGateDisable_OFFSET 9 |
| 8247 | #define GMMx4D0_SymclkbGateDisable_WIDTH 1 |
| 8248 | #define GMMx4D0_SymclkbGateDisable_MASK 0x200 |
| 8249 | #define GMMx4D0_Reserved_31_10_OFFSET 10 |
| 8250 | #define GMMx4D0_Reserved_31_10_WIDTH 22 |
| 8251 | #define GMMx4D0_Reserved_31_10_MASK 0xfffffc00 |
| 8252 | |
| 8253 | /// GMMx4D0 |
| 8254 | typedef union { |
| 8255 | struct { ///< |
| 8256 | UINT32 DispclkDccgGateDisable:1 ; ///< |
| 8257 | UINT32 DispclkRDccgGateDisable:1 ; ///< |
| 8258 | UINT32 SclkGateDisable:1 ; ///< |
| 8259 | UINT32 Reserved_7_3:5 ; ///< |
| 8260 | UINT32 SymclkaGateDisable:1 ; ///< |
| 8261 | UINT32 SymclkbGateDisable:1 ; ///< |
| 8262 | UINT32 Reserved_31_10:22; ///< |
| 8263 | } Field; ///< |
| 8264 | UINT32 Value; ///< |
| 8265 | } GMMx4D0_STRUCT; |
| 8266 | |
| 8267 | // **** GMMx770 Register Definition **** |
| 8268 | // Address |
| 8269 | #define GMMx770_ADDRESS 0x770 |
| 8270 | |
| 8271 | // Type |
| 8272 | #define GMMx770_TYPE TYPE_GMM |
| 8273 | // Field Data |
| 8274 | #define GMMx770_VoltageChangeReq_OFFSET 0 |
| 8275 | #define GMMx770_VoltageChangeReq_WIDTH 1 |
| 8276 | #define GMMx770_VoltageChangeReq_MASK 0x1 |
| 8277 | #define GMMx770_VoltageLevel_OFFSET 1 |
| 8278 | #define GMMx770_VoltageLevel_WIDTH 2 |
| 8279 | #define GMMx770_VoltageLevel_MASK 0x6 |
| 8280 | #define GMMx770_VoltageChangeEn_OFFSET 3 |
| 8281 | #define GMMx770_VoltageChangeEn_WIDTH 1 |
| 8282 | #define GMMx770_VoltageChangeEn_MASK 0x8 |
| 8283 | #define GMMx770_VoltageForceEn_OFFSET 4 |
| 8284 | #define GMMx770_VoltageForceEn_WIDTH 1 |
| 8285 | #define GMMx770_VoltageForceEn_MASK 0x10 |
| 8286 | #define GMMx770_Reserved_31_5_OFFSET 5 |
| 8287 | #define GMMx770_Reserved_31_5_WIDTH 27 |
| 8288 | #define GMMx770_Reserved_31_5_MASK 0xffffffe0 |
| 8289 | |
| 8290 | /// GMMx770 |
| 8291 | typedef union { |
| 8292 | struct { ///< |
| 8293 | UINT32 VoltageChangeReq:1 ; ///< |
| 8294 | UINT32 VoltageLevel:2 ; ///< |
| 8295 | UINT32 VoltageChangeEn:1 ; ///< |
| 8296 | UINT32 VoltageForceEn:1 ; ///< |
| 8297 | UINT32 Reserved_31_5:27; ///< |
| 8298 | } Field; ///< |
| 8299 | UINT32 Value; ///< |
| 8300 | } GMMx770_STRUCT; |
| 8301 | |
| 8302 | // **** GMMx774 Register Definition **** |
| 8303 | // Address |
| 8304 | #define GMMx774_ADDRESS 0x774 |
| 8305 | |
| 8306 | // Type |
| 8307 | #define GMMx774_TYPE TYPE_GMM |
| 8308 | // Field Data |
| 8309 | #define GMMx774_VoltageChangeAck_OFFSET 0 |
| 8310 | #define GMMx774_VoltageChangeAck_WIDTH 1 |
| 8311 | #define GMMx774_VoltageChangeAck_MASK 0x1 |
| 8312 | #define GMMx774_CurrentVoltageLevel_OFFSET 1 |
| 8313 | #define GMMx774_CurrentVoltageLevel_WIDTH 2 |
| 8314 | #define GMMx774_CurrentVoltageLevel_MASK 0x6 |
| 8315 | #define GMMx774_Reserved_31_3_OFFSET 3 |
| 8316 | #define GMMx774_Reserved_31_3_WIDTH 29 |
| 8317 | #define GMMx774_Reserved_31_3_MASK 0xfffffff8 |
| 8318 | |
| 8319 | /// GMMx774 |
| 8320 | typedef union { |
| 8321 | struct { ///< |
| 8322 | UINT32 VoltageChangeAck:1 ; ///< |
| 8323 | UINT32 CurrentVoltageLevel:2 ; ///< |
| 8324 | UINT32 Reserved_31_3:29; ///< |
| 8325 | } Field; ///< |
| 8326 | UINT32 Value; ///< |
| 8327 | } GMMx774_STRUCT; |
| 8328 | |
| 8329 | // **** GMMx15C0 Register Definition **** |
| 8330 | // Address |
| 8331 | #define GMMx15C0_ADDRESS 0x15c0 |
| 8332 | |
| 8333 | // Type |
| 8334 | #define GMMx15C0_TYPE TYPE_GMM |
| 8335 | // Field Data |
| 8336 | #define GMMx15C0_OnDly_OFFSET 0 |
| 8337 | #define GMMx15C0_OnDly_WIDTH 6 |
| 8338 | #define GMMx15C0_OnDly_MASK 0x3f |
| 8339 | #define GMMx15C0_OffDly_OFFSET 6 |
| 8340 | #define GMMx15C0_OffDly_WIDTH 6 |
| 8341 | #define GMMx15C0_OffDly_MASK 0xfc0 |
| 8342 | #define GMMx15C0_RdyDly_OFFSET 12 |
| 8343 | #define GMMx15C0_RdyDly_WIDTH 6 |
| 8344 | #define GMMx15C0_RdyDly_MASK 0x3f000 |
| 8345 | #define GMMx15C0_Enable_OFFSET 18 |
| 8346 | #define GMMx15C0_Enable_WIDTH 1 |
| 8347 | #define GMMx15C0_Enable_MASK 0x40000 |
| 8348 | #define GMMx15C0_Reserved_31_19_OFFSET 19 |
| 8349 | #define GMMx15C0_Reserved_31_19_WIDTH 13 |
| 8350 | #define GMMx15C0_Reserved_31_19_MASK 0xfff80000 |
| 8351 | |
| 8352 | /// GMMx15C0 |
| 8353 | typedef union { |
| 8354 | struct { ///< |
| 8355 | UINT32 OnDly:6 ; ///< |
| 8356 | UINT32 OffDly:6 ; ///< |
| 8357 | UINT32 RdyDly:6 ; ///< |
| 8358 | UINT32 Enable:1 ; ///< |
| 8359 | UINT32 Reserved_31_19:13; ///< |
| 8360 | } Field; ///< |
| 8361 | UINT32 Value; ///< |
| 8362 | } GMMx15C0_STRUCT; |
| 8363 | |
| 8364 | |
| 8365 | |
| 8366 | |
| 8367 | |
| 8368 | // **** GMMx2024 Register Definition **** |
| 8369 | // Address |
| 8370 | #define GMMx2024_ADDRESS 0x2024 |
| 8371 | |
| 8372 | // Type |
| 8373 | #define GMMx2024_TYPE TYPE_GMM |
| 8374 | // Field Data |
| 8375 | #define GMMx2024_Base_OFFSET 0 |
| 8376 | #define GMMx2024_Base_WIDTH 16 |
| 8377 | #define GMMx2024_Base_MASK 0xffff |
| 8378 | #define GMMx2024_Top_OFFSET 16 |
| 8379 | #define GMMx2024_Top_WIDTH 16 |
| 8380 | #define GMMx2024_Top_MASK 0xffff0000 |
| 8381 | |
| 8382 | /// GMMx2024 |
| 8383 | typedef union { |
| 8384 | struct { ///< |
| 8385 | UINT32 Base:16; ///< |
| 8386 | UINT32 Top:16; ///< |
| 8387 | } Field; ///< |
| 8388 | UINT32 Value; ///< |
| 8389 | } GMMx2024_STRUCT; |
| 8390 | |
| 8391 | |
| 8392 | |
| 8393 | |
| 8394 | |
| 8395 | |
| 8396 | |
| 8397 | |
| 8398 | |
| 8399 | |
| 8400 | |
| 8401 | |
| 8402 | |
| 8403 | |
| 8404 | |
| 8405 | |
| 8406 | |
| 8407 | |
| 8408 | |
| 8409 | |
| 8410 | |
| 8411 | |
| 8412 | |
| 8413 | |
| 8414 | |
| 8415 | |
| 8416 | |
| 8417 | |
| 8418 | |
| 8419 | |
| 8420 | |
| 8421 | |
| 8422 | |
| 8423 | |
| 8424 | |
| 8425 | |
| 8426 | |
| 8427 | |
| 8428 | |
| 8429 | |
| 8430 | // **** GMMx2814 Register Definition **** |
| 8431 | // Address |
| 8432 | #define GMMx2814_ADDRESS 0x2814 |
| 8433 | |
| 8434 | // Type |
| 8435 | #define GMMx2814_TYPE TYPE_GMM |
| 8436 | // Field Data |
| 8437 | #define GMMx2814_WriteClks_OFFSET 0 |
| 8438 | #define GMMx2814_WriteClks_WIDTH 9 |
| 8439 | #define GMMx2814_WriteClks_MASK 0x1ff |
| 8440 | #define GMMx2814_UvdHarshPriority_OFFSET 9 |
| 8441 | #define GMMx2814_UvdHarshPriority_WIDTH 1 |
| 8442 | #define GMMx2814_UvdHarshPriority_MASK 0x200 |
| 8443 | #define GMMx2814_Reserved_31_10_OFFSET 10 |
| 8444 | #define GMMx2814_Reserved_31_10_WIDTH 22 |
| 8445 | #define GMMx2814_Reserved_31_10_MASK 0xfffffc00 |
| 8446 | |
| 8447 | /// GMMx2814 |
| 8448 | typedef union { |
| 8449 | struct { ///< |
| 8450 | UINT32 WriteClks:9 ; ///< |
| 8451 | UINT32 UvdHarshPriority:1 ; ///< |
| 8452 | UINT32 Reserved_31_10:22; ///< |
| 8453 | } Field; ///< |
| 8454 | UINT32 Value; ///< |
| 8455 | } GMMx2814_STRUCT; |
| 8456 | |
| 8457 | // **** GMMx281C Register Definition **** |
| 8458 | // Address |
| 8459 | #define GMMx281C_ADDRESS 0x281c |
| 8460 | |
| 8461 | // Type |
| 8462 | #define GMMx281C_TYPE TYPE_GMM |
| 8463 | // Field Data |
| 8464 | #define GMMx281C_CSEnable_OFFSET 0 |
| 8465 | #define GMMx281C_CSEnable_WIDTH 1 |
| 8466 | #define GMMx281C_CSEnable_MASK 0x1 |
| 8467 | #define GMMx281C_Reserved_4_1_OFFSET 1 |
| 8468 | #define GMMx281C_Reserved_4_1_WIDTH 4 |
| 8469 | #define GMMx281C_Reserved_4_1_MASK 0x1e |
| 8470 | #define GMMx281C_BaseAddr_21_13__OFFSET 5 |
| 8471 | #define GMMx281C_BaseAddr_21_13__WIDTH 9 |
| 8472 | #define GMMx281C_BaseAddr_21_13__MASK 0x3fe0 |
| 8473 | #define GMMx281C_Reserved_18_14_OFFSET 14 |
| 8474 | #define GMMx281C_Reserved_18_14_WIDTH 5 |
| 8475 | #define GMMx281C_Reserved_18_14_MASK 0x7c000 |
| 8476 | #define GMMx281C_BaseAddr_36_27__OFFSET 19 |
| 8477 | #define GMMx281C_BaseAddr_36_27__WIDTH 10 |
| 8478 | #define GMMx281C_BaseAddr_36_27__MASK 0x1ff80000 |
| 8479 | #define GMMx281C_Reserved_31_29_OFFSET 29 |
| 8480 | #define GMMx281C_Reserved_31_29_WIDTH 3 |
| 8481 | #define GMMx281C_Reserved_31_29_MASK 0xe0000000 |
| 8482 | |
| 8483 | /// GMMx281C |
| 8484 | typedef union { |
| 8485 | struct { ///< |
| 8486 | UINT32 CSEnable:1 ; ///< |
| 8487 | UINT32 Reserved_4_1:4 ; ///< |
| 8488 | UINT32 BaseAddr_21_13_:9 ; ///< |
| 8489 | UINT32 Reserved_18_14:5 ; ///< |
| 8490 | UINT32 BaseAddr_36_27_:10; ///< |
| 8491 | UINT32 Reserved_31_29:3 ; ///< |
| 8492 | } Field; ///< |
| 8493 | UINT32 Value; ///< |
| 8494 | } GMMx281C_STRUCT; |
| 8495 | |
| 8496 | // **** GMMx2820 Register Definition **** |
| 8497 | // Address |
| 8498 | #define GMMx2820_ADDRESS 0x2820 |
| 8499 | |
| 8500 | // Type |
| 8501 | #define GMMx2820_TYPE TYPE_GMM |
| 8502 | // Field Data |
| 8503 | #define GMMx2820_CSEnable_OFFSET 0 |
| 8504 | #define GMMx2820_CSEnable_WIDTH 1 |
| 8505 | #define GMMx2820_CSEnable_MASK 0x1 |
| 8506 | #define GMMx2820_Reserved_4_1_OFFSET 1 |
| 8507 | #define GMMx2820_Reserved_4_1_WIDTH 4 |
| 8508 | #define GMMx2820_Reserved_4_1_MASK 0x1e |
| 8509 | #define GMMx2820_BaseAddr_21_13__OFFSET 5 |
| 8510 | #define GMMx2820_BaseAddr_21_13__WIDTH 9 |
| 8511 | #define GMMx2820_BaseAddr_21_13__MASK 0x3fe0 |
| 8512 | #define GMMx2820_Reserved_18_14_OFFSET 14 |
| 8513 | #define GMMx2820_Reserved_18_14_WIDTH 5 |
| 8514 | #define GMMx2820_Reserved_18_14_MASK 0x7c000 |
| 8515 | #define GMMx2820_BaseAddr_36_27__OFFSET 19 |
| 8516 | #define GMMx2820_BaseAddr_36_27__WIDTH 10 |
| 8517 | #define GMMx2820_BaseAddr_36_27__MASK 0x1ff80000 |
| 8518 | #define GMMx2820_Reserved_31_29_OFFSET 29 |
| 8519 | #define GMMx2820_Reserved_31_29_WIDTH 3 |
| 8520 | #define GMMx2820_Reserved_31_29_MASK 0xe0000000 |
| 8521 | |
| 8522 | /// GMMx2820 |
| 8523 | typedef union { |
| 8524 | struct { ///< |
| 8525 | UINT32 CSEnable:1 ; ///< |
| 8526 | UINT32 Reserved_4_1:4 ; ///< |
| 8527 | UINT32 BaseAddr_21_13_:9 ; ///< |
| 8528 | UINT32 Reserved_18_14:5 ; ///< |
| 8529 | UINT32 BaseAddr_36_27_:10; ///< |
| 8530 | UINT32 Reserved_31_29:3 ; ///< |
| 8531 | } Field; ///< |
| 8532 | UINT32 Value; ///< |
| 8533 | } GMMx2820_STRUCT; |
| 8534 | |
| 8535 | // **** GMMx2824 Register Definition **** |
| 8536 | // Address |
| 8537 | #define GMMx2824_ADDRESS 0x2824 |
| 8538 | |
| 8539 | // Type |
| 8540 | #define GMMx2824_TYPE TYPE_GMM |
| 8541 | // Field Data |
| 8542 | #define GMMx2824_CSEnable_OFFSET 0 |
| 8543 | #define GMMx2824_CSEnable_WIDTH 1 |
| 8544 | #define GMMx2824_CSEnable_MASK 0x1 |
| 8545 | #define GMMx2824_Reserved_4_1_OFFSET 1 |
| 8546 | #define GMMx2824_Reserved_4_1_WIDTH 4 |
| 8547 | #define GMMx2824_Reserved_4_1_MASK 0x1e |
| 8548 | #define GMMx2824_BaseAddr_21_13__OFFSET 5 |
| 8549 | #define GMMx2824_BaseAddr_21_13__WIDTH 9 |
| 8550 | #define GMMx2824_BaseAddr_21_13__MASK 0x3fe0 |
| 8551 | #define GMMx2824_Reserved_18_14_OFFSET 14 |
| 8552 | #define GMMx2824_Reserved_18_14_WIDTH 5 |
| 8553 | #define GMMx2824_Reserved_18_14_MASK 0x7c000 |
| 8554 | #define GMMx2824_BaseAddr_36_27__OFFSET 19 |
| 8555 | #define GMMx2824_BaseAddr_36_27__WIDTH 10 |
| 8556 | #define GMMx2824_BaseAddr_36_27__MASK 0x1ff80000 |
| 8557 | #define GMMx2824_Reserved_31_29_OFFSET 29 |
| 8558 | #define GMMx2824_Reserved_31_29_WIDTH 3 |
| 8559 | #define GMMx2824_Reserved_31_29_MASK 0xe0000000 |
| 8560 | |
| 8561 | /// GMMx2824 |
| 8562 | typedef union { |
| 8563 | struct { ///< |
| 8564 | UINT32 CSEnable:1 ; ///< |
| 8565 | UINT32 Reserved_4_1:4 ; ///< |
| 8566 | UINT32 BaseAddr_21_13_:9 ; ///< |
| 8567 | UINT32 Reserved_18_14:5 ; ///< |
| 8568 | UINT32 BaseAddr_36_27_:10; ///< |
| 8569 | UINT32 Reserved_31_29:3 ; ///< |
| 8570 | } Field; ///< |
| 8571 | UINT32 Value; ///< |
| 8572 | } GMMx2824_STRUCT; |
| 8573 | |
| 8574 | // **** GMMx2828 Register Definition **** |
| 8575 | // Address |
| 8576 | #define GMMx2828_ADDRESS 0x2828 |
| 8577 | |
| 8578 | // Type |
| 8579 | #define GMMx2828_TYPE TYPE_GMM |
| 8580 | // Field Data |
| 8581 | #define GMMx2828_CSEnable_OFFSET 0 |
| 8582 | #define GMMx2828_CSEnable_WIDTH 1 |
| 8583 | #define GMMx2828_CSEnable_MASK 0x1 |
| 8584 | #define GMMx2828_Reserved_4_1_OFFSET 1 |
| 8585 | #define GMMx2828_Reserved_4_1_WIDTH 4 |
| 8586 | #define GMMx2828_Reserved_4_1_MASK 0x1e |
| 8587 | #define GMMx2828_BaseAddr_21_13__OFFSET 5 |
| 8588 | #define GMMx2828_BaseAddr_21_13__WIDTH 9 |
| 8589 | #define GMMx2828_BaseAddr_21_13__MASK 0x3fe0 |
| 8590 | #define GMMx2828_Reserved_18_14_OFFSET 14 |
| 8591 | #define GMMx2828_Reserved_18_14_WIDTH 5 |
| 8592 | #define GMMx2828_Reserved_18_14_MASK 0x7c000 |
| 8593 | #define GMMx2828_BaseAddr_36_27__OFFSET 19 |
| 8594 | #define GMMx2828_BaseAddr_36_27__WIDTH 10 |
| 8595 | #define GMMx2828_BaseAddr_36_27__MASK 0x1ff80000 |
| 8596 | #define GMMx2828_Reserved_31_29_OFFSET 29 |
| 8597 | #define GMMx2828_Reserved_31_29_WIDTH 3 |
| 8598 | #define GMMx2828_Reserved_31_29_MASK 0xe0000000 |
| 8599 | |
| 8600 | /// GMMx2828 |
| 8601 | typedef union { |
| 8602 | struct { ///< |
| 8603 | UINT32 CSEnable:1 ; ///< |
| 8604 | UINT32 Reserved_4_1:4 ; ///< |
| 8605 | UINT32 BaseAddr_21_13_:9 ; ///< |
| 8606 | UINT32 Reserved_18_14:5 ; ///< |
| 8607 | UINT32 BaseAddr_36_27_:10; ///< |
| 8608 | UINT32 Reserved_31_29:3 ; ///< |
| 8609 | } Field; ///< |
| 8610 | UINT32 Value; ///< |
| 8611 | } GMMx2828_STRUCT; |
| 8612 | |
| 8613 | // **** GMMx282C Register Definition **** |
| 8614 | // Address |
| 8615 | #define GMMx282C_ADDRESS 0x282c |
| 8616 | |
| 8617 | // Type |
| 8618 | #define GMMx282C_TYPE TYPE_GMM |
| 8619 | // Field Data |
| 8620 | #define GMMx282C_CSEnable_OFFSET 0 |
| 8621 | #define GMMx282C_CSEnable_WIDTH 1 |
| 8622 | #define GMMx282C_CSEnable_MASK 0x1 |
| 8623 | #define GMMx282C_Reserved_4_1_OFFSET 1 |
| 8624 | #define GMMx282C_Reserved_4_1_WIDTH 4 |
| 8625 | #define GMMx282C_Reserved_4_1_MASK 0x1e |
| 8626 | #define GMMx282C_BaseAddr_21_13__OFFSET 5 |
| 8627 | #define GMMx282C_BaseAddr_21_13__WIDTH 9 |
| 8628 | #define GMMx282C_BaseAddr_21_13__MASK 0x3fe0 |
| 8629 | #define GMMx282C_Reserved_18_14_OFFSET 14 |
| 8630 | #define GMMx282C_Reserved_18_14_WIDTH 5 |
| 8631 | #define GMMx282C_Reserved_18_14_MASK 0x7c000 |
| 8632 | #define GMMx282C_BaseAddr_36_27__OFFSET 19 |
| 8633 | #define GMMx282C_BaseAddr_36_27__WIDTH 10 |
| 8634 | #define GMMx282C_BaseAddr_36_27__MASK 0x1ff80000 |
| 8635 | #define GMMx282C_Reserved_31_29_OFFSET 29 |
| 8636 | #define GMMx282C_Reserved_31_29_WIDTH 3 |
| 8637 | #define GMMx282C_Reserved_31_29_MASK 0xe0000000 |
| 8638 | |
| 8639 | /// GMMx282C |
| 8640 | typedef union { |
| 8641 | struct { ///< |
| 8642 | UINT32 CSEnable:1 ; ///< |
| 8643 | UINT32 Reserved_4_1:4 ; ///< |
| 8644 | UINT32 BaseAddr_21_13_:9 ; ///< |
| 8645 | UINT32 Reserved_18_14:5 ; ///< |
| 8646 | UINT32 BaseAddr_36_27_:10; ///< |
| 8647 | UINT32 Reserved_31_29:3 ; ///< |
| 8648 | } Field; ///< |
| 8649 | UINT32 Value; ///< |
| 8650 | } GMMx282C_STRUCT; |
| 8651 | |
| 8652 | // **** GMMx2830 Register Definition **** |
| 8653 | // Address |
| 8654 | #define GMMx2830_ADDRESS 0x2830 |
| 8655 | |
| 8656 | // Type |
| 8657 | #define GMMx2830_TYPE TYPE_GMM |
| 8658 | // Field Data |
| 8659 | #define GMMx2830_CSEnable_OFFSET 0 |
| 8660 | #define GMMx2830_CSEnable_WIDTH 1 |
| 8661 | #define GMMx2830_CSEnable_MASK 0x1 |
| 8662 | #define GMMx2830_Reserved_4_1_OFFSET 1 |
| 8663 | #define GMMx2830_Reserved_4_1_WIDTH 4 |
| 8664 | #define GMMx2830_Reserved_4_1_MASK 0x1e |
| 8665 | #define GMMx2830_BaseAddr_21_13__OFFSET 5 |
| 8666 | #define GMMx2830_BaseAddr_21_13__WIDTH 9 |
| 8667 | #define GMMx2830_BaseAddr_21_13__MASK 0x3fe0 |
| 8668 | #define GMMx2830_Reserved_18_14_OFFSET 14 |
| 8669 | #define GMMx2830_Reserved_18_14_WIDTH 5 |
| 8670 | #define GMMx2830_Reserved_18_14_MASK 0x7c000 |
| 8671 | #define GMMx2830_BaseAddr_36_27__OFFSET 19 |
| 8672 | #define GMMx2830_BaseAddr_36_27__WIDTH 10 |
| 8673 | #define GMMx2830_BaseAddr_36_27__MASK 0x1ff80000 |
| 8674 | #define GMMx2830_Reserved_31_29_OFFSET 29 |
| 8675 | #define GMMx2830_Reserved_31_29_WIDTH 3 |
| 8676 | #define GMMx2830_Reserved_31_29_MASK 0xe0000000 |
| 8677 | |
| 8678 | /// GMMx2830 |
| 8679 | typedef union { |
| 8680 | struct { ///< |
| 8681 | UINT32 CSEnable:1 ; ///< |
| 8682 | UINT32 Reserved_4_1:4 ; ///< |
| 8683 | UINT32 BaseAddr_21_13_:9 ; ///< |
| 8684 | UINT32 Reserved_18_14:5 ; ///< |
| 8685 | UINT32 BaseAddr_36_27_:10; ///< |
| 8686 | UINT32 Reserved_31_29:3 ; ///< |
| 8687 | } Field; ///< |
| 8688 | UINT32 Value; ///< |
| 8689 | } GMMx2830_STRUCT; |
| 8690 | |
| 8691 | // **** GMMx2834 Register Definition **** |
| 8692 | // Address |
| 8693 | #define GMMx2834_ADDRESS 0x2834 |
| 8694 | |
| 8695 | // Type |
| 8696 | #define GMMx2834_TYPE TYPE_GMM |
| 8697 | // Field Data |
| 8698 | #define GMMx2834_CSEnable_OFFSET 0 |
| 8699 | #define GMMx2834_CSEnable_WIDTH 1 |
| 8700 | #define GMMx2834_CSEnable_MASK 0x1 |
| 8701 | #define GMMx2834_Reserved_4_1_OFFSET 1 |
| 8702 | #define GMMx2834_Reserved_4_1_WIDTH 4 |
| 8703 | #define GMMx2834_Reserved_4_1_MASK 0x1e |
| 8704 | #define GMMx2834_BaseAddr_21_13__OFFSET 5 |
| 8705 | #define GMMx2834_BaseAddr_21_13__WIDTH 9 |
| 8706 | #define GMMx2834_BaseAddr_21_13__MASK 0x3fe0 |
| 8707 | #define GMMx2834_Reserved_18_14_OFFSET 14 |
| 8708 | #define GMMx2834_Reserved_18_14_WIDTH 5 |
| 8709 | #define GMMx2834_Reserved_18_14_MASK 0x7c000 |
| 8710 | #define GMMx2834_BaseAddr_36_27__OFFSET 19 |
| 8711 | #define GMMx2834_BaseAddr_36_27__WIDTH 10 |
| 8712 | #define GMMx2834_BaseAddr_36_27__MASK 0x1ff80000 |
| 8713 | #define GMMx2834_Reserved_31_29_OFFSET 29 |
| 8714 | #define GMMx2834_Reserved_31_29_WIDTH 3 |
| 8715 | #define GMMx2834_Reserved_31_29_MASK 0xe0000000 |
| 8716 | |
| 8717 | /// GMMx2834 |
| 8718 | typedef union { |
| 8719 | struct { ///< |
| 8720 | UINT32 CSEnable:1 ; ///< |
| 8721 | UINT32 Reserved_4_1:4 ; ///< |
| 8722 | UINT32 BaseAddr_21_13_:9 ; ///< |
| 8723 | UINT32 Reserved_18_14:5 ; ///< |
| 8724 | UINT32 BaseAddr_36_27_:10; ///< |
| 8725 | UINT32 Reserved_31_29:3 ; ///< |
| 8726 | } Field; ///< |
| 8727 | UINT32 Value; ///< |
| 8728 | } GMMx2834_STRUCT; |
| 8729 | |
| 8730 | // **** GMMx2838 Register Definition **** |
| 8731 | // Address |
| 8732 | #define GMMx2838_ADDRESS 0x2838 |
| 8733 | |
| 8734 | // Type |
| 8735 | #define GMMx2838_TYPE TYPE_GMM |
| 8736 | // Field Data |
| 8737 | #define GMMx2838_CSEnable_OFFSET 0 |
| 8738 | #define GMMx2838_CSEnable_WIDTH 1 |
| 8739 | #define GMMx2838_CSEnable_MASK 0x1 |
| 8740 | #define GMMx2838_Reserved_4_1_OFFSET 1 |
| 8741 | #define GMMx2838_Reserved_4_1_WIDTH 4 |
| 8742 | #define GMMx2838_Reserved_4_1_MASK 0x1e |
| 8743 | #define GMMx2838_BaseAddr_21_13__OFFSET 5 |
| 8744 | #define GMMx2838_BaseAddr_21_13__WIDTH 9 |
| 8745 | #define GMMx2838_BaseAddr_21_13__MASK 0x3fe0 |
| 8746 | #define GMMx2838_Reserved_18_14_OFFSET 14 |
| 8747 | #define GMMx2838_Reserved_18_14_WIDTH 5 |
| 8748 | #define GMMx2838_Reserved_18_14_MASK 0x7c000 |
| 8749 | #define GMMx2838_BaseAddr_36_27__OFFSET 19 |
| 8750 | #define GMMx2838_BaseAddr_36_27__WIDTH 10 |
| 8751 | #define GMMx2838_BaseAddr_36_27__MASK 0x1ff80000 |
| 8752 | #define GMMx2838_Reserved_31_29_OFFSET 29 |
| 8753 | #define GMMx2838_Reserved_31_29_WIDTH 3 |
| 8754 | #define GMMx2838_Reserved_31_29_MASK 0xe0000000 |
| 8755 | |
| 8756 | /// GMMx2838 |
| 8757 | typedef union { |
| 8758 | struct { ///< |
| 8759 | UINT32 CSEnable:1 ; ///< |
| 8760 | UINT32 Reserved_4_1:4 ; ///< |
| 8761 | UINT32 BaseAddr_21_13_:9 ; ///< |
| 8762 | UINT32 Reserved_18_14:5 ; ///< |
| 8763 | UINT32 BaseAddr_36_27_:10; ///< |
| 8764 | UINT32 Reserved_31_29:3 ; ///< |
| 8765 | } Field; ///< |
| 8766 | UINT32 Value; ///< |
| 8767 | } GMMx2838_STRUCT; |
| 8768 | |
| 8769 | // **** GMMx283C Register Definition **** |
| 8770 | // Address |
| 8771 | #define GMMx283C_ADDRESS 0x283c |
| 8772 | |
| 8773 | // Type |
| 8774 | #define GMMx283C_TYPE TYPE_GMM |
| 8775 | // Field Data |
| 8776 | #define GMMx283C_Reserved_4_0_OFFSET 0 |
| 8777 | #define GMMx283C_Reserved_4_0_WIDTH 5 |
| 8778 | #define GMMx283C_Reserved_4_0_MASK 0x1f |
| 8779 | #define GMMx283C_AddrMask_21_13__OFFSET 5 |
| 8780 | #define GMMx283C_AddrMask_21_13__WIDTH 9 |
| 8781 | #define GMMx283C_AddrMask_21_13__MASK 0x3fe0 |
| 8782 | #define GMMx283C_Reserved_18_14_OFFSET 14 |
| 8783 | #define GMMx283C_Reserved_18_14_WIDTH 5 |
| 8784 | #define GMMx283C_Reserved_18_14_MASK 0x7c000 |
| 8785 | #define GMMx283C_AddrMask_36_27__OFFSET 19 |
| 8786 | #define GMMx283C_AddrMask_36_27__WIDTH 10 |
| 8787 | #define GMMx283C_AddrMask_36_27__MASK 0x1ff80000 |
| 8788 | #define GMMx283C_Reserved_31_29_OFFSET 29 |
| 8789 | #define GMMx283C_Reserved_31_29_WIDTH 3 |
| 8790 | #define GMMx283C_Reserved_31_29_MASK 0xe0000000 |
| 8791 | |
| 8792 | /// GMMx283C |
| 8793 | typedef union { |
| 8794 | struct { ///< |
| 8795 | UINT32 Reserved_4_0:5 ; ///< |
| 8796 | UINT32 AddrMask_21_13_:9 ; ///< |
| 8797 | UINT32 Reserved_18_14:5 ; ///< |
| 8798 | UINT32 AddrMask_36_27_:10; ///< |
| 8799 | UINT32 Reserved_31_29:3 ; ///< |
| 8800 | } Field; ///< |
| 8801 | UINT32 Value; ///< |
| 8802 | } GMMx283C_STRUCT; |
| 8803 | |
| 8804 | // **** GMMx2840 Register Definition **** |
| 8805 | // Address |
| 8806 | #define GMMx2840_ADDRESS 0x2840 |
| 8807 | |
| 8808 | // Type |
| 8809 | #define GMMx2840_TYPE TYPE_GMM |
| 8810 | // Field Data |
| 8811 | #define GMMx2840_Reserved_4_0_OFFSET 0 |
| 8812 | #define GMMx2840_Reserved_4_0_WIDTH 5 |
| 8813 | #define GMMx2840_Reserved_4_0_MASK 0x1f |
| 8814 | #define GMMx2840_AddrMask_21_13__OFFSET 5 |
| 8815 | #define GMMx2840_AddrMask_21_13__WIDTH 9 |
| 8816 | #define GMMx2840_AddrMask_21_13__MASK 0x3fe0 |
| 8817 | #define GMMx2840_Reserved_18_14_OFFSET 14 |
| 8818 | #define GMMx2840_Reserved_18_14_WIDTH 5 |
| 8819 | #define GMMx2840_Reserved_18_14_MASK 0x7c000 |
| 8820 | #define GMMx2840_AddrMask_36_27__OFFSET 19 |
| 8821 | #define GMMx2840_AddrMask_36_27__WIDTH 10 |
| 8822 | #define GMMx2840_AddrMask_36_27__MASK 0x1ff80000 |
| 8823 | #define GMMx2840_Reserved_31_29_OFFSET 29 |
| 8824 | #define GMMx2840_Reserved_31_29_WIDTH 3 |
| 8825 | #define GMMx2840_Reserved_31_29_MASK 0xe0000000 |
| 8826 | |
| 8827 | /// GMMx2840 |
| 8828 | typedef union { |
| 8829 | struct { ///< |
| 8830 | UINT32 Reserved_4_0:5 ; ///< |
| 8831 | UINT32 AddrMask_21_13_:9 ; ///< |
| 8832 | UINT32 Reserved_18_14:5 ; ///< |
| 8833 | UINT32 AddrMask_36_27_:10; ///< |
| 8834 | UINT32 Reserved_31_29:3 ; ///< |
| 8835 | } Field; ///< |
| 8836 | UINT32 Value; ///< |
| 8837 | } GMMx2840_STRUCT; |
| 8838 | |
| 8839 | // **** GMMx2844 Register Definition **** |
| 8840 | // Address |
| 8841 | #define GMMx2844_ADDRESS 0x2844 |
| 8842 | |
| 8843 | // Type |
| 8844 | #define GMMx2844_TYPE TYPE_GMM |
| 8845 | // Field Data |
| 8846 | #define GMMx2844_Reserved_4_0_OFFSET 0 |
| 8847 | #define GMMx2844_Reserved_4_0_WIDTH 5 |
| 8848 | #define GMMx2844_Reserved_4_0_MASK 0x1f |
| 8849 | #define GMMx2844_AddrMask_21_13__OFFSET 5 |
| 8850 | #define GMMx2844_AddrMask_21_13__WIDTH 9 |
| 8851 | #define GMMx2844_AddrMask_21_13__MASK 0x3fe0 |
| 8852 | #define GMMx2844_Reserved_18_14_OFFSET 14 |
| 8853 | #define GMMx2844_Reserved_18_14_WIDTH 5 |
| 8854 | #define GMMx2844_Reserved_18_14_MASK 0x7c000 |
| 8855 | #define GMMx2844_AddrMask_36_27__OFFSET 19 |
| 8856 | #define GMMx2844_AddrMask_36_27__WIDTH 10 |
| 8857 | #define GMMx2844_AddrMask_36_27__MASK 0x1ff80000 |
| 8858 | #define GMMx2844_Reserved_31_29_OFFSET 29 |
| 8859 | #define GMMx2844_Reserved_31_29_WIDTH 3 |
| 8860 | #define GMMx2844_Reserved_31_29_MASK 0xe0000000 |
| 8861 | |
| 8862 | /// GMMx2844 |
| 8863 | typedef union { |
| 8864 | struct { ///< |
| 8865 | UINT32 Reserved_4_0:5 ; ///< |
| 8866 | UINT32 AddrMask_21_13_:9 ; ///< |
| 8867 | UINT32 Reserved_18_14:5 ; ///< |
| 8868 | UINT32 AddrMask_36_27_:10; ///< |
| 8869 | UINT32 Reserved_31_29:3 ; ///< |
| 8870 | } Field; ///< |
| 8871 | UINT32 Value; ///< |
| 8872 | } GMMx2844_STRUCT; |
| 8873 | |
| 8874 | // **** GMMx2848 Register Definition **** |
| 8875 | // Address |
| 8876 | #define GMMx2848_ADDRESS 0x2848 |
| 8877 | |
| 8878 | // Type |
| 8879 | #define GMMx2848_TYPE TYPE_GMM |
| 8880 | // Field Data |
| 8881 | #define GMMx2848_Reserved_4_0_OFFSET 0 |
| 8882 | #define GMMx2848_Reserved_4_0_WIDTH 5 |
| 8883 | #define GMMx2848_Reserved_4_0_MASK 0x1f |
| 8884 | #define GMMx2848_AddrMask_21_13__OFFSET 5 |
| 8885 | #define GMMx2848_AddrMask_21_13__WIDTH 9 |
| 8886 | #define GMMx2848_AddrMask_21_13__MASK 0x3fe0 |
| 8887 | #define GMMx2848_Reserved_18_14_OFFSET 14 |
| 8888 | #define GMMx2848_Reserved_18_14_WIDTH 5 |
| 8889 | #define GMMx2848_Reserved_18_14_MASK 0x7c000 |
| 8890 | #define GMMx2848_AddrMask_36_27__OFFSET 19 |
| 8891 | #define GMMx2848_AddrMask_36_27__WIDTH 10 |
| 8892 | #define GMMx2848_AddrMask_36_27__MASK 0x1ff80000 |
| 8893 | #define GMMx2848_Reserved_31_29_OFFSET 29 |
| 8894 | #define GMMx2848_Reserved_31_29_WIDTH 3 |
| 8895 | #define GMMx2848_Reserved_31_29_MASK 0xe0000000 |
| 8896 | |
| 8897 | /// GMMx2848 |
| 8898 | typedef union { |
| 8899 | struct { ///< |
| 8900 | UINT32 Reserved_4_0:5 ; ///< |
| 8901 | UINT32 AddrMask_21_13_:9 ; ///< |
| 8902 | UINT32 Reserved_18_14:5 ; ///< |
| 8903 | UINT32 AddrMask_36_27_:10; ///< |
| 8904 | UINT32 Reserved_31_29:3 ; ///< |
| 8905 | } Field; ///< |
| 8906 | UINT32 Value; ///< |
| 8907 | } GMMx2848_STRUCT; |
| 8908 | |
| 8909 | // **** GMMx284C Register Definition **** |
| 8910 | // Address |
| 8911 | #define GMMx284C_ADDRESS 0x284c |
| 8912 | |
| 8913 | // Type |
| 8914 | #define GMMx284C_TYPE TYPE_GMM |
| 8915 | // Field Data |
| 8916 | #define GMMx284C_Dimm0AddrMap_OFFSET 0 |
| 8917 | #define GMMx284C_Dimm0AddrMap_WIDTH 4 |
| 8918 | #define GMMx284C_Dimm0AddrMap_MASK 0xf |
| 8919 | #define GMMx284C_Dimm1AddrMap_OFFSET 4 |
| 8920 | #define GMMx284C_Dimm1AddrMap_WIDTH 4 |
| 8921 | #define GMMx284C_Dimm1AddrMap_MASK 0xf0 |
| 8922 | #define GMMx284C_Reserved_15_8_OFFSET 8 |
| 8923 | #define GMMx284C_Reserved_15_8_WIDTH 8 |
| 8924 | #define GMMx284C_Reserved_15_8_MASK 0xff00 |
| 8925 | #define GMMx284C_BankSwizzleMode_OFFSET 16 |
| 8926 | #define GMMx284C_BankSwizzleMode_WIDTH 1 |
| 8927 | #define GMMx284C_BankSwizzleMode_MASK 0x10000 |
| 8928 | #define GMMx284C_Ddr3Mode_OFFSET 17 |
| 8929 | #define GMMx284C_Ddr3Mode_WIDTH 1 |
| 8930 | #define GMMx284C_Ddr3Mode_MASK 0x20000 |
| 8931 | #define GMMx284C_BurstLength32_OFFSET 18 |
| 8932 | #define GMMx284C_BurstLength32_WIDTH 1 |
| 8933 | #define GMMx284C_BurstLength32_MASK 0x40000 |
| 8934 | #define GMMx284C_BankSwap_OFFSET 19 |
| 8935 | #define GMMx284C_BankSwap_WIDTH 1 |
| 8936 | #define GMMx284C_BankSwap_MASK 0x80000 |
| 8937 | #define GMMx284C_Reserved_31_20_OFFSET 20 |
| 8938 | #define GMMx284C_Reserved_31_20_WIDTH 12 |
| 8939 | #define GMMx284C_Reserved_31_20_MASK 0xfff00000 |
| 8940 | |
| 8941 | /// GMMx284C |
| 8942 | typedef union { |
| 8943 | struct { ///< |
| 8944 | UINT32 Dimm0AddrMap:4 ; ///< |
| 8945 | UINT32 Dimm1AddrMap:4 ; ///< |
| 8946 | UINT32 Reserved_15_8:8 ; ///< |
| 8947 | UINT32 BankSwizzleMode:1 ; ///< |
| 8948 | UINT32 Ddr3Mode:1 ; ///< |
| 8949 | UINT32 BurstLength32:1 ; ///< |
| 8950 | UINT32 BankSwap:1 ; ///< |
| 8951 | UINT32 Reserved_31_20:12; ///< |
| 8952 | } Field; ///< |
| 8953 | UINT32 Value; ///< |
| 8954 | } GMMx284C_STRUCT; |
| 8955 | |
| 8956 | // **** GMMx2850 Register Definition **** |
| 8957 | // Address |
| 8958 | #define GMMx2850_ADDRESS 0x2850 |
| 8959 | |
| 8960 | // Type |
| 8961 | #define GMMx2850_TYPE TYPE_GMM |
| 8962 | // Field Data |
| 8963 | #define GMMx2850_Dimm0AddrMap_OFFSET 0 |
| 8964 | #define GMMx2850_Dimm0AddrMap_WIDTH 4 |
| 8965 | #define GMMx2850_Dimm0AddrMap_MASK 0xf |
| 8966 | #define GMMx2850_Dimm1AddrMap_OFFSET 4 |
| 8967 | #define GMMx2850_Dimm1AddrMap_WIDTH 4 |
| 8968 | #define GMMx2850_Dimm1AddrMap_MASK 0xf0 |
| 8969 | #define GMMx2850_Reserved_15_8_OFFSET 8 |
| 8970 | #define GMMx2850_Reserved_15_8_WIDTH 8 |
| 8971 | #define GMMx2850_Reserved_15_8_MASK 0xff00 |
| 8972 | #define GMMx2850_BankSwizzleMode_OFFSET 16 |
| 8973 | #define GMMx2850_BankSwizzleMode_WIDTH 1 |
| 8974 | #define GMMx2850_BankSwizzleMode_MASK 0x10000 |
| 8975 | #define GMMx2850_Ddr3Mode_OFFSET 17 |
| 8976 | #define GMMx2850_Ddr3Mode_WIDTH 1 |
| 8977 | #define GMMx2850_Ddr3Mode_MASK 0x20000 |
| 8978 | #define GMMx2850_BurstLength32_OFFSET 18 |
| 8979 | #define GMMx2850_BurstLength32_WIDTH 1 |
| 8980 | #define GMMx2850_BurstLength32_MASK 0x40000 |
| 8981 | #define GMMx2850_BankSwap_OFFSET 19 |
| 8982 | #define GMMx2850_BankSwap_WIDTH 1 |
| 8983 | #define GMMx2850_BankSwap_MASK 0x80000 |
| 8984 | #define GMMx2850_Reserved_31_20_OFFSET 20 |
| 8985 | #define GMMx2850_Reserved_31_20_WIDTH 12 |
| 8986 | #define GMMx2850_Reserved_31_20_MASK 0xfff00000 |
| 8987 | |
| 8988 | /// GMMx2850 |
| 8989 | typedef union { |
| 8990 | struct { ///< |
| 8991 | UINT32 Dimm0AddrMap:4 ; ///< |
| 8992 | UINT32 Dimm1AddrMap:4 ; ///< |
| 8993 | UINT32 Reserved_15_8:8 ; ///< |
| 8994 | UINT32 BankSwizzleMode:1 ; ///< |
| 8995 | UINT32 Ddr3Mode:1 ; ///< |
| 8996 | UINT32 BurstLength32:1 ; ///< |
| 8997 | UINT32 BankSwap:1 ; ///< |
| 8998 | UINT32 Reserved_31_20:12; ///< |
| 8999 | } Field; ///< |
| 9000 | UINT32 Value; ///< |
| 9001 | } GMMx2850_STRUCT; |
| 9002 | |
| 9003 | // **** GMMx2854 Register Definition **** |
| 9004 | // Address |
| 9005 | #define GMMx2854_ADDRESS 0x2854 |
| 9006 | |
| 9007 | // Type |
| 9008 | #define GMMx2854_TYPE TYPE_GMM |
| 9009 | // Field Data |
| 9010 | #define GMMx2854_DctSelHiRngEn_OFFSET 0 |
| 9011 | #define GMMx2854_DctSelHiRngEn_WIDTH 1 |
| 9012 | #define GMMx2854_DctSelHiRngEn_MASK 0x1 |
| 9013 | #define GMMx2854_DctSelHi_OFFSET 1 |
| 9014 | #define GMMx2854_DctSelHi_WIDTH 1 |
| 9015 | #define GMMx2854_DctSelHi_MASK 0x2 |
| 9016 | #define GMMx2854_DctSelIntLvEn_OFFSET 2 |
| 9017 | #define GMMx2854_DctSelIntLvEn_WIDTH 1 |
| 9018 | #define GMMx2854_DctSelIntLvEn_MASK 0x4 |
| 9019 | #define GMMx2854_Reserved_5_3_OFFSET 3 |
| 9020 | #define GMMx2854_Reserved_5_3_WIDTH 3 |
| 9021 | #define GMMx2854_Reserved_5_3_MASK 0x38 |
| 9022 | #define GMMx2854_DctSelIntLvAddr_1_0__OFFSET 6 |
| 9023 | #define GMMx2854_DctSelIntLvAddr_1_0__WIDTH 2 |
| 9024 | #define GMMx2854_DctSelIntLvAddr_1_0__MASK 0xc0 |
| 9025 | #define GMMx2854_Reserved_10_8_OFFSET 8 |
| 9026 | #define GMMx2854_Reserved_10_8_WIDTH 3 |
| 9027 | #define GMMx2854_Reserved_10_8_MASK 0x700 |
| 9028 | #define GMMx2854_DctSelBaseAddr_39_27__OFFSET 11 |
| 9029 | #define GMMx2854_DctSelBaseAddr_39_27__WIDTH 13 |
| 9030 | #define GMMx2854_DctSelBaseAddr_39_27__MASK 0xfff800 |
| 9031 | #define GMMx2854_Reserved_31_24_OFFSET 24 |
| 9032 | #define GMMx2854_Reserved_31_24_WIDTH 8 |
| 9033 | #define GMMx2854_Reserved_31_24_MASK 0xff000000 |
| 9034 | |
| 9035 | /// GMMx2854 |
| 9036 | typedef union { |
| 9037 | struct { ///< |
| 9038 | UINT32 DctSelHiRngEn:1 ; ///< |
| 9039 | UINT32 DctSelHi:1 ; ///< |
| 9040 | UINT32 DctSelIntLvEn:1 ; ///< |
| 9041 | UINT32 Reserved_5_3:3 ; ///< |
| 9042 | UINT32 DctSelIntLvAddr_1_0_:2 ; ///< |
| 9043 | UINT32 Reserved_10_8:3 ; ///< |
| 9044 | UINT32 DctSelBaseAddr_39_27_:13; ///< |
| 9045 | UINT32 Reserved_31_24:8 ; ///< |
| 9046 | } Field; ///< |
| 9047 | UINT32 Value; ///< |
| 9048 | } GMMx2854_STRUCT; |
| 9049 | |
| 9050 | // **** GMMx2858 Register Definition **** |
| 9051 | // Address |
| 9052 | #define GMMx2858_ADDRESS 0x2858 |
| 9053 | |
| 9054 | // Type |
| 9055 | #define GMMx2858_TYPE TYPE_GMM |
| 9056 | // Field Data |
| 9057 | #define GMMx2858_Reserved_8_0_OFFSET 0 |
| 9058 | #define GMMx2858_Reserved_8_0_WIDTH 9 |
| 9059 | #define GMMx2858_Reserved_8_0_MASK 0x1ff |
| 9060 | #define GMMx2858_DctSelIntLvAddr_2__OFFSET 9 |
| 9061 | #define GMMx2858_DctSelIntLvAddr_2__WIDTH 1 |
| 9062 | #define GMMx2858_DctSelIntLvAddr_2__MASK 0x200 |
| 9063 | #define GMMx2858_DctSelBaseOffset_39_26__OFFSET 10 |
| 9064 | #define GMMx2858_DctSelBaseOffset_39_26__WIDTH 14 |
| 9065 | #define GMMx2858_DctSelBaseOffset_39_26__MASK 0xfffc00 |
| 9066 | #define GMMx2858_Reserved_31_24_OFFSET 24 |
| 9067 | #define GMMx2858_Reserved_31_24_WIDTH 8 |
| 9068 | #define GMMx2858_Reserved_31_24_MASK 0xff000000 |
| 9069 | |
| 9070 | /// GMMx2858 |
| 9071 | typedef union { |
| 9072 | struct { ///< |
| 9073 | UINT32 Reserved_8_0:9 ; ///< |
| 9074 | UINT32 DctSelIntLvAddr_2_:1 ; ///< |
| 9075 | UINT32 DctSelBaseOffset_39_26_:14; ///< |
| 9076 | UINT32 Reserved_31_24:8 ; ///< |
| 9077 | } Field; ///< |
| 9078 | UINT32 Value; ///< |
| 9079 | } GMMx2858_STRUCT; |
| 9080 | |
| 9081 | // **** GMMx285C Register Definition **** |
| 9082 | // Address |
| 9083 | #define GMMx285C_ADDRESS 0x285c |
| 9084 | |
| 9085 | // Type |
| 9086 | #define GMMx285C_TYPE TYPE_GMM |
| 9087 | // Field Data |
| 9088 | #define GMMx285C_DramHoleValid_OFFSET 0 |
| 9089 | #define GMMx285C_DramHoleValid_WIDTH 1 |
| 9090 | #define GMMx285C_DramHoleValid_MASK 0x1 |
| 9091 | #define GMMx285C_Reserved_6_1_OFFSET 1 |
| 9092 | #define GMMx285C_Reserved_6_1_WIDTH 6 |
| 9093 | #define GMMx285C_Reserved_6_1_MASK 0x7e |
| 9094 | #define GMMx285C_DramHoleOffset_31_23__OFFSET 7 |
| 9095 | #define GMMx285C_DramHoleOffset_31_23__WIDTH 9 |
| 9096 | #define GMMx285C_DramHoleOffset_31_23__MASK 0xff80 |
| 9097 | #define GMMx285C_Reserved_23_16_OFFSET 16 |
| 9098 | #define GMMx285C_Reserved_23_16_WIDTH 8 |
| 9099 | #define GMMx285C_Reserved_23_16_MASK 0xff0000 |
| 9100 | #define GMMx285C_DramHoleBase_31_24__OFFSET 24 |
| 9101 | #define GMMx285C_DramHoleBase_31_24__WIDTH 8 |
| 9102 | #define GMMx285C_DramHoleBase_31_24__MASK 0xff000000 |
| 9103 | |
| 9104 | /// GMMx285C |
| 9105 | typedef union { |
| 9106 | struct { ///< |
| 9107 | UINT32 DramHoleValid:1 ; ///< |
| 9108 | UINT32 Reserved_6_1:6 ; ///< |
| 9109 | UINT32 DramHoleOffset_31_23_:9 ; ///< |
| 9110 | UINT32 Reserved_23_16:8 ; ///< |
| 9111 | UINT32 DramHoleBase_31_24_:8 ; ///< |
| 9112 | } Field; ///< |
| 9113 | UINT32 Value; ///< |
| 9114 | } GMMx285C_STRUCT; |
| 9115 | |
| 9116 | |
| 9117 | |
| 9118 | |
| 9119 | |
| 9120 | // **** GMMx2870 Register Definition **** |
| 9121 | // Address |
| 9122 | #define GMMx2870_ADDRESS 0x2870 |
| 9123 | |
| 9124 | // Type |
| 9125 | #define GMMx2870_TYPE TYPE_GMM |
| 9126 | // Field Data |
| 9127 | #define GMMx2870_Base_OFFSET 0 |
| 9128 | #define GMMx2870_Base_WIDTH 20 |
| 9129 | #define GMMx2870_Base_MASK 0xfffff |
| 9130 | #define GMMx2870_Reserved_31_20_OFFSET 20 |
| 9131 | #define GMMx2870_Reserved_31_20_WIDTH 12 |
| 9132 | #define GMMx2870_Reserved_31_20_MASK 0xfff00000 |
| 9133 | |
| 9134 | /// GMMx2870 |
| 9135 | typedef union { |
| 9136 | struct { ///< |
| 9137 | UINT32 Base:20; ///< |
| 9138 | UINT32 Reserved_31_20:12; ///< |
| 9139 | } Field; ///< |
| 9140 | UINT32 Value; ///< |
| 9141 | } GMMx2870_STRUCT; |
| 9142 | |
| 9143 | // **** GMMx2874 Register Definition **** |
| 9144 | // Address |
| 9145 | #define GMMx2874_ADDRESS 0x2874 |
| 9146 | |
| 9147 | // Type |
| 9148 | #define GMMx2874_TYPE TYPE_GMM |
| 9149 | // Field Data |
| 9150 | #define GMMx2874_Base_OFFSET 0 |
| 9151 | #define GMMx2874_Base_WIDTH 20 |
| 9152 | #define GMMx2874_Base_MASK 0xfffff |
| 9153 | #define GMMx2874_Reserved_31_20_OFFSET 20 |
| 9154 | #define GMMx2874_Reserved_31_20_WIDTH 12 |
| 9155 | #define GMMx2874_Reserved_31_20_MASK 0xfff00000 |
| 9156 | |
| 9157 | /// GMMx2874 |
| 9158 | typedef union { |
| 9159 | struct { ///< |
| 9160 | UINT32 Base:20; ///< |
| 9161 | UINT32 Reserved_31_20:12; ///< |
| 9162 | } Field; ///< |
| 9163 | UINT32 Value; ///< |
| 9164 | } GMMx2874_STRUCT; |
| 9165 | |
| 9166 | |
| 9167 | // **** GMMx287C Register Definition **** |
| 9168 | // Address |
| 9169 | #define GMMx287C_ADDRESS 0x287c |
| 9170 | |
| 9171 | // Type |
| 9172 | #define GMMx287C_TYPE TYPE_GMM |
| 9173 | // Field Data |
| 9174 | #define GMMx287C_Top_OFFSET 0 |
| 9175 | #define GMMx287C_Top_WIDTH 20 |
| 9176 | #define GMMx287C_Top_MASK 0xfffff |
| 9177 | #define GMMx287C_Reserved_31_20_OFFSET 20 |
| 9178 | #define GMMx287C_Reserved_31_20_WIDTH 12 |
| 9179 | #define GMMx287C_Reserved_31_20_MASK 0xfff00000 |
| 9180 | |
| 9181 | /// GMMx287C |
| 9182 | typedef union { |
| 9183 | struct { ///< |
| 9184 | UINT32 Top:20; ///< |
| 9185 | UINT32 Reserved_31_20:12; ///< |
| 9186 | } Field; ///< |
| 9187 | UINT32 Value; ///< |
| 9188 | } GMMx287C_STRUCT; |
| 9189 | |
| 9190 | |
| 9191 | |
| 9192 | // **** GMMx2888 Register Definition **** |
| 9193 | // Address |
| 9194 | #define GMMx2888_ADDRESS 0x2888 |
| 9195 | |
| 9196 | // Type |
| 9197 | #define GMMx2888_TYPE TYPE_GMM |
| 9198 | // Field Data |
| 9199 | #define GMMx2888_Top_OFFSET 0 |
| 9200 | #define GMMx2888_Top_WIDTH 20 |
| 9201 | #define GMMx2888_Top_MASK 0xfffff |
| 9202 | #define GMMx2888_Reserved_31_20_OFFSET 20 |
| 9203 | #define GMMx2888_Reserved_31_20_WIDTH 12 |
| 9204 | #define GMMx2888_Reserved_31_20_MASK 0xfff00000 |
| 9205 | |
| 9206 | /// GMMx2888 |
| 9207 | typedef union { |
| 9208 | struct { ///< |
| 9209 | UINT32 Top:20; ///< |
| 9210 | UINT32 Reserved_31_20:12; ///< |
| 9211 | } Field; ///< |
| 9212 | UINT32 Value; ///< |
| 9213 | } GMMx2888_STRUCT; |
| 9214 | |
| 9215 | |
| 9216 | |
| 9217 | |
| 9218 | |
| 9219 | |
| 9220 | // **** GMMx28D8 Register Definition **** |
| 9221 | // Address |
| 9222 | #define GMMx28D8_ADDRESS 0x28d8 |
| 9223 | |
| 9224 | // Type |
| 9225 | #define GMMx28D8_TYPE TYPE_GMM |
| 9226 | // Field Data |
| 9227 | #define GMMx28D8_ActRd_OFFSET 0 |
| 9228 | #define GMMx28D8_ActRd_WIDTH 8 |
| 9229 | #define GMMx28D8_ActRd_MASK 0xff |
| 9230 | #define GMMx28D8_ActWr_OFFSET 8 |
| 9231 | #define GMMx28D8_ActWr_WIDTH 8 |
| 9232 | #define GMMx28D8_ActWr_MASK 0xff00 |
| 9233 | #define GMMx28D8_RasMActRd_OFFSET 16 |
| 9234 | #define GMMx28D8_RasMActRd_WIDTH 8 |
| 9235 | #define GMMx28D8_RasMActRd_MASK 0xff0000 |
| 9236 | #define GMMx28D8_RasMActWr_OFFSET 24 |
| 9237 | #define GMMx28D8_RasMActWr_WIDTH 8 |
| 9238 | #define GMMx28D8_RasMActWr_MASK 0xff000000 |
| 9239 | |
| 9240 | /// GMMx28D8 |
| 9241 | typedef union { |
| 9242 | struct { ///< |
| 9243 | UINT32 ActRd:8 ; ///< |
| 9244 | UINT32 ActWr:8 ; ///< |
| 9245 | UINT32 RasMActRd:8 ; ///< |
| 9246 | UINT32 RasMActWr:8 ; ///< |
| 9247 | } Field; ///< |
| 9248 | UINT32 Value; ///< |
| 9249 | } GMMx28D8_STRUCT; |
| 9250 | |
| 9251 | |
| 9252 | |
| 9253 | |
| 9254 | |
| 9255 | |
| 9256 | |
| 9257 | // **** GMMx2C04 Register Definition **** |
| 9258 | // Address |
| 9259 | #define GMMx2C04_ADDRESS 0x2c04 |
| 9260 | |
| 9261 | // Type |
| 9262 | #define GMMx2C04_TYPE TYPE_GMM |
| 9263 | // Field Data |
| 9264 | #define GMMx2C04_NonsurfBase_OFFSET 0 |
| 9265 | #define GMMx2C04_NonsurfBase_WIDTH 28 |
| 9266 | #define GMMx2C04_NonsurfBase_MASK 0xfffffff |
| 9267 | #define GMMx2C04_Reserved_31_28_OFFSET 28 |
| 9268 | #define GMMx2C04_Reserved_31_28_WIDTH 4 |
| 9269 | #define GMMx2C04_Reserved_31_28_MASK 0xf0000000 |
| 9270 | |
| 9271 | /// GMMx2C04 |
| 9272 | typedef union { |
| 9273 | struct { ///< |
| 9274 | UINT32 NonsurfBase:28; ///< |
| 9275 | UINT32 Reserved_31_28:4 ; ///< |
| 9276 | } Field; ///< |
| 9277 | UINT32 Value; ///< |
| 9278 | } GMMx2C04_STRUCT; |
| 9279 | |
| 9280 | // **** GMMx5428 Register Definition **** |
| 9281 | // Address |
| 9282 | #define GMMx5428_ADDRESS 0x5428 |
| 9283 | |
| 9284 | // Type |
| 9285 | #define GMMx5428_TYPE TYPE_GMM |
| 9286 | // Field Data |
| 9287 | #define GMMx5428_ConfigMemsize_OFFSET 0 |
| 9288 | #define GMMx5428_ConfigMemsize_WIDTH 32 |
| 9289 | #define GMMx5428_ConfigMemsize_MASK 0xffffffff |
| 9290 | |
| 9291 | /// GMMx5428 |
| 9292 | typedef union { |
| 9293 | struct { ///< |
| 9294 | UINT32 ConfigMemsize:32; ///< |
| 9295 | } Field; ///< |
| 9296 | UINT32 Value; ///< |
| 9297 | } GMMx5428_STRUCT; |
| 9298 | |
| 9299 | // **** GMMx5490 Register Definition **** |
| 9300 | // Address |
| 9301 | #define GMMx5490_ADDRESS 0x5490 |
| 9302 | |
| 9303 | // Type |
| 9304 | #define GMMx5490_TYPE TYPE_GMM |
| 9305 | // Field Data |
| 9306 | #define GMMx5490_FbReadEn_OFFSET 0 |
| 9307 | #define GMMx5490_FbReadEn_WIDTH 1 |
| 9308 | #define GMMx5490_FbReadEn_MASK 0x1 |
| 9309 | #define GMMx5490_FbWriteEn_OFFSET 1 |
| 9310 | #define GMMx5490_FbWriteEn_WIDTH 1 |
| 9311 | #define GMMx5490_FbWriteEn_MASK 0x2 |
| 9312 | #define GMMx5490_Reserved_31_2_OFFSET 2 |
| 9313 | #define GMMx5490_Reserved_31_2_WIDTH 30 |
| 9314 | #define GMMx5490_Reserved_31_2_MASK 0xfffffffc |
| 9315 | |
| 9316 | /// GMMx5490 |
| 9317 | typedef union { |
| 9318 | struct { ///< |
| 9319 | UINT32 FbReadEn:1 ; ///< |
| 9320 | UINT32 FbWriteEn:1 ; ///< |
| 9321 | UINT32 Reserved_31_2:30; ///< |
| 9322 | } Field; ///< |
| 9323 | UINT32 Value; ///< |
| 9324 | } GMMx5490_STRUCT; |
| 9325 | |
| 9326 | |
| 9327 | /// SMUx73 |
| 9328 | typedef union { |
| 9329 | struct { ///< |
| 9330 | UINT32 DisLclkGating:1 ; ///< |
| 9331 | UINT32 DisSclkGating:1 ; ///< |
| 9332 | UINT32 Reserved_15_2:14; ///< |
| 9333 | } Field; ///< |
| 9334 | UINT32 Value; ///< |
| 9335 | } SMUx73_STRUCT; |
| 9336 | |
| 9337 | // **** MSRC001_001A Register Definition **** |
| 9338 | // Address |
| 9339 | #define MSRC001_001A_ADDRESS 0xc001001a |
| 9340 | |
| 9341 | // Type |
| 9342 | #define MSRC001_001A_TYPE TYPE_MSR |
| 9343 | // Field Data |
| 9344 | #define MSRC001_001A_RAZ_22_0_OFFSET 0 |
| 9345 | #define MSRC001_001A_RAZ_22_0_WIDTH 23 |
| 9346 | #define MSRC001_001A_RAZ_22_0_MASK 0x7fffff |
| 9347 | #define MSRC001_001A_TOM_39_23__OFFSET 23 |
| 9348 | #define MSRC001_001A_TOM_39_23__WIDTH 17 |
| 9349 | #define MSRC001_001A_TOM_39_23__MASK 0xffff800000 |
| 9350 | #define MSRC001_001A_MBZ_47_40_OFFSET 40 |
| 9351 | #define MSRC001_001A_MBZ_47_40_WIDTH 8 |
| 9352 | #define MSRC001_001A_MBZ_47_40_MASK 0xff0000000000 |
| 9353 | #define MSRC001_001A_RAZ_63_48_OFFSET 48 |
| 9354 | #define MSRC001_001A_RAZ_63_48_WIDTH 16 |
| 9355 | #define MSRC001_001A_RAZ_63_48_MASK 0xffff000000000000 |
| 9356 | |
| 9357 | /// MSRC001_001A |
| 9358 | typedef union { |
| 9359 | struct { ///< |
| 9360 | UINT64 RAZ_22_0:23; ///< |
| 9361 | UINT64 TOM_39_23_:17; ///< |
| 9362 | UINT64 MBZ_47_40:8 ; ///< |
| 9363 | UINT64 RAZ_63_48:16; ///< |
| 9364 | } Field; ///< |
| 9365 | UINT64 Value; ///< |
| 9366 | } MSRC001_001A_STRUCT; |
| 9367 | |
| 9368 | |
| 9369 | |
| 9370 | |
| 9371 | |
| 9372 | |
| 9373 | |
| 9374 | // **** D0F0xE4_WRAP_8013 Register Definition **** |
| 9375 | // Address |
| 9376 | #define D0F0xE4_WRAP_8013_ADDRESS 0x8013 |
| 9377 | |
| 9378 | // Field Data |
| 9379 | #define D0F0xE4_WRAP_8013_MasterPciePllA_OFFSET 0 |
| 9380 | #define D0F0xE4_WRAP_8013_MasterPciePllA_WIDTH 1 |
| 9381 | #define D0F0xE4_WRAP_8013_MasterPciePllA_MASK 0x1 |
| 9382 | #define D0F0xE4_WRAP_8013_Reserved_1_1_OFFSET 1 |
| 9383 | #define D0F0xE4_WRAP_8013_Reserved_1_1_WIDTH 1 |
| 9384 | #define D0F0xE4_WRAP_8013_Reserved_1_1_MASK 0x2 |
| 9385 | #define D0F0xE4_WRAP_8013_Reserved_2_2_OFFSET 2 |
| 9386 | #define D0F0xE4_WRAP_8013_Reserved_2_2_WIDTH 1 |
| 9387 | #define D0F0xE4_WRAP_8013_Reserved_2_2_MASK 0x4 |
| 9388 | #define D0F0xE4_WRAP_8013_Reserved_3_3_OFFSET 3 |
| 9389 | #define D0F0xE4_WRAP_8013_Reserved_3_3_WIDTH 1 |
| 9390 | #define D0F0xE4_WRAP_8013_Reserved_3_3_MASK 0x8 |
| 9391 | #define D0F0xE4_WRAP_8013_ClkDividerResetOverrideA_OFFSET 4 |
| 9392 | #define D0F0xE4_WRAP_8013_ClkDividerResetOverrideA_WIDTH 1 |
| 9393 | #define D0F0xE4_WRAP_8013_ClkDividerResetOverrideA_MASK 0x10 |
| 9394 | #define D0F0xE4_WRAP_8013_Reserved_5_5_OFFSET 5 |
| 9395 | #define D0F0xE4_WRAP_8013_Reserved_5_5_WIDTH 1 |
| 9396 | #define D0F0xE4_WRAP_8013_Reserved_5_5_MASK 0x20 |
| 9397 | #define D0F0xE4_WRAP_8013_Reserved_6_6_OFFSET 6 |
| 9398 | #define D0F0xE4_WRAP_8013_Reserved_6_6_WIDTH 1 |
| 9399 | #define D0F0xE4_WRAP_8013_Reserved_6_6_MASK 0x40 |
| 9400 | #define D0F0xE4_WRAP_8013_Reserved_7_7_OFFSET 7 |
| 9401 | #define D0F0xE4_WRAP_8013_Reserved_7_7_WIDTH 1 |
| 9402 | #define D0F0xE4_WRAP_8013_Reserved_7_7_MASK 0x80 |
| 9403 | #define D0F0xE4_WRAP_8013_TxclkSelCoreOverride_OFFSET 8 |
| 9404 | #define D0F0xE4_WRAP_8013_TxclkSelCoreOverride_WIDTH 1 |
| 9405 | #define D0F0xE4_WRAP_8013_TxclkSelCoreOverride_MASK 0x100 |
| 9406 | #define D0F0xE4_WRAP_8013_TxclkSelPifAOverride_OFFSET 9 |
| 9407 | #define D0F0xE4_WRAP_8013_TxclkSelPifAOverride_WIDTH 1 |
| 9408 | #define D0F0xE4_WRAP_8013_TxclkSelPifAOverride_MASK 0x200 |
| 9409 | #define D0F0xE4_WRAP_8013_Reserved_10_10_OFFSET 10 |
| 9410 | #define D0F0xE4_WRAP_8013_Reserved_10_10_WIDTH 1 |
| 9411 | #define D0F0xE4_WRAP_8013_Reserved_10_10_MASK 0x400 |
| 9412 | #define D0F0xE4_WRAP_8013_Reserved_11_11_OFFSET 11 |
| 9413 | #define D0F0xE4_WRAP_8013_Reserved_11_11_WIDTH 1 |
| 9414 | #define D0F0xE4_WRAP_8013_Reserved_11_11_MASK 0x800 |
| 9415 | #define D0F0xE4_WRAP_8013_Reserved_12_12_OFFSET 12 |
| 9416 | #define D0F0xE4_WRAP_8013_Reserved_12_12_WIDTH 1 |
| 9417 | #define D0F0xE4_WRAP_8013_Reserved_12_12_MASK 0x1000 |
| 9418 | #define D0F0xE4_WRAP_8013_Reserved_15_13_OFFSET 13 |
| 9419 | #define D0F0xE4_WRAP_8013_Reserved_15_13_WIDTH 3 |
| 9420 | #define D0F0xE4_WRAP_8013_Reserved_15_13_MASK 0xe000 |
| 9421 | #define D0F0xE4_WRAP_8013_Reserved_16_16_OFFSET 16 |
| 9422 | #define D0F0xE4_WRAP_8013_Reserved_16_16_WIDTH 1 |
| 9423 | #define D0F0xE4_WRAP_8013_Reserved_16_16_MASK 0x10000 |
| 9424 | #define D0F0xE4_WRAP_8013_Reserved_19_17_OFFSET 17 |
| 9425 | #define D0F0xE4_WRAP_8013_Reserved_19_17_WIDTH 3 |
| 9426 | #define D0F0xE4_WRAP_8013_Reserved_19_17_MASK 0xe0000 |
| 9427 | #define D0F0xE4_WRAP_8013_Reserved_20_20_OFFSET 20 |
| 9428 | #define D0F0xE4_WRAP_8013_Reserved_20_20_WIDTH 1 |
| 9429 | #define D0F0xE4_WRAP_8013_Reserved_20_20_MASK 0x100000 |
| 9430 | #define D0F0xE4_WRAP_8013_Reserved_31_21_OFFSET 21 |
| 9431 | #define D0F0xE4_WRAP_8013_Reserved_31_21_WIDTH 11 |
| 9432 | #define D0F0xE4_WRAP_8013_Reserved_31_21_MASK 0xffe00000 |
| 9433 | |
| 9434 | /// D0F0xE4_WRAP_8013 |
| 9435 | typedef union { |
| 9436 | struct { ///< |
| 9437 | UINT32 MasterPciePllA:1 ; ///< |
| 9438 | UINT32 MasterPciePllB:1 ; ///< |
| 9439 | UINT32 MasterPciePllC:1 ; ///< |
| 9440 | UINT32 MasterPciePllD:1 ; ///< |
| 9441 | UINT32 ClkDividerResetOverrideA:1 ; ///< |
| 9442 | UINT32 Reserved_5_5:1 ; ///< |
| 9443 | UINT32 Reserved_6_6:1 ; ///< |
| 9444 | UINT32 Reserved_7_7:1 ; ///< |
| 9445 | UINT32 TxclkSelCoreOverride:1 ; ///< |
| 9446 | UINT32 TxclkSelPifAOverride:1 ; ///< |
| 9447 | UINT32 Reserved_10_10:1 ; ///< |
| 9448 | UINT32 Reserved_11_11:1 ; ///< |
| 9449 | UINT32 Reserved_12_12:1 ; ///< |
| 9450 | UINT32 Reserved_15_13:3 ; ///< |
| 9451 | UINT32 Reserved_16_16:1 ; ///< |
| 9452 | UINT32 Reserved_19_17:3 ; ///< |
| 9453 | UINT32 Reserved_20_20:1 ; ///< |
| 9454 | UINT32 Reserved_31_21:11; ///< |
| 9455 | } Field; ///< |
| 9456 | UINT32 Value; ///< |
| 9457 | } D0F0xE4_WRAP_8013_STRUCT; |
| 9458 | |
| 9459 | // **** D0F0xE4_WRAP_8014 Register Definition **** |
| 9460 | // Address |
| 9461 | #define D0F0xE4_WRAP_8014_ADDRESS 0x8014 |
| 9462 | |
| 9463 | // Field Data |
| 9464 | #define D0F0xE4_WRAP_8014_TxclkPermGateEnable_OFFSET 0 |
| 9465 | #define D0F0xE4_WRAP_8014_TxclkPermGateEnable_WIDTH 1 |
| 9466 | #define D0F0xE4_WRAP_8014_TxclkPermGateEnable_MASK 0x1 |
| 9467 | #define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_OFFSET 1 |
| 9468 | #define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_WIDTH 1 |
| 9469 | #define D0F0xE4_WRAP_8014_TxclkPrbsGateEnable_MASK 0x2 |
| 9470 | #define D0F0xE4_WRAP_8014_Reserved_2_2_OFFSET 2 |
| 9471 | #define D0F0xE4_WRAP_8014_Reserved_2_2_WIDTH 1 |
| 9472 | #define D0F0xE4_WRAP_8014_Reserved_2_2_MASK 0x4 |
| 9473 | #define D0F0xE4_WRAP_8014_Reserved_3_3_OFFSET 3 |
| 9474 | #define D0F0xE4_WRAP_8014_Reserved_3_3_WIDTH 1 |
| 9475 | #define D0F0xE4_WRAP_8014_Reserved_3_3_MASK 0x8 |
| 9476 | #define D0F0xE4_WRAP_8014_Reserved_4_4_OFFSET 4 |
| 9477 | #define D0F0xE4_WRAP_8014_Reserved_4_4_WIDTH 1 |
| 9478 | #define D0F0xE4_WRAP_8014_Reserved_4_4_MASK 0x10 |
| 9479 | #define D0F0xE4_WRAP_8014_Reserved_5_5_OFFSET 5 |
| 9480 | #define D0F0xE4_WRAP_8014_Reserved_5_5_WIDTH 1 |
| 9481 | #define D0F0xE4_WRAP_8014_Reserved_5_5_MASK 0x20 |
| 9482 | #define D0F0xE4_WRAP_8014_Reserved_6_6_OFFSET 6 |
| 9483 | #define D0F0xE4_WRAP_8014_Reserved_6_6_WIDTH 1 |
| 9484 | #define D0F0xE4_WRAP_8014_Reserved_6_6_MASK 0x40 |
| 9485 | #define D0F0xE4_WRAP_8014_Reserved_7_7_OFFSET 7 |
| 9486 | #define D0F0xE4_WRAP_8014_Reserved_7_7_WIDTH 1 |
| 9487 | #define D0F0xE4_WRAP_8014_Reserved_7_7_MASK 0x80 |
| 9488 | #define D0F0xE4_WRAP_8014_Reserved_8_8_OFFSET 8 |
| 9489 | #define D0F0xE4_WRAP_8014_Reserved_8_8_WIDTH 1 |
| 9490 | #define D0F0xE4_WRAP_8014_Reserved_8_8_MASK 0x100 |
| 9491 | #define D0F0xE4_WRAP_8014_Reserved_9_9_OFFSET 9 |
| 9492 | #define D0F0xE4_WRAP_8014_Reserved_9_9_WIDTH 1 |
| 9493 | #define D0F0xE4_WRAP_8014_Reserved_9_9_MASK 0x200 |
| 9494 | #define D0F0xE4_WRAP_8014_Reserved_10_10_OFFSET 10 |
| 9495 | #define D0F0xE4_WRAP_8014_Reserved_10_10_WIDTH 1 |
| 9496 | #define D0F0xE4_WRAP_8014_Reserved_10_10_MASK 0x400 |
| 9497 | #define D0F0xE4_WRAP_8014_Reserved_11_11_OFFSET 11 |
| 9498 | #define D0F0xE4_WRAP_8014_Reserved_11_11_WIDTH 1 |
| 9499 | #define D0F0xE4_WRAP_8014_Reserved_11_11_MASK 0x800 |
| 9500 | #define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_OFFSET 12 |
| 9501 | #define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_WIDTH 1 |
| 9502 | #define D0F0xE4_WRAP_8014_PcieGatePifA1xEnable_MASK 0x1000 |
| 9503 | #define D0F0xE4_WRAP_8014_Reserved_13_13_OFFSET 13 |
| 9504 | #define D0F0xE4_WRAP_8014_Reserved_13_13_WIDTH 1 |
| 9505 | #define D0F0xE4_WRAP_8014_Reserved_13_13_MASK 0x2000 |
| 9506 | #define D0F0xE4_WRAP_8014_Reserved_14_14_OFFSET 14 |
| 9507 | #define D0F0xE4_WRAP_8014_Reserved_14_14_WIDTH 1 |
| 9508 | #define D0F0xE4_WRAP_8014_Reserved_14_14_MASK 0x4000 |
| 9509 | #define D0F0xE4_WRAP_8014_Reserved_15_15_OFFSET 15 |
| 9510 | #define D0F0xE4_WRAP_8014_Reserved_15_15_WIDTH 1 |
| 9511 | #define D0F0xE4_WRAP_8014_Reserved_15_15_MASK 0x8000 |
| 9512 | #define D0F0xE4_WRAP_8014_PcieGatePifA2p5xEnable_OFFSET 16 |
| 9513 | #define D0F0xE4_WRAP_8014_PcieGatePifA2p5xEnable_WIDTH 1 |
| 9514 | #define D0F0xE4_WRAP_8014_PcieGatePifA2p5xEnable_MASK 0x10000 |
| 9515 | #define D0F0xE4_WRAP_8014_Reserved_17_17_OFFSET 17 |
| 9516 | #define D0F0xE4_WRAP_8014_Reserved_17_17_WIDTH 1 |
| 9517 | #define D0F0xE4_WRAP_8014_Reserved_17_17_MASK 0x20000 |
| 9518 | #define D0F0xE4_WRAP_8014_Reserved_18_18_OFFSET 18 |
| 9519 | #define D0F0xE4_WRAP_8014_Reserved_18_18_WIDTH 1 |
| 9520 | #define D0F0xE4_WRAP_8014_Reserved_18_18_MASK 0x40000 |
| 9521 | #define D0F0xE4_WRAP_8014_Reserved_19_19_OFFSET 19 |
| 9522 | #define D0F0xE4_WRAP_8014_Reserved_19_19_WIDTH 1 |
| 9523 | #define D0F0xE4_WRAP_8014_Reserved_19_19_MASK 0x80000 |
| 9524 | #define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_OFFSET 20 |
| 9525 | #define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_WIDTH 1 |
| 9526 | #define D0F0xE4_WRAP_8014_TxclkPermGateOnlyWhenPllPwrDn_MASK 0x100000 |
| 9527 | #define D0F0xE4_WRAP_8014_Reserved_31_21_OFFSET 21 |
| 9528 | #define D0F0xE4_WRAP_8014_Reserved_31_21_WIDTH 11 |
| 9529 | #define D0F0xE4_WRAP_8014_Reserved_31_21_MASK 0xffe00000 |
| 9530 | |
| 9531 | /// D0F0xE4_WRAP_8014 |
| 9532 | typedef union { |
| 9533 | struct { |
| 9534 | UINT32 TxclkPermGateEnable:1 ; ///< |
| 9535 | UINT32 TxclkPrbsGateEnable:1 ; ///< |
| 9536 | UINT32 DdiGatePifA1xEnable:1 ; ///< |
| 9537 | UINT32 DdiGatePifB1xEnable:1 ; ///< |
| 9538 | UINT32 DdiGatePifC1xEnable:1 ; ///< |
| 9539 | UINT32 DdiGatePifD1xEnable:1 ; ///< |
| 9540 | UINT32 DdiGateDigAEnable:1 ; ///< |
| 9541 | UINT32 DdiGateDigBEnable:1 ; ///< |
| 9542 | UINT32 DdiGatePifA2p5xEnable:1 ; ///< |
| 9543 | UINT32 DdiGatePifB2p5xEnable:1 ; ///< |
| 9544 | UINT32 DdiGatePifC2p5xEnable:1 ; ///< |
| 9545 | UINT32 DdiGatePifD2p5xEnable:1 ; ///< |
| 9546 | UINT32 PcieGatePifA1xEnable:1 ; ///< |
| 9547 | UINT32 PcieGatePifB1xEnable:1 ; ///< |
| 9548 | UINT32 PcieGatePifC1xEnable:1 ; ///< |
| 9549 | UINT32 PcieGatePifD1xEnable:1 ; ///< |
| 9550 | UINT32 PcieGatePifA2p5xEnable:1 ; ///< |
| 9551 | UINT32 PcieGatePifB2p5xEnable:1 ; ///< |
| 9552 | UINT32 PcieGatePifC2p5xEnable:1 ; ///< |
| 9553 | UINT32 PcieGatePifD2p5xEnable:1 ; ///< |
| 9554 | UINT32 TxclkPermGateOnlyWhenPllPwrDn:1 ; ///< |
| 9555 | UINT32 Reserved_31_21:11; ///< |
| 9556 | } Field; ///< |
| 9557 | UINT32 Value; ///< |
| 9558 | } D0F0xE4_WRAP_8014_STRUCT; |
| 9559 | |
| 9560 | |
| 9561 | |
| 9562 | |
| 9563 | |
| 9564 | // **** GMMx6124 Register Definition **** |
| 9565 | // Address |
| 9566 | #define GMMx6124_ADDRESS 0x6124 |
| 9567 | |
| 9568 | // **** GMMx6124 Register Definition **** |
| 9569 | // Address |
| 9570 | #define GMMx6124_ADDRESS 0x6124 |
| 9571 | |
| 9572 | // Type |
| 9573 | #define GMMx6124_TYPE TYPE_GMM |
| 9574 | // Field Data |
| 9575 | #define GMMx6124_DoutScratch_OFFSET 0 |
| 9576 | #define GMMx6124_DoutScratch_WIDTH 32 |
| 9577 | #define GMMx6124_DoutScratch_MASK 0xffffffff |
| 9578 | |
| 9579 | |
| 9580 | |
| 9581 | |
| 9582 | |
| 9583 | |
| 9584 | |
| 9585 | |
| 9586 | // **** D0F0xE4_CORE_0020 Register Definition **** |
| 9587 | // Address |
| 9588 | #define D0F0xE4_CORE_0020_ADDRESS 0x20 |
| 9589 | |
| 9590 | // Type |
| 9591 | #define D0F0xE4_CORE_0020_TYPE TYPE_D0F0xE4 |
| 9592 | // Field Data |
| 9593 | #define D0F0xE4_CORE_0020_Reserved_1_0_OFFSET 0 |
| 9594 | #define D0F0xE4_CORE_0020_Reserved_1_0_WIDTH 2 |
| 9595 | #define D0F0xE4_CORE_0020_Reserved_1_0_MASK 0x3 |
| 9596 | #define D0F0xE4_CORE_0020_Reserved_31_12_OFFSET 12 |
| 9597 | #define D0F0xE4_CORE_0020_Reserved_31_12_WIDTH 20 |
| 9598 | #define D0F0xE4_CORE_0020_Reserved_31_12_MASK 0xfffff000 |
| 9599 | |
| 9600 | /// D0F0xE4_CORE_0020 |
| 9601 | typedef union { |
| 9602 | struct { ///< |
| 9603 | UINT32 Reserved_1_0:2 ; ///< |
| 9604 | UINT32 :1 ; ///< |
| 9605 | UINT32 :1 ; ///< |
| 9606 | UINT32 :1 ; ///< |
| 9607 | UINT32 :1 ; ///< |
| 9608 | UINT32 :2 ; ///< |
| 9609 | UINT32 :1 ; ///< |
| 9610 | UINT32 :1 ; ///< |
| 9611 | UINT32 :1 ; ///< |
| 9612 | UINT32 :1 ; ///< |
| 9613 | UINT32 Reserved_31_12:20; ///< |
| 9614 | } Field; ///< |
| 9615 | UINT32 Value; ///< |
| 9616 | } D0F0xE4_CORE_0020_STRUCT; |
| 9617 | |
| 9618 | // **** D0F0xE4_CORE_0010 Register Definition **** |
| 9619 | // Address |
| 9620 | #define D0F0xE4_CORE_0010_ADDRESS 0x10 |
| 9621 | |
| 9622 | // Type |
| 9623 | #define D0F0xE4_CORE_0010_TYPE TYPE_D0F0xE4 |
| 9624 | // Field Data |
| 9625 | #define D0F0xE4_CORE_0010_HwInitWrLock_OFFSET 0 |
| 9626 | #define D0F0xE4_CORE_0010_HwInitWrLock_WIDTH 1 |
| 9627 | #define D0F0xE4_CORE_0010_HwInitWrLock_MASK 0x1 |
| 9628 | #define D0F0xE4_CORE_0010_LcHotPlugDelSel_OFFSET 1 |
| 9629 | #define D0F0xE4_CORE_0010_LcHotPlugDelSel_WIDTH 3 |
| 9630 | #define D0F0xE4_CORE_0010_LcHotPlugDelSel_MASK 0xe |
| 9631 | #define D0F0xE4_CORE_0010_Reserved_6_4_OFFSET 4 |
| 9632 | #define D0F0xE4_CORE_0010_Reserved_6_4_WIDTH 3 |
| 9633 | #define D0F0xE4_CORE_0010_Reserved_6_4_MASK 0x70 |
| 9634 | |
| 9635 | /// D0F0xE4_CORE_0010 |
| 9636 | typedef union { |
| 9637 | struct { ///< |
| 9638 | UINT32 HwInitWrLock:1 ; ///< |
| 9639 | UINT32 LcHotPlugDelSel:3 ; ///< |
| 9640 | UINT32 Reserved_6_4:3 ; ///< |
| 9641 | UINT32 :1 ; ///< |
| 9642 | UINT32 :1 ; ///< |
| 9643 | UINT32 :1 ; ///< |
| 9644 | UINT32 :3 ; ///< |
| 9645 | UINT32 :3 ; ///< |
| 9646 | UINT32 :1 ; ///< |
| 9647 | UINT32 :1 ; ///< |
| 9648 | UINT32 :1 ; ///< |
| 9649 | UINT32 :1 ; ///< |
| 9650 | UINT32 :1 ; ///< |
| 9651 | UINT32 :1 ; ///< |
| 9652 | UINT32 :1 ; ///< |
| 9653 | UINT32 :1 ; ///< |
| 9654 | UINT32 :6 ; ///< |
| 9655 | UINT32 :1 ; ///< |
| 9656 | UINT32 :1 ; ///< |
| 9657 | } Field; ///< |
| 9658 | UINT32 Value; ///< |
| 9659 | } D0F0xE4_CORE_0010_STRUCT; |
| 9660 | |
| 9661 | |
| 9662 | // **** D0F0x98_x0C Register Definition **** |
| 9663 | // Address |
| 9664 | #define D0F0x98_x0C_ADDRESS 0xc |
| 9665 | |
| 9666 | // Type |
| 9667 | #define D0F0x98_x0C_TYPE TYPE_D0F0x98 |
| 9668 | // Field Data |
| 9669 | #define D0F0x98_x0C_GcmWrrLenA_OFFSET 0 |
| 9670 | #define D0F0x98_x0C_GcmWrrLenA_WIDTH 8 |
| 9671 | #define D0F0x98_x0C_GcmWrrLenA_MASK 0xff |
| 9672 | #define D0F0x98_x0C_GcmWrrLenB_OFFSET 8 |
| 9673 | #define D0F0x98_x0C_GcmWrrLenB_WIDTH 8 |
| 9674 | #define D0F0x98_x0C_GcmWrrLenB_MASK 0xff00 |
| 9675 | #define D0F0x98_x0C_Reserved_29_16_OFFSET 16 |
| 9676 | #define D0F0x98_x0C_Reserved_29_16_WIDTH 14 |
| 9677 | #define D0F0x98_x0C_Reserved_29_16_MASK 0x3fff0000 |
| 9678 | #define D0F0x98_x0C_StrictSelWinnerEn_OFFSET 30 |
| 9679 | #define D0F0x98_x0C_StrictSelWinnerEn_WIDTH 1 |
| 9680 | #define D0F0x98_x0C_StrictSelWinnerEn_MASK 0x40000000 |
| 9681 | |
| 9682 | /// D0F0x98_x0C |
| 9683 | typedef union { |
| 9684 | struct { ///< |
| 9685 | UINT32 GcmWrrLenA:8 ; ///< |
| 9686 | UINT32 GcmWrrLenB:8 ; ///< |
| 9687 | UINT32 Reserved_29_16:14; ///< |
| 9688 | UINT32 StrictSelWinnerEn:1 ; ///< |
| 9689 | UINT32 :1 ; ///< |
| 9690 | } Field; ///< |
| 9691 | UINT32 Value; ///< |
| 9692 | } D0F0x98_x0C_STRUCT; |
| 9693 | |
| 9694 | |
| 9695 | |
| 9696 | |
| 9697 | |
| 9698 | |
| 9699 | |
| 9700 | |
| 9701 | |
| 9702 | |
| 9703 | |
| 9704 | |
| 9705 | |
| 9706 | |
| 9707 | |
| 9708 | |
| 9709 | |
| 9710 | |
| 9711 | |
| 9712 | |
| 9713 | |
| 9714 | // **** D0F0xE4_WRAP_8063 Register Definition **** |
| 9715 | // Address |
| 9716 | #define D0F0xE4_WRAP_8063_ADDRESS 0x8063 |
| 9717 | |
| 9718 | // Type |
| 9719 | #define D0F0xE4_WRAP_8063_TYPE TYPE_D0F0xE4 |
| 9720 | // Field Data |
| 9721 | #define D0F0xE4_WRAP_8063_Reserved_0_0_OFFSET 0 |
| 9722 | #define D0F0xE4_WRAP_8063_Reserved_0_0_WIDTH 1 |
| 9723 | #define D0F0xE4_WRAP_8063_Reserved_0_0_MASK 0x1 |
| 9724 | #define D0F0xE4_WRAP_8063_Reserved_25_25_OFFSET 25 |
| 9725 | #define D0F0xE4_WRAP_8063_Reserved_25_25_WIDTH 1 |
| 9726 | #define D0F0xE4_WRAP_8063_Reserved_25_25_MASK 0x2000000 |
| 9727 | #define D0F0xE4_WRAP_8063_Reserved_27_26_OFFSET 26 |
| 9728 | #define D0F0xE4_WRAP_8063_Reserved_27_26_WIDTH 2 |
| 9729 | #define D0F0xE4_WRAP_8063_Reserved_27_26_MASK 0xc000000 |
| 9730 | #define D0F0xE4_WRAP_8063_Reserved_31_28_OFFSET 28 |
| 9731 | #define D0F0xE4_WRAP_8063_Reserved_31_28_WIDTH 4 |
| 9732 | #define D0F0xE4_WRAP_8063_Reserved_31_28_MASK 0xf0000000 |
| 9733 | |
| 9734 | /// D0F0xE4_WRAP_8063 |
| 9735 | typedef union { |
| 9736 | struct { ///< |
| 9737 | UINT32 Reserved_0_0:1 ; ///< |
| 9738 | UINT32 :1 ; ///< |
| 9739 | UINT32 :1 ; ///< |
| 9740 | UINT32 :1 ; ///< |
| 9741 | UINT32 line331:1 ; ///< |
| 9742 | UINT32 line332:1 ; ///< |
| 9743 | UINT32 :1 ; ///< |
| 9744 | UINT32 :1 ; ///< |
| 9745 | UINT32 :2 ; ///< |
| 9746 | UINT32 :1 ; ///< |
| 9747 | UINT32 :1 ; ///< |
| 9748 | UINT32 line338:1 ; ///< |
| 9749 | UINT32 line339:1 ; ///< |
| 9750 | UINT32 line340:1 ; ///< |
| 9751 | UINT32 :1 ; ///< |
| 9752 | UINT32 :1 ; ///< |
| 9753 | UINT32 :1 ; ///< |
| 9754 | UINT32 :2 ; ///< |
| 9755 | UINT32 :1 ; ///< |
| 9756 | UINT32 :1 ; ///< |
| 9757 | UINT32 :2 ; ///< |
| 9758 | UINT32 :1 ; ///< |
| 9759 | UINT32 Reserved_25_25:1 ; ///< |
| 9760 | UINT32 Reserved_27_26:2 ; ///< |
| 9761 | UINT32 Reserved_31_28:4 ; ///< |
| 9762 | } Field; ///< |
| 9763 | UINT32 Value; ///< |
| 9764 | } D0F0xE4_WRAP_8063_STRUCT; |
| 9765 | |
| 9766 | // **** D0F0xE4_WRAP_8015 Register Definition **** |
| 9767 | // Address |
| 9768 | #define D0F0xE4_WRAP_8015_ADDRESS 0x8015 |
| 9769 | |
| 9770 | // Type |
| 9771 | #define D0F0xE4_WRAP_8015_TYPE TYPE_D0F0xE4 |
| 9772 | // Field Data |
| 9773 | #define D0F0xE4_WRAP_8015_EnableD0StateReport_OFFSET 0 |
| 9774 | #define D0F0xE4_WRAP_8015_EnableD0StateReport_WIDTH 1 |
| 9775 | #define D0F0xE4_WRAP_8015_EnableD0StateReport_MASK 0x1 |
| 9776 | #define D0F0xE4_WRAP_8015_Reserved_1_1_OFFSET 1 |
| 9777 | #define D0F0xE4_WRAP_8015_Reserved_1_1_WIDTH 1 |
| 9778 | #define D0F0xE4_WRAP_8015_Reserved_1_1_MASK 0x2 |
| 9779 | #define D0F0xE4_WRAP_8015_SlowRefclkThroughTxclk2p5x_OFFSET 2 |
| 9780 | #define D0F0xE4_WRAP_8015_SlowRefclkThroughTxclk2p5x_WIDTH 1 |
| 9781 | #define D0F0xE4_WRAP_8015_SlowRefclkThroughTxclk2p5x_MASK 0x4 |
| 9782 | #define D0F0xE4_WRAP_8015_SlowRefclkEnableTxclk2p5x_OFFSET 3 |
| 9783 | #define D0F0xE4_WRAP_8015_SlowRefclkEnableTxclk2p5x_WIDTH 1 |
| 9784 | #define D0F0xE4_WRAP_8015_SlowRefclkEnableTxclk2p5x_MASK 0x8 |
| 9785 | #define D0F0xE4_WRAP_8015_SlowRefclkDivideTxclk2p5x_OFFSET 4 |
| 9786 | #define D0F0xE4_WRAP_8015_SlowRefclkDivideTxclk2p5x_WIDTH 2 |
| 9787 | #define D0F0xE4_WRAP_8015_SlowRefclkDivideTxclk2p5x_MASK 0x30 |
| 9788 | #define D0F0xE4_WRAP_8015_SlowRefclkBurstTxclk2p5x_OFFSET 6 |
| 9789 | #define D0F0xE4_WRAP_8015_SlowRefclkBurstTxclk2p5x_WIDTH 2 |
| 9790 | #define D0F0xE4_WRAP_8015_SlowRefclkBurstTxclk2p5x_MASK 0xc0 |
| 9791 | #define D0F0xE4_WRAP_8015_Reserved_8_8_OFFSET 8 |
| 9792 | #define D0F0xE4_WRAP_8015_Reserved_8_8_WIDTH 1 |
| 9793 | #define D0F0xE4_WRAP_8015_Reserved_8_8_MASK 0x100 |
| 9794 | #define D0F0xE4_WRAP_8015_SlowRefclkLcntGateForce_OFFSET 9 |
| 9795 | #define D0F0xE4_WRAP_8015_SlowRefclkLcntGateForce_WIDTH 1 |
| 9796 | #define D0F0xE4_WRAP_8015_SlowRefclkLcntGateForce_MASK 0x200 |
| 9797 | #define D0F0xE4_WRAP_8015_SlowRefclkThroughTxclk1x_OFFSET 10 |
| 9798 | #define D0F0xE4_WRAP_8015_SlowRefclkThroughTxclk1x_WIDTH 1 |
| 9799 | #define D0F0xE4_WRAP_8015_SlowRefclkThroughTxclk1x_MASK 0x400 |
| 9800 | #define D0F0xE4_WRAP_8015_SlowRefclkEnableTxclk1x_OFFSET 11 |
| 9801 | #define D0F0xE4_WRAP_8015_SlowRefclkEnableTxclk1x_WIDTH 1 |
| 9802 | #define D0F0xE4_WRAP_8015_SlowRefclkEnableTxclk1x_MASK 0x800 |
| 9803 | #define D0F0xE4_WRAP_8015_SlowRefclkDivideTxclk1x_OFFSET 12 |
| 9804 | #define D0F0xE4_WRAP_8015_SlowRefclkDivideTxclk1x_WIDTH 2 |
| 9805 | #define D0F0xE4_WRAP_8015_SlowRefclkDivideTxclk1x_MASK 0x3000 |
| 9806 | #define D0F0xE4_WRAP_8015_SlowRefclkBurstTxclk1x_OFFSET 14 |
| 9807 | #define D0F0xE4_WRAP_8015_SlowRefclkBurstTxclk1x_WIDTH 2 |
| 9808 | #define D0F0xE4_WRAP_8015_SlowRefclkBurstTxclk1x_MASK 0xc000 |
| 9809 | #define D0F0xE4_WRAP_8015_RefclkRegsGateLatency_OFFSET 16 |
| 9810 | #define D0F0xE4_WRAP_8015_RefclkRegsGateLatency_WIDTH 6 |
| 9811 | #define D0F0xE4_WRAP_8015_RefclkRegsGateLatency_MASK 0x3f0000 |
| 9812 | #define D0F0xE4_WRAP_8015_Reserved_22_22_OFFSET 22 |
| 9813 | #define D0F0xE4_WRAP_8015_Reserved_22_22_WIDTH 1 |
| 9814 | #define D0F0xE4_WRAP_8015_Reserved_22_22_MASK 0x400000 |
| 9815 | #define D0F0xE4_WRAP_8015_RefclkRegsGateEnable_OFFSET 23 |
| 9816 | #define D0F0xE4_WRAP_8015_RefclkRegsGateEnable_WIDTH 1 |
| 9817 | #define D0F0xE4_WRAP_8015_RefclkRegsGateEnable_MASK 0x800000 |
| 9818 | #define D0F0xE4_WRAP_8015_RefclkBphyGateLatency_OFFSET 24 |
| 9819 | #define D0F0xE4_WRAP_8015_RefclkBphyGateLatency_WIDTH 6 |
| 9820 | #define D0F0xE4_WRAP_8015_RefclkBphyGateLatency_MASK 0x3f000000 |
| 9821 | #define D0F0xE4_WRAP_8015_Reserved_30_30_OFFSET 30 |
| 9822 | #define D0F0xE4_WRAP_8015_Reserved_30_30_WIDTH 1 |
| 9823 | #define D0F0xE4_WRAP_8015_Reserved_30_30_MASK 0x40000000 |
| 9824 | #define D0F0xE4_WRAP_8015_RefclkBphyGateEnable_OFFSET 31 |
| 9825 | #define D0F0xE4_WRAP_8015_RefclkBphyGateEnable_WIDTH 1 |
| 9826 | #define D0F0xE4_WRAP_8015_RefclkBphyGateEnable_MASK 0x80000000 |
| 9827 | |
| 9828 | /// D0F0xE4_WRAP_8015 |
| 9829 | typedef union { |
| 9830 | struct { ///< |
| 9831 | UINT32 EnableD0StateReport:1 ; ///< |
| 9832 | UINT32 Reserved_1_1:1 ; ///< |
| 9833 | UINT32 SlowRefclkThroughTxclk2p5x:1 ; ///< |
| 9834 | UINT32 SlowRefclkEnableTxclk2p5x:1 ; ///< |
| 9835 | UINT32 SlowRefclkDivideTxclk2p5x:2 ; ///< |
| 9836 | UINT32 SlowRefclkBurstTxclk2p5x:2 ; ///< |
| 9837 | UINT32 Reserved_8_8:1 ; ///< |
| 9838 | UINT32 SlowRefclkLcntGateForce:1 ; ///< |
| 9839 | UINT32 SlowRefclkThroughTxclk1x:1 ; ///< |
| 9840 | UINT32 SlowRefclkEnableTxclk1x:1 ; ///< |
| 9841 | UINT32 SlowRefclkDivideTxclk1x:2 ; ///< |
| 9842 | UINT32 SlowRefclkBurstTxclk1x:2 ; ///< |
| 9843 | UINT32 RefclkRegsGateLatency:6 ; ///< |
| 9844 | UINT32 Reserved_22_22:1 ; ///< |
| 9845 | UINT32 RefclkRegsGateEnable:1 ; ///< |
| 9846 | UINT32 RefclkBphyGateLatency:6 ; ///< |
| 9847 | UINT32 Reserved_30_30:1 ; ///< |
| 9848 | UINT32 RefclkBphyGateEnable:1 ; ///< |
| 9849 | } Field; ///< |
| 9850 | UINT32 Value; ///< |
| 9851 | } D0F0xE4_WRAP_8015_STRUCT; |
| 9852 | |
| 9853 | // **** DxF0xE4_xB5 Register Definition **** |
| 9854 | // Address |
| 9855 | #define DxF0xE4_xB5_ADDRESS 0xb5 |
| 9856 | |
| 9857 | // Type |
| 9858 | #define DxF0xE4_xB5_TYPE TYPE_D4F0xE4 |
| 9859 | // Field Data |
| 9860 | #define DxF0xE4_xB5_LcSelectDeemphasis_OFFSET 0 |
| 9861 | #define DxF0xE4_xB5_LcSelectDeemphasis_WIDTH 1 |
| 9862 | #define DxF0xE4_xB5_LcSelectDeemphasis_MASK 0x1 |
| 9863 | #define DxF0xE4_xB5_LcSelectDeemphasisCntl_OFFSET 1 |
| 9864 | #define DxF0xE4_xB5_LcSelectDeemphasisCntl_WIDTH 2 |
| 9865 | #define DxF0xE4_xB5_LcSelectDeemphasisCntl_MASK 0x6 |
| 9866 | #define DxF0xE4_xB5_LcRcvdDeemphasis_OFFSET 3 |
| 9867 | #define DxF0xE4_xB5_LcRcvdDeemphasis_WIDTH 1 |
| 9868 | #define DxF0xE4_xB5_LcRcvdDeemphasis_MASK 0x8 |
| 9869 | #define DxF0xE4_xB5_Reserved_31_23_OFFSET 23 |
| 9870 | #define DxF0xE4_xB5_Reserved_31_23_WIDTH 9 |
| 9871 | #define DxF0xE4_xB5_Reserved_31_23_MASK 0xff800000 |
| 9872 | |
| 9873 | /// DxF0xE4_xB5 |
| 9874 | typedef union { |
| 9875 | struct { ///< |
| 9876 | UINT32 LcSelectDeemphasis:1 ; ///< |
| 9877 | UINT32 LcSelectDeemphasisCntl:2 ; ///< |
| 9878 | UINT32 LcRcvdDeemphasis:1 ; ///< |
| 9879 | UINT32 :1 ; ///< |
| 9880 | UINT32 :1 ; ///< |
| 9881 | UINT32 :2 ; ///< |
| 9882 | UINT32 :1 ; ///< |
| 9883 | UINT32 :1 ; ///< |
| 9884 | UINT32 line519:1 ; ///< |
| 9885 | UINT32 :1 ; ///< |
| 9886 | UINT32 line521:2 ; ///< |
| 9887 | UINT32 line522:2 ; ///< |
| 9888 | UINT32 :1 ; ///< |
| 9889 | UINT32 :1 ; ///< |
| 9890 | UINT32 :1 ; ///< |
| 9891 | UINT32 :2 ; ///< |
| 9892 | UINT32 :1 ; ///< |
| 9893 | UINT32 :1 ; ///< |
| 9894 | UINT32 Reserved_31_23:9 ; ///< |
| 9895 | } Field; ///< |
| 9896 | UINT32 Value; ///< |
| 9897 | } DxF0xE4_xB5_STRUCT; |
| 9898 | |
| 9899 | |
| 9900 | // **** D0F0xE4_PHY_6006 Register Definition **** |
| 9901 | // Address |
| 9902 | #define D0F0xE4_PHY_6006_ADDRESS 0x6006 |
| 9903 | |
| 9904 | // Type |
| 9905 | #define D0F0xE4_PHY_6006_TYPE TYPE_D0F0xE4 |
| 9906 | // Field Data |
| 9907 | #define D0F0xE4_PHY_6006_TxMarginNom_OFFSET 0 |
| 9908 | #define D0F0xE4_PHY_6006_TxMarginNom_WIDTH 8 |
| 9909 | #define D0F0xE4_PHY_6006_TxMarginNom_MASK 0xff |
| 9910 | #define D0F0xE4_PHY_6006_DeemphGen1Nom_OFFSET 8 |
| 9911 | #define D0F0xE4_PHY_6006_DeemphGen1Nom_WIDTH 8 |
| 9912 | #define D0F0xE4_PHY_6006_DeemphGen1Nom_MASK 0xff00 |
| 9913 | #define D0F0xE4_PHY_6006_Deemph35Gen2Nom_OFFSET 16 |
| 9914 | #define D0F0xE4_PHY_6006_Deemph35Gen2Nom_WIDTH 8 |
| 9915 | #define D0F0xE4_PHY_6006_Deemph35Gen2Nom_MASK 0xff0000 |
| 9916 | #define D0F0xE4_PHY_6006_Deemph60Gen2Nom_OFFSET 24 |
| 9917 | #define D0F0xE4_PHY_6006_Deemph60Gen2Nom_WIDTH 8 |
| 9918 | #define D0F0xE4_PHY_6006_Deemph60Gen2Nom_MASK 0xff000000 |
| 9919 | |
| 9920 | /// D0F0xE4_PHY_6006 |
| 9921 | typedef union { |
| 9922 | struct { ///< |
| 9923 | UINT32 TxMarginNom:8 ; ///< |
| 9924 | UINT32 DeemphGen1Nom:8 ; ///< |
| 9925 | UINT32 Deemph35Gen2Nom:8 ; ///< |
| 9926 | UINT32 Deemph60Gen2Nom:8 ; ///< |
| 9927 | } Field; ///< |
| 9928 | UINT32 Value; ///< |
| 9929 | } D0F0xE4_PHY_6006_STRUCT; |
| 9930 | |
| 9931 | |
| 9932 | |
| 9933 | // **** D0F0x64_x1C Register Definition **** |
| 9934 | // Address |
| 9935 | #define D0F0x64_x1C_ADDRESS 0x1c |
| 9936 | |
| 9937 | // Type |
| 9938 | #define D0F0x64_x1C_TYPE TYPE_D0F0x64 |
| 9939 | // Field Data |
| 9940 | #define D0F0x64_x1C_WriteDis_OFFSET 0 |
| 9941 | #define D0F0x64_x1C_WriteDis_WIDTH 1 |
| 9942 | #define D0F0x64_x1C_WriteDis_MASK 0x1 |
| 9943 | #define D0F0x64_x1C_F0NonlegacyDeviceTypeEn_OFFSET 1 |
| 9944 | #define D0F0x64_x1C_F0NonlegacyDeviceTypeEn_WIDTH 1 |
| 9945 | #define D0F0x64_x1C_F0NonlegacyDeviceTypeEn_MASK 0x2 |
| 9946 | #define D0F0x64_x1C_F064BarEn_OFFSET 2 |
| 9947 | #define D0F0x64_x1C_F064BarEn_WIDTH 1 |
| 9948 | #define D0F0x64_x1C_F064BarEn_MASK 0x4 |
| 9949 | #define D0F0x64_x1C_MemApSize_OFFSET 3 |
| 9950 | #define D0F0x64_x1C_MemApSize_WIDTH 3 |
| 9951 | #define D0F0x64_x1C_MemApSize_MASK 0x38 |
| 9952 | #define D0F0x64_x1C_RegApSize_OFFSET 6 |
| 9953 | #define D0F0x64_x1C_RegApSize_WIDTH 1 |
| 9954 | #define D0F0x64_x1C_RegApSize_MASK 0x40 |
| 9955 | |
| 9956 | /// D0F0x64_x1C |
| 9957 | typedef union { |
| 9958 | struct { ///< |
| 9959 | UINT32 WriteDis:1 ; ///< |
| 9960 | UINT32 F0NonlegacyDeviceTypeEn:1 ; ///< |
| 9961 | UINT32 F064BarEn:1 ; ///< |
| 9962 | UINT32 MemApSize:3 ; ///< |
| 9963 | UINT32 RegApSize:1 ; ///< |
| 9964 | UINT32 /* DualfuncDisplayEn*/:1 ; ///< |
| 9965 | UINT32 /* AudioEn*/:1 ; ///< |
| 9966 | UINT32 /* MsiDis*/:1 ; ///< |
| 9967 | UINT32 /* AudioNonlegacyDeviceTypeEn*/:1 ; ///< |
| 9968 | UINT32 /* Audio64BarEn*/:1 ; ///< |
| 9969 | UINT32 /* VgaDis*/:1 ; ///< |
| 9970 | UINT32 /* FbAlwaysOn*/:1 ; ///< |
| 9971 | UINT32 /* FbCplTypeSel*/:2 ; ///< |
| 9972 | UINT32 /* IoBarDis*/:1 ; ///< |
| 9973 | UINT32 /* F0En*/:1 ; ///< |
| 9974 | UINT32 /* F0BarEn*/:1 ; ///< |
| 9975 | UINT32 /* F1BarEn*/:1 ; ///< |
| 9976 | UINT32 /* F2BarEn*/:1 ; ///< |
| 9977 | UINT32 /* PcieDis*/:1 ; ///< |
| 9978 | UINT32 /* BifBxcntlSpare0*/:1 ; ///< |
| 9979 | UINT32 /* RcieEn*/:1 ; ///< |
| 9980 | UINT32 /* BifBxcntlSpare*/:8 ; ///< |
| 9981 | } Field; ///< |
| 9982 | UINT32 Value; ///< |
| 9983 | } D0F0x64_x1C_STRUCT; |
| 9984 | |
| 9985 | // **** GMMx00 Register Definition **** |
| 9986 | // Address |
| 9987 | #define GMMx00_ADDRESS 0x0 |
| 9988 | |
| 9989 | // Type |
| 9990 | #define GMMx00_TYPE TYPE_GMM |
| 9991 | // Field Data |
| 9992 | #define GMMx00_Offset_OFFSET 0 |
| 9993 | #define GMMx00_Offset_WIDTH 31 |
| 9994 | #define GMMx00_Offset_MASK 0x7fffffff |
| 9995 | #define GMMx00_Aper_OFFSET 31 |
| 9996 | #define GMMx00_Aper_WIDTH 1 |
| 9997 | #define GMMx00_Aper_MASK 0x80000000 |
| 9998 | |
| 9999 | /// GMMx00 |
| 10000 | typedef union { |
| 10001 | struct { ///< |
| 10002 | UINT32 Offset:31; ///< |
| 10003 | UINT32 Aper:1 ; ///< |
| 10004 | } Field; ///< |
| 10005 | UINT32 Value; ///< |
| 10006 | } GMMx00_STRUCT; |
| 10007 | |
| 10008 | // **** GMMx04 Register Definition **** |
| 10009 | // Address |
| 10010 | #define GMMx04_ADDRESS 0x4 |
| 10011 | |
| 10012 | // Type |
| 10013 | #define GMMx04_TYPE TYPE_GMM |
| 10014 | // Field Data |
| 10015 | #define GMMx04_Data_OFFSET 0 |
| 10016 | #define GMMx04_Data_WIDTH 32 |
| 10017 | #define GMMx04_Data_MASK 0xffffffff |
| 10018 | |
| 10019 | /// GMMx04 |
| 10020 | typedef union { |
| 10021 | struct { ///< |
| 10022 | UINT32 Data:32; ///< |
| 10023 | } Field; ///< |
| 10024 | UINT32 Value; ///< |
| 10025 | } GMMx04_STRUCT; |
| 10026 | |
| 10027 | |
| 10028 | |
| 10029 | // **** D18F2x09C_x0D0FE00A Register Definition **** |
| 10030 | // Address |
| 10031 | #define D18F2x09C_x0D0FE00A_ADDRESS 0x0D0FE00A |
| 10032 | |
| 10033 | // Type |
| 10034 | #define D18F2x09C_x0D0FE00A_TYPE TYPE_D18F2x9C |
| 10035 | // Field Data |
| 10036 | #define D18F2x09C_x0D0FE00A_Reserved_3_0_OFFSET 0 |
| 10037 | #define D18F2x09C_x0D0FE00A_Reserved_3_0_WIDTH 4 |
| 10038 | #define D18F2x09C_x0D0FE00A_Reserved_3_0_MASK 0xF |
| 10039 | #define D18F2x09C_x0D0FE00A_SkewMemClk_OFFSET 4 |
| 10040 | #define D18F2x09C_x0D0FE00A_SkewMemClk_WIDTH 1 |
| 10041 | #define D18F2x09C_x0D0FE00A_SkewMemClk_MASK 0x10 |
| 10042 | #define D18F2x09C_x0D0FE00A_Reserved_11_5_OFFSET 5 |
| 10043 | #define D18F2x09C_x0D0FE00A_Reserved_11_5_WIDTH 7 |
| 10044 | #define D18F2x09C_x0D0FE00A_Reserved_11_5_MASK 0xFE0 |
| 10045 | #define D18F2x09C_x0D0FE00A_Reserved_31_15_OFFSET 15 |
| 10046 | #define D18F2x09C_x0D0FE00A_Reserved_31_15_WIDTH 17 |
| 10047 | #define D18F2x09C_x0D0FE00A_Reserved_31_15_MASK 0xFFFF8000 |
| 10048 | |
| 10049 | /// D18F2x09C_x0D0FE00A |
| 10050 | typedef union { |
| 10051 | struct { ///< |
| 10052 | UINT32 Reserved_3_0:4; ///< |
| 10053 | UINT32 SkewMemClk:1; ///< |
| 10054 | UINT32 Reserved_11_5:7; ///< |
| 10055 | UINT32 :2; ///< |
| 10056 | UINT32 :1; ///< |
| 10057 | UINT32 Reserved_31_15:17; ///< |
| 10058 | } Field; ///< |
| 10059 | UINT32 Value; ///< |
| 10060 | } D18F2x09C_x0D0FE00A_STRUCT; |
| 10061 | |
| 10062 | /// D0F0xE4_WRAP_8016 |
| 10063 | typedef union { |
| 10064 | struct { ///< |
| 10065 | UINT32 CalibAckLatency:6 ; ///< |
| 10066 | UINT32 Reserved_7_6:2 ; ///< |
| 10067 | UINT32 CalibDoneSelPifA:1 ; ///< |
| 10068 | UINT32 Reserved_9_9:1 ; ///< |
| 10069 | UINT32 Reserved_10_10:1 ; ///< |
| 10070 | UINT32 Reserved_11_11:1 ; ///< |
| 10071 | UINT32 Gen1OnlyEngage:1 ; ///< |
| 10072 | UINT32 Gen1OnlyEngaged:1 ; ///< |
| 10073 | UINT32 Reserved_15_14:2 ; ///< |
| 10074 | UINT32 LclkDynGateLatency:6 ; ///< |
| 10075 | UINT32 LclkGateFree:1 ; ///< |
| 10076 | UINT32 LclkDynGateEnable:1 ; ///< |
| 10077 | UINT32 Reserved_31_24:8 ; ///< |
| 10078 | } Field; ///< |
| 10079 | UINT32 Value; ///< |
| 10080 | } ex688_STRUCT; |
| 10081 | |
| 10082 | |
| 10083 | |
| 10084 | #endif |