zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * Initialize GFX configuration data structure. |
| 6 | * |
| 7 | * |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: GNB |
| 12 | * @e \$Revision: 64730 $ @e \$Date: 2012-01-30 02:05:39 -0600 (Mon, 30 Jan 2012) $ |
| 13 | * |
| 14 | */ |
| 15 | /* |
| 16 | ***************************************************************************** |
| 17 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 18 | * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. |
| 19 | * All rights reserved. |
| 20 | * |
| 21 | * Redistribution and use in source and binary forms, with or without |
| 22 | * modification, are permitted provided that the following conditions are met: |
| 23 | * * Redistributions of source code must retain the above copyright |
| 24 | * notice, this list of conditions and the following disclaimer. |
| 25 | * * Redistributions in binary form must reproduce the above copyright |
| 26 | * notice, this list of conditions and the following disclaimer in the |
| 27 | * documentation and/or other materials provided with the distribution. |
| 28 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 29 | * its contributors may be used to endorse or promote products derived |
| 30 | * from this software without specific prior written permission. |
| 31 | * |
| 32 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 33 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 34 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 35 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 36 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 37 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 38 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 39 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 40 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 41 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 42 | * *************************************************************************** |
| 43 | * |
| 44 | */ |
| 45 | |
| 46 | #ifndef _GNBGFX_H_ |
| 47 | #define _GNBGFX_H_ |
| 48 | |
| 49 | //#ifndef PVOID |
| 50 | // typedef UINT64 PVOID; |
| 51 | //#endif |
| 52 | |
| 53 | #define DEVICE_DFP 0x1 |
| 54 | #define DEVICE_CRT 0x2 |
| 55 | #define DEVICE_LCD 0x3 |
| 56 | |
| 57 | |
| 58 | #define CONNECTOR_DISPLAYPORT_ENUM 0x3013 |
| 59 | #define CONNECTOR_HDMI_TYPE_A_ENUM 0x300c |
| 60 | #define CONNECTOR_SINGLE_LINK_DVI_D_ENUM 0x3003 |
| 61 | #define CONNECTOR_DUAL_LINK_DVI_D_ENUM 0x3004 |
| 62 | #define CONNECTOR_SINGLE_LINK_DVI_I_ENUM 0x3001 |
| 63 | #define CONNECTOR_DUAL_LINK_DVI_I_ENUM 0x3002 |
| 64 | #define CONNECTOR_VGA_ENUM 0x3005 |
| 65 | #define CONNECTOR_LVDS_ENUM 0x300E |
| 66 | #define CONNECTOR_eDP_ENUM 0x3014 |
| 67 | #define CONNECTOR_LVDS_eDP_ENUM 0x3016 |
| 68 | #define ENCODER_TRAVIS_ENUM_ID1 0x2123 |
| 69 | #define ENCODER_TRAVIS_ENUM_ID2 0x2223 |
| 70 | #define ENCODER_ALMOND_ENUM_ID1 0x2122 |
| 71 | #define ENCODER_NOT_PRESENT 0x0000 |
| 72 | |
| 73 | // no eDP->LVDS translator chip |
| 74 | #define eDP_TO_LVDS_RX_DISABLE 0x00 |
| 75 | // common eDP->LVDS translator chip without AMD SW init |
| 76 | #define eDP_TO_LVDS_COMMON_ID 0x01 |
| 77 | // Realtek tansaltor which require AMD SW init |
| 78 | #define eDP_TO_LVDS_REALTEK_ID 0x02 |
| 79 | |
| 80 | |
| 81 | #define ATOM_DEVICE_CRT1_SUPPORT 0x0001 |
| 82 | #define ATOM_DEVICE_DFP1_SUPPORT 0x0008 |
| 83 | #define ATOM_DEVICE_DFP6_SUPPORT 0x0040 |
| 84 | #define ATOM_DEVICE_DFP2_SUPPORT 0x0080 |
| 85 | #define ATOM_DEVICE_DFP3_SUPPORT 0x0200 |
| 86 | #define ATOM_DEVICE_DFP4_SUPPORT 0x0400 |
| 87 | #define ATOM_DEVICE_DFP5_SUPPORT 0x0800 |
| 88 | #define ATOM_DEVICE_LCD1_SUPPORT 0x0002 |
| 89 | |
| 90 | /// Graphics card information structure |
| 91 | typedef struct { |
| 92 | UINT32 AmdPcieGfxCardBitmap; ///< AMD PCIE graphics card information |
| 93 | UINT32 PcieGfxCardBitmap; ///< All PCIE graphics card information |
| 94 | UINT32 PciGfxCardBitmap; ///< All PCI graphics card information |
| 95 | } GFX_CARD_CARD_INFO; |
| 96 | |
| 97 | typedef enum { |
| 98 | iGpuVgaAdapter, ///< Configure iGPU as VGA adapter |
| 99 | iGpuVgaNonAdapter ///< Configure iGPU as non VGA adapter |
| 100 | } GFX_IGPU_VGA_MODE; |
| 101 | |
| 102 | typedef enum { |
| 103 | excel992, |
| 104 | excel993 |
| 105 | } UMA_STEERING; |
| 106 | |
| 107 | /// User Options |
| 108 | typedef enum { |
| 109 | OptionDisabled, ///< Disabled |
| 110 | OptionEnabled ///< Enabled |
| 111 | } CONTROL_OPTION; |
| 112 | |
| 113 | /// GFX enable Policy |
| 114 | typedef enum { |
| 115 | GmcPowerGatingDisabled, ///< Disable Power gating |
| 116 | GmcPowerGatingStutterOnly, ///< GMC Stutter Only mode |
| 117 | GmcPowerGatingWidthStutter ///< GMC Power gating with Stutter mode |
| 118 | } GMC_POWER_GATING; |
| 119 | |
| 120 | /// Internal GFX mode |
| 121 | typedef enum { |
| 122 | GfxControllerLegacyBridgeMode, ///< APC bridge Legacy mode |
| 123 | GfxControllerPcieEndpointMode, ///< IGFX PCIE Bus 0, Device 1 |
| 124 | } GFX_CONTROLLER_MODE; |
| 125 | |
| 126 | /// Graphics Platform Configuration |
| 127 | typedef struct { |
Stefan Reinauer | d91ddc8 | 2015-07-30 11:17:40 -0700 | [diff] [blame] | 128 | UINTN StdHeader; ///< Standard Header TODO: Used to be PVOID |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 129 | PCI_ADDR GfxPciAddress; ///< Graphics PCI Address |
| 130 | UMA_INFO UmaInfo; ///< UMA Information |
| 131 | UINT32 GmmBase; ///< GMM Base |
| 132 | UINT8 GnbHdAudio; ///< Control GFX HD Audio controller(Used for HDMI and DP display output), |
| 133 | ///< essentially it enables function 1 of graphics device. |
| 134 | ///< @li 0 = HD Audio disable |
| 135 | ///< @li 1 = HD Audio enable |
| 136 | UINT8 AbmSupport; ///< Automatic adjust LVDS/eDP Back light level support.It is |
| 137 | ///< characteristic specific to display panel which used by platform design. |
| 138 | ///< @li 0 = ABM support disabled |
| 139 | ///< @li 1 = ABM support enabled |
| 140 | UINT8 DynamicRefreshRate; ///< Adjust refresh rate on LVDS/eDP. |
| 141 | UINT16 LcdBackLightControl; ///< The PWM frequency to LCD backlight control. |
| 142 | ///< If equal to 0 backlight not controlled by iGPU. |
| 143 | UINT32 AmdPlatformType; ///< Platform type |
| 144 | UMA_STEERING UmaSteering; ///< UMA Steering |
| 145 | GFX_IGPU_VGA_MODE iGpuVgaMode; ///< iGPU VGA mode |
| 146 | BOOLEAN GmcClockGating; ///< Clock gating |
| 147 | BOOLEAN GmcLockRegisters; ///< GmcLock Registers |
| 148 | BOOLEAN GfxFusedOff; ///< Record if GFX is fused off. |
| 149 | GMC_POWER_GATING GmcPowerGating; ///< Gmc Power Gating. |
| 150 | UINT8 Gnb3dStereoPinIndex; ///< 3D Stereo Pin ID |
| 151 | GFX_CONTROLLER_MODE GfxControllerMode; ///< Gfx controller mode |
| 152 | UINT16 LvdsSpreadSpectrum; ///< Spread spectrum value in 0.01 % |
| 153 | UINT16 LvdsSpreadSpectrumRate; ///< Spread spectrum frequency used by SS hardware logic in unit of 10Hz, 0 - default frequency 40kHz |
| 154 | UINT8 LvdsPowerOnSeqDigonToDe; ///< Panel initialization timing. |
| 155 | UINT8 LvdsPowerOnSeqDeToVaryBl; ///< Panel initialization timing. |
| 156 | UINT8 LvdsPowerOnSeqDeToDigon; ///< Panel initialization timing. |
| 157 | UINT8 LvdsPowerOnSeqVaryBlToDe; ///< Panel initialization timing. |
| 158 | UINT8 LvdsPowerOnSeqOnToOffDelay; ///< Panel initialization timing. |
| 159 | UINT8 LvdsPowerOnSeqVaryBlToBlon; ///< Panel initialization timing. |
| 160 | UINT8 LvdsPowerOnSeqBlonToVaryBl; ///< Panel initialization timing. |
| 161 | UINT16 LvdsMaxPixelClockFreq; ///< The maximum pixel clock frequency supported. |
| 162 | UINT32 LcdBitDepthControlValue; ///< The LCD bit depth control settings. |
| 163 | UINT8 Lvds24bbpPanelMode; ///< The LVDS 24 BBP mode. |
| 164 | LVDS_MISC_CONTROL LvdsMiscControl; ///< THe LVDS swap/Hsync/Vsync/BLON/Volt-overwrite control |
| 165 | GFX_CARD_CARD_INFO GfxDiscreteCardInfo; ///< Discrete GFX card info |
| 166 | UINT16 PcieRefClkSpreadSpectrum; ///< Spread spectrum value in 0.01 % |
| 167 | BOOLEAN GnbRemoteDisplaySupport; ///< Wireless Display Enable |
| 168 | UINT8 gfxplmcfg0 ; |
| 169 | DISPLAY_MISC_CONTROL DisplayMiscControl; ///< The Display misc control |
| 170 | } GFX_PLATFORM_CONFIG; |
| 171 | |
| 172 | |
| 173 | typedef UINT32 ULONG; |
| 174 | typedef UINT16 USHORT; |
| 175 | typedef UINT8 UCHAR; |
| 176 | |
| 177 | /// Driver interface header structure |
| 178 | typedef struct _ATOM_COMMON_TABLE_HEADER { |
| 179 | USHORT usStructureSize; ///< Structure size |
| 180 | UCHAR ucTableFormatRevision; ///< Format revision number |
| 181 | UCHAR ucTableContentRevision; ///< Contents revision number |
| 182 | } ATOM_COMMON_TABLE_HEADER; |
| 183 | |
| 184 | /// Link ping mapping for DP/eDP/LVDS |
| 185 | typedef struct _ATOM_DP_CONN_CHANNEL_MAPPING { |
| 186 | UCHAR ucDP_Lane0_Source :2; ///< Define which pin connect to DP connector DP_Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 |
| 187 | UCHAR ucDP_Lane1_Source :2; ///< Define which pin connect to DP connector DP_Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 |
| 188 | UCHAR ucDP_Lane2_Source :2; ///< Define which pin connect to DP connector DP_Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 |
| 189 | UCHAR ucDP_Lane3_Source :2; ///< Define which pin connect to DP connector DP_Lane3, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 |
| 190 | } ATOM_DP_CONN_CHANNEL_MAPPING; |
| 191 | |
| 192 | /// Link ping mapping for DVI/HDMI |
| 193 | typedef struct _ATOM_DVI_CONN_CHANNEL_MAPPING { |
| 194 | UCHAR ucDVI_DATA2_Source :2; ///< Define which pin connect to DVI connector data Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 |
| 195 | UCHAR ucDVI_DATA1_Source :2; ///< Define which pin connect to DVI connector data Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 |
| 196 | UCHAR ucDVI_DATA0_Source :2; ///< Define which pin connect to DVI connector data Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 |
| 197 | UCHAR ucDVI_CLK_Source :2; ///< Define which pin connect to DVI connector clock lane, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 |
| 198 | } ATOM_DVI_CONN_CHANNEL_MAPPING; |
| 199 | |
| 200 | |
| 201 | /// External Display Path |
| 202 | typedef struct _EXT_DISPLAY_PATH { |
| 203 | USHORT usDeviceTag; ///< A bit vector to show what devices are supported |
| 204 | USHORT usDeviceACPIEnum; ///< 16bit device ACPI id. |
| 205 | USHORT usDeviceConnector; ///< A physical connector for displays to plug in, using object connector definitions |
| 206 | UCHAR ucExtAUXDDCLutIndex; ///< An index into external AUX/DDC channel LUT |
| 207 | UCHAR ucExtHPDPINLutIndex; ///< An index into external HPD pin LUT |
| 208 | USHORT usExtEncoderObjId; ///< external encoder object id |
| 209 | union { ///< Lane mapping |
| 210 | UCHAR ucChannelMapping; ///< lane mapping on connector (ucChannelMapping=0 use default) |
| 211 | ATOM_DP_CONN_CHANNEL_MAPPING asDPMapping; ///< lane mapping on connector (ucChannelMapping=0 use default) |
| 212 | ATOM_DVI_CONN_CHANNEL_MAPPING asDVIMapping; ///< lane mapping on connector (ucChannelMapping=0 use default) |
| 213 | } ChannelMapping; |
| 214 | UCHAR ucChPNInvert; ///< Bit vector for up to 8 lanes. 0: P and N is not invert, 1: P and N is inverted |
| 215 | USHORT usCaps; ///< Capabilities IF BIT[0] == 1, downgrade phy link to DP1.1 |
| 216 | USHORT usReserved; ///< Reserved |
| 217 | } EXT_DISPLAY_PATH; |
| 218 | |
| 219 | /// External Display Connection Information |
| 220 | typedef struct _ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO { |
| 221 | ATOM_COMMON_TABLE_HEADER sHeader; ///< Standard Header |
| 222 | UCHAR ucGuid [16]; ///< Guid |
| 223 | EXT_DISPLAY_PATH sPath[7]; ///< External Display Path |
| 224 | UCHAR ucChecksum; ///< Checksum |
| 225 | UCHAR uc3DStereoPinId; ///< 3D Stereo Pin ID |
| 226 | UCHAR ucRemoteDisplayConfig; ///< Bit0=1:Enable Wireless Display through APU VCE HW function |
| 227 | UCHAR uceDPToLVDSRxId; ///< 3rd party eDP to LVDS translator chip presented. 0:no, 1:chip without AMD SW init, 2:Realtek tansaltor which require AMD SW init |
| 228 | UCHAR Reserved [4]; ///< Reserved |
| 229 | } ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO; |
| 230 | |
| 231 | /// Displclk to VID relation table |
| 232 | typedef struct _ATOM_CLK_VOLT_CAPABILITY { |
| 233 | ULONG ulVoltageIndex; ///< The Voltage Index indicated by FUSE, same voltage index shared with SCLK DPM fuse table |
| 234 | ULONG ulMaximumSupportedCLK;///< Maximum clock supported with specified voltage index, unit in 10kHz |
| 235 | } ATOM_CLK_VOLT_CAPABILITY; |
| 236 | |
| 237 | /// Available Sclk table |
| 238 | typedef struct _ATOM_AVAILABLE_SCLK_LIST { |
| 239 | ULONG ulSupportedSCLK; ///< Maximum clock supported with specified voltage index, unit in 10kHz |
| 240 | USHORT usVoltageIndex; ///< The Voltage Index indicated by FUSE for specified SCLK |
| 241 | USHORT usVoltageID; ///< The Voltage ID indicated by FUSE for specified SCLK |
| 242 | } ATOM_AVAILABLE_SCLK_LIST; |
| 243 | |
| 244 | /// Integrate System Info Table is used for Llano/Ontario APU |
| 245 | typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 { |
| 246 | ATOM_COMMON_TABLE_HEADER sHeader; ///< Standard Header |
| 247 | ULONG ulBootUpEngineClock; ///< VBIOS bootup Engine clock frequency, in 10kHz unit. |
| 248 | ULONG excel994; |
| 249 | ULONG ulBootUpUMAClock; ///< System memory boot up clock frequency in 10Khz unit. |
| 250 | ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4]; ///< Report Display clock voltage requirement. |
| 251 | ULONG ulBootUpReqDisplayVector; /**< VBIOS boot up display IDs, following are supported devices in Llano/Fam 12 and Ontario/Fam 14 projects: |
| 252 | * ATOM_DEVICE_CRT1_SUPPORT 0x0001 |
| 253 | * ATOM_DEVICE_CRT2_SUPPORT 0x0010 |
| 254 | * ATOM_DEVICE_DFP1_SUPPORT 0x0008 |
| 255 | * ATOM_DEVICE_DFP6_SUPPORT 0x0040 |
| 256 | * ATOM_DEVICE_DFP2_SUPPORT 0x0080 |
| 257 | * ATOM_DEVICE_DFP3_SUPPORT 0x0200 |
| 258 | * ATOM_DEVICE_DFP4_SUPPORT 0x0400 |
| 259 | * ATOM_DEVICE_DFP5_SUPPORT 0x0800 |
| 260 | * ATOM_DEVICE_LCD1_SUPPORT 0x0002 |
| 261 | */ |
| 262 | ULONG ulOtherDisplayMisc; ///< Other display related flags, not defined yet. |
| 263 | ULONG ulGPUCapInfo; /**> @li BIT[0] - TMDS/HDMI Coherent Mode 0: use cascade PLL mode, 1: use signel PLL mode. |
| 264 | * @li BIT[1] - DP mode 0: use cascade PLL mode, 1: use single PLL mode |
| 265 | * @li BIT[3] - AUX HW mode detection logic 0: Enable, 1: Disable |
| 266 | */ |
| 267 | ULONG ulSB_MMIO_Base_Addr; ///< Physical Base address to SB MMIO space. Driver need to initialize it for SMU usage. |
| 268 | USHORT usRequestedPWMFreqInHz; ///< Panel Required PWM frequency. if this parameter is 0 PWM from to control LCD Backlight will be disabled. |
| 269 | UCHAR ucHtcTmpLmt; ///< HTC temperature limit.The processor enters HTC-active state when Tctl reaches or exceeds HtcHystLmt. |
| 270 | UCHAR ucHtcHystLmt; ///< HTC hysteresis.The processor exits HTC-active state when Tctl is less than HtcTmpLmt minus HtcHystLmt. |
| 271 | ULONG ulMinEngineClock; ///< Min SCLK |
| 272 | ULONG ulSystemConfig; /**< System configuration |
| 273 | * @li BIT[0] - 0: PCIE Power Gating Disabled, 1: PCIE Power Gating Enabled. |
| 274 | * @li BIT[1] - 0: DDR-DLL shut-down feature disabled, 1: DDR-DLL shut-down feature enabled. |
| 275 | * @li BIT[2] - 0: DDR-PLL Power down feature disabled, 1: DDR-PLL Power down feature enabled. |
| 276 | */ |
| 277 | ULONG ulCPUCapInfo; ///< TBD |
| 278 | USHORT usNBP0Voltage; ///< VID for voltage on NB P0 State |
| 279 | USHORT usNBP1Voltage; ///< VID for voltage on NB P1 State |
| 280 | USHORT usBootUpNBVoltage; ///< Voltage Index of GNB voltage configured by SBIOS, which is sufficient to support VBIOS DISPCLK requirement. |
| 281 | USHORT usExtDispConnInfoOffset; ///< Offset to sExtDispConnInfo inside the structure |
| 282 | USHORT usPanelRefreshRateRange; /**< Bit vector for LVDS/eDP supported refresh rate range. If DRR is enabled, 2 of the bits must be set. |
| 283 | * SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 |
| 284 | * SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 |
| 285 | * SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 |
| 286 | * SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 |
| 287 | */ |
| 288 | UCHAR ucMemoryType; ///< Memory type (3 for DDR3) |
| 289 | UCHAR ucUMAChannelNumber; ///< System memory channel numbers. |
| 290 | ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10]; ///< Arrays with values for CSR M3 arbiter for default. |
| 291 | ULONG ulCSR_M3_ARB_CNTL_UVD[10]; ///< Arrays with values for CSR M3 arbiter for UVD playback. |
| 292 | ULONG ulCSR_M3_ARB_CNTL_FS3D[10]; ///< Arrays with values for CSR M3 arbiter for Full Screen 3D applications. |
| 293 | ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5]; ///< Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high |
| 294 | ULONG ulGMCRestoreResetTime; ///< GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. |
| 295 | ULONG ulMinimumNClk; ///< Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz. |
| 296 | ULONG ulIdleNClk; ///< NCLK speed while memory runs in self-refresh state. Unit in 10kHz. |
| 297 | ULONG ulDDR_DLL_PowerUpTime; ///< DDR PHY DLL power up time. Unit in ns. |
| 298 | ULONG ulDDR_PLL_PowerUpTime; ///< DDR PHY PLL power up time. Unit in ns |
| 299 | USHORT usPCIEClkSSPercentage; ///< usPCIEClkSSPercentage |
| 300 | USHORT usPCIEClkSSType; ///< usPCIEClkSSType |
| 301 | USHORT usLvdsSSPercentage; ///< usLvdsSSPercentage |
| 302 | USHORT usLvdsSSpreadRateIn10Hz; ///< usLvdsSSpreadRateIn10Hz |
| 303 | USHORT usHDMISSPercentage; ///< usHDMISSPercentage |
| 304 | USHORT usHDMISSpreadRateIn10Hz; ///< usHDMISSpreadRateIn10Hz |
| 305 | USHORT usDVISSPercentage; ///< usDVISSPercentage |
| 306 | USHORT usDVISSpreadRateIn10Hz; ///< usDVISSpreadRateIn10Hz |
| 307 | ULONG SclkDpmBoostMargin; ///< SclkDpmBoostMargin |
| 308 | ULONG SclkDpmThrottleMargin; ///< SclkDpmThrottleMargin |
| 309 | USHORT SclkDpmTdpLimitPG; ///< SclkDpmTdpLimitPG |
| 310 | USHORT SclkDpmTdpLimitBoost; ///< SclkDpmTdpLimitBoost |
| 311 | ULONG ulBoostEngineCLock; ///< ulBoostEngineCLock |
| 312 | UCHAR ulBoostVid_2bit; ///< ulBoostVid_2bit |
| 313 | UCHAR EnableBoost; ///< EnableBoost |
| 314 | USHORT GnbTdpLimit; ///< GnbTdpLimit |
| 315 | USHORT usMaxLVDSPclkFreqInSingleLink; ///< usMaxLVDSPclkFreqInSingleLink |
| 316 | UCHAR ucLvdsMisc; ///< ucLvdsMisc |
| 317 | UCHAR ucLVDSReserved; ///< ucLVDSReserved |
| 318 | ULONG ulReserved3[15]; ///< Reserved |
| 319 | ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; ///< Display connector definition |
| 320 | } ATOM_INTEGRATED_SYSTEM_INFO_V6; |
| 321 | |
| 322 | /// this Table is used for Llano/Ontario APU |
| 323 | typedef struct _ATOM_FUSION_SYSTEM_INFO_V1 { |
| 324 | ATOM_INTEGRATED_SYSTEM_INFO_V6 sIntegratedSysInfo; ///< Refer to ATOM_INTEGRATED_SYSTEM_INFO_V6 definition. |
| 325 | ULONG ulPowerplayTable[128]; ///< This 512 bytes memory is used to save ATOM_PPLIB_POWERPLAYTABLE3, starting form ulPowerplayTable[0] |
| 326 | } ATOM_FUSION_SYSTEM_INFO_V1; |
| 327 | |
| 328 | /// Integrated Info table |
| 329 | /// Upgrade is followed by Trinity SBIOS/VBIOS & Driver interface Design Document VER 0.5 |
| 330 | typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 { |
| 331 | ATOM_COMMON_TABLE_HEADER sHeader; ///< Standard Header |
| 332 | ULONG ulBootUpEngineClock; ///< VBIOS bootup Engine clock frequency, in 10kHz unit. |
| 333 | ULONG ulDentistVCOFreq; ///< Dentist VCO clock in 10kHz unit. |
| 334 | ULONG ulBootUpUMAClock; ///< System memory boot up clock frequency in 10Khz unit. |
| 335 | ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4]; ///< Report Display clock voltage requirement. |
| 336 | ULONG ulBootUpReqDisplayVector; /**< VBIOS boot up display IDs, following are supported devices in Llano/Fam 12 and Ontario/Fam 14 projects: |
| 337 | * ATOM_DEVICE_CRT1_SUPPORT 0x0001 |
| 338 | * ATOM_DEVICE_CRT2_SUPPORT 0x0010 |
| 339 | * ATOM_DEVICE_DFP1_SUPPORT 0x0008 |
| 340 | * ATOM_DEVICE_DFP6_SUPPORT 0x0040 |
| 341 | * ATOM_DEVICE_DFP2_SUPPORT 0x0080 |
| 342 | * ATOM_DEVICE_DFP3_SUPPORT 0x0200 |
| 343 | * ATOM_DEVICE_DFP4_SUPPORT 0x0400 |
| 344 | * ATOM_DEVICE_DFP5_SUPPORT 0x0800 |
| 345 | * ATOM_DEVICE_LCD1_SUPPORT 0x0002 |
| 346 | */ |
| 347 | ULONG ulOtherDisplayMisc; ///< Other display related flags, not defined yet. |
| 348 | ULONG ulGPUCapInfo; /**> @li BIT[0] - TMDS/HDMI Coherent Mode 0: use cascade PLL mode, 1: use signel PLL mode. |
| 349 | * @li BIT[1] - DP mode 0: use cascade PLL mode, 1: use single PLL mode |
| 350 | * @li BIT[3] - AUX HW mode detection logic 0: Enable, 1: Disable |
| 351 | */ |
| 352 | ULONG ulSB_MMIO_Base_Addr; ///< Physical Base address to SB MMIO space. Driver need to initialize it for SMU usage. |
| 353 | USHORT usRequestedPWMFreqInHz; ///< Panel Required PWM frequency. if this parameter is 0 PWM from to control LCD Backlight will be disabled. |
| 354 | UCHAR ucHtcTmpLmt; ///< HTC temperature limit.The processor enters HTC-active state when Tctl reaches or exceeds HtcHystLmt. |
| 355 | UCHAR ucHtcHystLmt; ///< HTC hysteresis.The processor exits HTC-active state when Tctl is less than HtcTmpLmt minus HtcHystLmt. |
| 356 | ULONG ulMinEngineClock; ///< Min SCLK |
| 357 | ULONG ulSystemConfig; ///< TBD |
| 358 | ULONG ulCPUCapInfo; ///< TBD |
| 359 | USHORT usNBP0Voltage; ///< VID for voltage on NB P0 State |
| 360 | USHORT usNBP1Voltage; ///< VID for voltage on NB P1 State |
| 361 | USHORT usBootUpNBVoltage; ///< Voltage Index of GNB voltage configured by SBIOS, which is sufficient to support VBIOS DISPCLK requirement. |
| 362 | USHORT usExtDispConnInfoOffset; ///< Offset to sExtDispConnInfo inside the structure |
| 363 | USHORT usPanelRefreshRateRange; /**< Bit vector for LVDS/eDP supported refresh rate range. If DRR is enabled, 2 of the bits must be set. |
| 364 | * SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 |
| 365 | * SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 |
| 366 | * SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 |
| 367 | * SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 |
| 368 | */ |
| 369 | UCHAR ucMemoryType; ///< Memory type (3 for DDR3) |
| 370 | UCHAR ucUMAChannelNumber; ///< System memory channel numbers. |
| 371 | UCHAR strVBIOSMsg[40]; ///< Allow customer to have its own VBIOS message |
| 372 | ULONG ulReserved[20]; ///< |
| 373 | ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5]; ///< Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high |
| 374 | ULONG ulGMCRestoreResetTime; ///< GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. |
| 375 | ULONG ulMinimumNClk; ///< Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz. |
| 376 | ULONG ulIdleNClk; ///< NCLK speed while memory runs in self-refresh state. Unit in 10kHz. |
| 377 | ULONG ulDDR_DLL_PowerUpTime; ///< DDR PHY DLL power up time. Unit in ns. |
| 378 | ULONG ulDDR_PLL_PowerUpTime; ///< DDR PHY PLL power up time. Unit in ns |
| 379 | USHORT usPCIEClkSSPercentage; ///< |
| 380 | USHORT usPCIEClkSSType; ///< |
| 381 | USHORT usLvdsSSPercentage; ///< |
| 382 | USHORT usLvdsSSpreadRateIn10Hz; ///< |
| 383 | USHORT usHDMISSPercentage; ///< |
| 384 | USHORT usHDMISSpreadRateIn10Hz; ///< |
| 385 | USHORT usDVISSPercentage; ///< |
| 386 | USHORT usDVISSpreadRateIn10Hz; ///< |
| 387 | ULONG SclkDpmBoostMargin; ///< |
| 388 | ULONG SclkDpmThrottleMargin; ///< |
| 389 | USHORT SclkDpmTdpLimitPG; ///< |
| 390 | USHORT SclkDpmTdpLimitBoost; ///< |
| 391 | ULONG ulBoostEngineCLock; ///< |
| 392 | UCHAR ulBoostVid_2bit; ///< |
| 393 | UCHAR EnableBoost; ///< |
| 394 | USHORT GnbTdpLimit; ///< |
| 395 | USHORT usMaxLVDSPclkFreqInSingleLink; ///< |
| 396 | UCHAR ucLvdsMisc; ///< |
| 397 | UCHAR gnbgfxline429 ; ///< |
| 398 | UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms; ///< |
| 399 | UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms; ///< |
| 400 | UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms; ///< |
| 401 | UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms; ///< |
| 402 | UCHAR ucLVDSOffToOnDelay_in4Ms; ///< |
| 403 | UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms; ///< |
| 404 | UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms; ///< |
| 405 | UCHAR ucLVDSReserved1; ///< |
| 406 | ULONG ulLCDBitDepthControlVal; ///< |
| 407 | ULONG ulNbpStateMemclkFreq[4]; ///< |
| 408 | USHORT usNBP2Voltage; ///< |
| 409 | USHORT usNBP3Voltage; ///< |
| 410 | ULONG ulNbpStateNClkFreq[4]; ///< |
| 411 | UCHAR ucNBDPMEnable; ///< |
| 412 | UCHAR ucReserved[3]; ///< |
| 413 | UCHAR ucDPMState0VclkFid; ///< |
| 414 | UCHAR ucDPMState0DclkFid; ///< |
| 415 | UCHAR ucDPMState1VclkFid; ///< |
| 416 | UCHAR ucDPMState1DclkFid; ///< |
| 417 | UCHAR ucDPMState2VclkFid; ///< |
| 418 | UCHAR ucDPMState2DclkFid; ///< |
| 419 | UCHAR ucDPMState3VclkFid; ///< |
| 420 | UCHAR ucDPMState3DclkFid; ///< |
| 421 | ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; ///< |
| 422 | } ATOM_INTEGRATED_SYSTEM_INFO_V1_7; |
| 423 | |
| 424 | /// this Table is used for Llano/Ontario APU |
| 425 | typedef struct _ATOM_FUSION_SYSTEM_INFO_V2 { |
| 426 | ATOM_INTEGRATED_SYSTEM_INFO_V1_7 sIntegratedSysInfo; ///< Refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_7 definition. |
| 427 | ULONG ulPowerplayTable[128]; ///< This 512 bytes memory is used to save ATOM_PPLIB_POWERPLAYTABLE3, starting form ulPowerplayTable[0] |
| 428 | } ATOM_FUSION_SYSTEM_INFO_V2; |
| 429 | |
| 430 | #define GNB_SBDFO MAKE_SBDFO(0, 0, 0, 0, 0) |
| 431 | |
| 432 | /// Define configuration values for ulGPUCapInfo |
| 433 | // BIT[0] - TMDS/HDMI Coherent Mode 0: use cascade PLL mode, 1: use signel PLL mode. |
| 434 | #define GPUCAPINFO_TMDS_HDMI_USE_CASCADE_PLL_MODE 0x00ul |
| 435 | #define GPUCAPINFO_TMDS_HDMI_USE_SINGLE_PLL_MODE 0x01ul |
| 436 | |
| 437 | // BIT[1] - DP mode 0: use cascade PLL mode, 1: use single PLL mode |
| 438 | #define GPUCAPINFO_DP_MODE_USE_CASCADE_PLL_MODE 0x00ul |
| 439 | #define GPUCAPINFO_DP_USE_SINGLE_PLL_MODE 0x02ul |
| 440 | |
| 441 | // BIT[3] - AUX HW mode detection logic 0: Enable, 1: Disable |
| 442 | #define GPUCAPINFO_AUX_HW_MODE_DETECTION_ENABLE 0x00ul |
| 443 | #define GPUCAPINFO_AUX_HW_MODE_DETECTION_DISABLE 0x08ul |
| 444 | |
| 445 | #endif |