zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * Config Fch Gpp controller |
| 6 | * |
| 7 | * Init Gpp features (PEI phase). |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: FCH |
| 12 | * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ |
| 13 | * |
| 14 | */ |
| 15 | /* |
| 16 | ***************************************************************************** |
| 17 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 18 | * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. |
| 19 | * All rights reserved. |
| 20 | * |
| 21 | * Redistribution and use in source and binary forms, with or without |
| 22 | * modification, are permitted provided that the following conditions are met: |
| 23 | * * Redistributions of source code must retain the above copyright |
| 24 | * notice, this list of conditions and the following disclaimer. |
| 25 | * * Redistributions in binary form must reproduce the above copyright |
| 26 | * notice, this list of conditions and the following disclaimer in the |
| 27 | * documentation and/or other materials provided with the distribution. |
| 28 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 29 | * its contributors may be used to endorse or promote products derived |
| 30 | * from this software without specific prior written permission. |
| 31 | * |
| 32 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 33 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 34 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 35 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 36 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 37 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 38 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 39 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 40 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 41 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 42 | **************************************************************************** |
| 43 | */ |
| 44 | #include "FchPlatform.h" |
| 45 | #include "Filecode.h" |
| 46 | #define FILECODE PROC_FCH_PCIE_GPPRESET_FILECODE |
| 47 | |
| 48 | |
| 49 | // |
| 50 | //----------------------------------------------------------------------------------- |
| 51 | // Early GPP initialization sequence: |
| 52 | // |
| 53 | // 1) Set port enable bit fields by current GPP link configuration mode |
| 54 | // 2) Deassert GPP reset and pull EP out of reset - Clear GPP_RESET (abcfg:0xC0[8] = 0) |
| 55 | // 3) Loop polling for the link status of all ports |
| 56 | // 4) Misc operations after link training: |
| 57 | // - (optional) Detect GFX device |
| 58 | // - Hide empty GPP configuration spaces (Disable empty GPP ports) |
| 59 | // - (optional) Power down unused GPP ports |
| 60 | // - (optional) Configure PCIE_P2P_Int_Map (abcfg:0xC4[7:0]) |
| 61 | // 5) GPP init completed |
| 62 | // |
| 63 | // |
| 64 | // *) Gen2 vs Gen1 |
| 65 | // Gen2 mode Gen1 mode |
| 66 | // --------------------------------------------------------------- |
| 67 | // STRAP_PHY_PLL_CLKF[6:0] 7'h32 7'h19 |
| 68 | // STRAP_BIF_GEN2_EN 1 0 |
| 69 | // |
| 70 | // PCIE_PHY_PLL clock locks @ 5GHz |
| 71 | // |
| 72 | // |
| 73 | |
| 74 | /** |
| 75 | * FchInitResetGpp - Config Gpp during Power-On |
| 76 | * |
| 77 | * |
| 78 | * |
| 79 | * @param[in] FchDataPtr Fch configuration structure pointer. |
| 80 | * |
| 81 | */ |
| 82 | VOID |
| 83 | FchInitResetGpp ( |
| 84 | IN VOID *FchDataPtr |
| 85 | ) |
| 86 | { |
| 87 | FCH_RESET_DATA_BLOCK *LocalCfgPtr; |
| 88 | AMD_CONFIG_PARAMS *StdHeader; |
| 89 | |
| 90 | LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr; |
| 91 | StdHeader = LocalCfgPtr->StdHeader; |
| 92 | if ( LocalCfgPtr->Gpp.NewGppAlgorithm == TRUE ) { |
| 93 | if (ReadFchSleepType (StdHeader) == ACPI_SLPTYP_S3) { |
| 94 | FchGppPortInitS3Phase (&LocalCfgPtr->Gpp, StdHeader); |
| 95 | } |
| 96 | } |
| 97 | } |
| 98 | |
| 99 | |