blob: d71736902abd6b0194a49131feba5fbaad7c00b8 [file] [log] [blame]
zbao7d94cf92012-07-02 14:19:14 +08001/* $NoKeywords:$ */
2/**
3 * @file
4 *
5 * Config Hudson2 Pcie controller
6 *
7 * Init GPP (pcie Controller) features.
8 *
9 * @xrefitem bom "File Content Label" "Release Content"
10 * @e project: AGESA
11 * @e sub-project: FCH
12 * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
13 *
14 */
15/*
16*****************************************************************************
17*
Siyuan Wang641f00c2013-06-08 11:50:55 +080018 * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
19 * All rights reserved.
20 *
21 * Redistribution and use in source and binary forms, with or without
22 * modification, are permitted provided that the following conditions are met:
23 * * Redistributions of source code must retain the above copyright
24 * notice, this list of conditions and the following disclaimer.
25 * * Redistributions in binary form must reproduce the above copyright
26 * notice, this list of conditions and the following disclaimer in the
27 * documentation and/or other materials provided with the distribution.
28 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
29 * its contributors may be used to endorse or promote products derived
30 * from this software without specific prior written permission.
31 *
32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
34 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
36 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
37 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
38 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
39 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
41 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
zbao7d94cf92012-07-02 14:19:14 +080042****************************************************************************
43*/
44#include "FchPlatform.h"
45#include "Ids.h"
46#include "Filecode.h"
47#define FILECODE PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2GPPSERVICE_FILECODE
48
49/**
50 * ProgramGppTogglePcieReset - Toggle PCIE_RST2#
51 *
52 *
53 * @param[in] DoToggling
54 * @param[in] StdHeader
55 *
56 */
57VOID
58ProgramGppTogglePcieReset (
59 IN BOOLEAN DoToggling,
60 IN AMD_CONFIG_PARAMS *StdHeader
61 )
62{
63 if (DoToggling) {
64 FchResetPcie (FchBlock, AssertReset, StdHeader);
65 FchStall (500, StdHeader);
66 FchResetPcie (FchBlock, DeassertReset, StdHeader);
67 } else {
68 RwMem (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GEVENT_REG04, AccessWidth8, (UINT32)~(BIT1 + BIT0), 0x02);
69 }
70}
71
72/**
73 * FchGppDynamicPowerSaving - GPP Dynamic Power Saving
74 *
75 *
76 * @param[in] FchGpp Pointer to Fch GPP configuration structure
77 * @param[in] StdHeader Pointer to AMD_CONFIG_PARAMS
78 *
79 */
80VOID
81FchGppDynamicPowerSaving (
82 IN FCH_GPP *FchGpp,
83 IN AMD_CONFIG_PARAMS *StdHeader
84 )
85{
86 FCH_GPP_PORT_CONFIG *PortCfg;
87 UINT32 GppData32;
88 UINT32 HoldGppData32;
89 UINT32 AbValue;
90
91 if (!FchGpp->GppDynamicPowerSaving || FchGpp->SerialDebugBusEnable) {
92 return;
93 }
94
95 if (FchGpp->GppHardwareDownGrade) {
96 PortCfg = &FchGpp->PortCfg[FchGpp->GppHardwareDownGrade - 1];
97 PortCfg->PortDetected = TRUE;
98 }
99
100 GppData32 = 0;
101 HoldGppData32 = 0;
102
103 switch ( FchGpp->GppLinkConfig ) {
104 case PortA4:
105 PortCfg = &FchGpp->PortCfg[0];
106 if ( PortCfg->PortDetected == FALSE ) {
107 GppData32 |= 0x0f0f;
108 HoldGppData32 |= 0x1000;
109 }
110 break;
111
112 case PortA2B2:
113 PortCfg = &FchGpp->PortCfg[0];
114 if ( PortCfg->PortDetected == FALSE ) {
115 GppData32 |= ( FchGpp->GppLaneReversal )? 0x0c0c:0x0303;
116 HoldGppData32 |= 0x1000;
117 }
118
119 PortCfg = &FchGpp->PortCfg[1];
120 if ( PortCfg->PortDetected == FALSE ) {
121 GppData32 |= ( FchGpp->GppLaneReversal )? 0x0303:0x0c0c;
122 HoldGppData32 |= 0x2000;
123 }
124 break;
125
126 case PortA2B1C1:
127 PortCfg = &FchGpp->PortCfg[0];
128 if ( PortCfg->PortDetected == FALSE ) {
129 GppData32 |= ( FchGpp->GppLaneReversal )? 0x0c0c:0x0303;
130 HoldGppData32 |= 0x1000;
131 }
132
133 PortCfg = &FchGpp->PortCfg[1];
134 if ( PortCfg->PortDetected == FALSE ) {
135 GppData32 |= ( FchGpp->GppLaneReversal )? 0x0202:0x0404;
136 HoldGppData32 |= 0x2000;
137 }
138
139 PortCfg = &FchGpp->PortCfg[2];
140 if ( PortCfg->PortDetected == FALSE ) {
141 GppData32 |= ( FchGpp->GppLaneReversal )? 0x0101:0x0808;
142 HoldGppData32 |= 0x4000;
143 }
144 break;
145
146 case PortA1B1C1D1:
147 PortCfg = &FchGpp->PortCfg[0];
148 if ( PortCfg->PortDetected == FALSE ) {
149 GppData32 |= ( FchGpp->GppLaneReversal )? 0x0808:0x0101;
150 HoldGppData32 |= 0x1000;
151 }
152
153 PortCfg = &FchGpp->PortCfg[1];
154 if ( PortCfg->PortDetected == FALSE ) {
155 GppData32 |= ( FchGpp->GppLaneReversal )? 0x0404:0x0202;
156 HoldGppData32 |= 0x2000;
157 }
158
159 PortCfg = &FchGpp->PortCfg[2];
160 if ( PortCfg->PortDetected == FALSE ) {
161 GppData32 |= ( FchGpp->GppLaneReversal )? 0x0202:0x0404;
162 HoldGppData32 |= 0x4000;
163 }
164
165 PortCfg = &FchGpp->PortCfg[3];
166 if ( PortCfg->PortDetected == FALSE ) {
167 GppData32 |= ( FchGpp->GppLaneReversal )? 0x0101:0x0808;
168 HoldGppData32 |= 0x8000;
169 }
170 break;
171
172 default:
173 ASSERT (FALSE);
174 break;
175 }
176
177 //
178 // Power Saving With GPP Disable
179 // ABCFG 0xC0[8] = 0x0
180 // ABCFG 0xC0[15:12] = 0xF
181 // Enable "Power Saving Feature for A-Link Express Lanes"
182 // Enable "Power Saving Feature for GPP Lanes"
183 // ABCFG 0x90[19] = 1
184 // ABCFG 0x90[6] = 1
185 // RCINDC_Reg 0x65 [27:0] = 0xFFFFFFF
186 // ABCFG 0xC0[7:4] = 0x0
187 //
188 if (FchGpp->UmiPhyPllPowerDown && FchGpp->GppPhyPllPowerDown ) {
189 AbValue = ReadAlink (FCH_ABCFG_REGC0 | (UINT32) (ABCFG << 29), StdHeader);
190 WriteAlink (FCH_ABCFG_REGC0 | (UINT32) (ABCFG << 29), (( AbValue | HoldGppData32 ) & (~ BIT8 )), StdHeader);
191 RwAlink (FCH_AX_INDXC_REG40, (UINT32)~(BIT9 + BIT4), (BIT0 + BIT3 + BIT12), StdHeader);
192 RwAlink ((FCH_ABCFG_REG90 | (UINT32) (ABCFG << 29)), 0xFFFFFFFF, (BIT6 + BIT19), StdHeader);
193 RwAlink (FCH_RCINDXC_REG65, 0xFFFFFFFF, ((GppData32 & 0x0F) == 0x0F) ? GppData32 | 0x0CFF0000 : GppData32, StdHeader);
194 }
195}
196