zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * Config Hudson2 Pcie controller |
| 6 | * |
| 7 | * Init GPP (pcie Controller) features. |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: FCH |
| 12 | * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ |
| 13 | * |
| 14 | */ |
| 15 | /* |
| 16 | ***************************************************************************** |
| 17 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 18 | * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. |
| 19 | * All rights reserved. |
| 20 | * |
| 21 | * Redistribution and use in source and binary forms, with or without |
| 22 | * modification, are permitted provided that the following conditions are met: |
| 23 | * * Redistributions of source code must retain the above copyright |
| 24 | * notice, this list of conditions and the following disclaimer. |
| 25 | * * Redistributions in binary form must reproduce the above copyright |
| 26 | * notice, this list of conditions and the following disclaimer in the |
| 27 | * documentation and/or other materials provided with the distribution. |
| 28 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 29 | * its contributors may be used to endorse or promote products derived |
| 30 | * from this software without specific prior written permission. |
| 31 | * |
| 32 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 33 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 34 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 35 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 36 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 37 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 38 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 39 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 40 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 41 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 42 | **************************************************************************** |
| 43 | */ |
| 44 | #include "FchPlatform.h" |
| 45 | #include "Filecode.h" |
| 46 | #define FILECODE PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2GPPRESETSERVICE_FILECODE |
| 47 | |
| 48 | |
| 49 | /** |
| 50 | * ProgramFchGppInitReset - Config Gpp at PowerOnReset |
| 51 | * |
| 52 | * |
| 53 | * @param[in] FchGpp Pointer to Fch GPP configuration structure |
| 54 | * @param[in] StdHeader Pointer to AMD_CONFIG_PARAMS |
| 55 | * |
| 56 | */ |
| 57 | VOID |
| 58 | ProgramFchGppInitReset ( |
| 59 | IN FCH_GPP *FchGpp, |
| 60 | IN AMD_CONFIG_PARAMS *StdHeader |
| 61 | ) |
| 62 | { |
| 63 | // |
| 64 | // Toggle GEVENT4 to reset all GPP devices |
| 65 | // |
| 66 | ProgramGppTogglePcieReset (FchGpp->GppToggleReset, StdHeader); |
| 67 | if (FchGpp->SerialDebugBusEnable) { |
| 68 | RwAlink (FCH_ABCFG_REGC0, (UINT32) (ABCFG << 29), (UINT32)~BIT12, 0x00); |
| 69 | } |
| 70 | } |
| 71 | |
| 72 | /** |
| 73 | * FchResetPcie - Toggle GEVENT4 to assert/deassert GPP device |
| 74 | * reset |
| 75 | * |
| 76 | * |
| 77 | * @param[in] ResetBlock - PCIE reset for FCH GPP or NB PCIE |
| 78 | * @param[in] ResetOp - Assert or deassert PCIE reset |
| 79 | * @param[in] StdHeader |
| 80 | * |
| 81 | */ |
| 82 | VOID |
| 83 | FchResetPcie ( |
| 84 | IN RESET_BLOCK ResetBlock, |
| 85 | IN RESET_OP ResetOp, |
| 86 | IN AMD_CONFIG_PARAMS *StdHeader |
| 87 | ) |
| 88 | { |
| 89 | UINT8 Or8; |
| 90 | UINT8 Mask8; |
| 91 | |
| 92 | if (ResetBlock == NbBlock) { |
| 93 | if (ResetOp == AssertReset) { |
| 94 | Or8 = BIT4; |
| 95 | Mask8 = 0; |
| 96 | LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGC4), &Or8, &Mask8, StdHeader); |
| 97 | } else if (ResetOp == DeassertReset) { |
| 98 | Or8 = 0; |
| 99 | Mask8 = BIT4; |
| 100 | LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGC4), &Or8, &Mask8, StdHeader); |
| 101 | } |
| 102 | } else if (ResetBlock == FchBlock) { |
| 103 | Or8 = BIT1; |
| 104 | Mask8 = BIT1 + BIT0; |
| 105 | LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GEVENT_REG04), &Or8, &Mask8, StdHeader); |
| 106 | if (ResetOp == AssertReset) { |
| 107 | Or8 = 0; |
| 108 | Mask8 = BIT5; |
| 109 | LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + GPIO_BASE + FCH_GEVENT_REG04), &Or8, &Mask8, StdHeader); |
| 110 | Or8 = BIT4; |
| 111 | Mask8 = 0; |
| 112 | LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGBF), &Or8, &Mask8, StdHeader); |
| 113 | } else if (ResetOp == DeassertReset) { |
| 114 | Or8 = 0; |
| 115 | Mask8 = BIT4; |
| 116 | LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGBF), &Or8, &Mask8, StdHeader); |
| 117 | Or8 = BIT5; |
| 118 | Mask8 = 0; |
| 119 | LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + GPIO_BASE + FCH_GEVENT_REG04), &Or8, &Mask8, StdHeader); |
| 120 | } |
| 121 | } |
| 122 | } |
| 123 | |