zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * Config Fch Pcib controller |
| 6 | * |
| 7 | * Init Pcib Controller features (PEI phase). |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: FCH |
| 12 | * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ |
| 13 | * |
| 14 | */ |
| 15 | /* |
| 16 | ***************************************************************************** |
| 17 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 18 | * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. |
| 19 | * All rights reserved. |
| 20 | * |
| 21 | * Redistribution and use in source and binary forms, with or without |
| 22 | * modification, are permitted provided that the following conditions are met: |
| 23 | * * Redistributions of source code must retain the above copyright |
| 24 | * notice, this list of conditions and the following disclaimer. |
| 25 | * * Redistributions in binary form must reproduce the above copyright |
| 26 | * notice, this list of conditions and the following disclaimer in the |
| 27 | * documentation and/or other materials provided with the distribution. |
| 28 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 29 | * its contributors may be used to endorse or promote products derived |
| 30 | * from this software without specific prior written permission. |
| 31 | * |
| 32 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 33 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 34 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 35 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 36 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 37 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 38 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 39 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 40 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 41 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 42 | **************************************************************************** |
| 43 | */ |
| 44 | #include "FchPlatform.h" |
| 45 | #define FILECODE PROC_FCH_PCIB_PCIBRESET_FILECODE |
| 46 | /** |
| 47 | * FchInitResetPcibPciTable - Pcib device registers initial |
| 48 | * during the power on stage. |
| 49 | * |
| 50 | * |
| 51 | * |
| 52 | * |
| 53 | */ |
Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame] | 54 | CONST REG8_MASK FchInitResetPcibPciTable[] = |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 55 | { |
| 56 | // |
| 57 | // P2P Bridge (Bus 0, Dev 20, Func 4) |
| 58 | // |
| 59 | {0x00, PCIB_BUS_DEV_FUN, 0}, |
| 60 | {FCH_PCIB_REG4B, 0xFF, BIT6 + BIT7 + BIT4}, |
| 61 | {FCH_PCIB_REG40, 0xDF, 0x20}, |
| 62 | {0x50 , 0x02, 0x01}, |
| 63 | {0xFF, 0xFF, 0xFF}, |
| 64 | }; |
| 65 | |
| 66 | /** |
| 67 | * FchInitResetPcib - Config Pcib controller during Power-On |
| 68 | * |
| 69 | * |
| 70 | * |
| 71 | * @param[in] FchDataPtr Fch configuration structure pointer. |
| 72 | * |
| 73 | */ |
| 74 | VOID |
| 75 | FchInitResetPcib ( |
| 76 | IN VOID *FchDataPtr |
| 77 | ) |
| 78 | { |
| 79 | AMD_CONFIG_PARAMS *StdHeader; |
| 80 | |
| 81 | StdHeader = &((AMD_RESET_PARAMS *)FchDataPtr)->StdHeader; |
| 82 | |
| 83 | ProgramPciByteTable ( |
| 84 | (REG8_MASK*) (&FchInitResetPcibPciTable[0]), |
Patrick Georgi | 6b688f5 | 2021-02-12 13:49:11 +0100 | [diff] [blame] | 85 | ARRAY_SIZE(FchInitResetPcibPciTable), |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 86 | StdHeader |
| 87 | ); |
| 88 | if ( UserOptions.FchBldCfg->CfgFchPort80BehindPcib ) { |
| 89 | FchInitResetPcibPort80Enable (FchDataPtr); |
| 90 | } |
| 91 | } |
| 92 | |
| 93 | /** |
| 94 | * FchInitResetPcibPort80Enable - Pcib device registers initial |
| 95 | * during the power on stage. |
| 96 | * |
| 97 | * |
| 98 | * |
| 99 | * |
| 100 | */ |
Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame] | 101 | CONST REG8_MASK FchInitResetPcibPort80EnableTable[] = |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 102 | { |
| 103 | // |
| 104 | // P2P Bridge (Bus 0, Dev 20, Func 4) |
| 105 | // |
| 106 | {0x00, PCIB_BUS_DEV_FUN, 0}, |
| 107 | {0x1C , 0x00, 0xF0}, |
| 108 | {0x1D , 0x00, 0x00}, |
| 109 | {0x04 , 0x00, 0x21}, |
| 110 | {0xFF, 0xFF, 0xFF}, |
| 111 | }; |
| 112 | |
| 113 | /** |
| 114 | * FchInitResetPcibPort80Enable - Enable Port80 Behind PCIB |
| 115 | * |
| 116 | * |
| 117 | * |
| 118 | * @param[in] FchDataPtr Fch configuration structure pointer. |
| 119 | * |
| 120 | */ |
| 121 | VOID |
| 122 | FchInitResetPcibPort80Enable ( |
| 123 | IN VOID *FchDataPtr |
| 124 | ) |
| 125 | { |
| 126 | AMD_CONFIG_PARAMS *StdHeader; |
| 127 | |
| 128 | StdHeader = &((AMD_RESET_PARAMS *)FchDataPtr)->StdHeader; |
| 129 | |
| 130 | ProgramPciByteTable ( |
| 131 | (REG8_MASK*) (&FchInitResetPcibPort80EnableTable[0]), |
Patrick Georgi | 6b688f5 | 2021-02-12 13:49:11 +0100 | [diff] [blame] | 132 | ARRAY_SIZE(FchInitResetPcibPort80EnableTable), |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 133 | StdHeader |
| 134 | ); |
| 135 | } |