zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * Config Fch Ir controller |
| 6 | * |
| 7 | * Init Ir Controller features. |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: FCH |
| 12 | * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ |
| 13 | * |
| 14 | */ |
| 15 | /* |
| 16 | ***************************************************************************** |
| 17 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 18 | * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. |
| 19 | * All rights reserved. |
| 20 | * |
| 21 | * Redistribution and use in source and binary forms, with or without |
| 22 | * modification, are permitted provided that the following conditions are met: |
| 23 | * * Redistributions of source code must retain the above copyright |
| 24 | * notice, this list of conditions and the following disclaimer. |
| 25 | * * Redistributions in binary form must reproduce the above copyright |
| 26 | * notice, this list of conditions and the following disclaimer in the |
| 27 | * documentation and/or other materials provided with the distribution. |
| 28 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 29 | * its contributors may be used to endorse or promote products derived |
| 30 | * from this software without specific prior written permission. |
| 31 | * |
| 32 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 33 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 34 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 35 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 36 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 37 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 38 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 39 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 40 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 41 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 42 | **************************************************************************** |
| 43 | */ |
| 44 | #include "FchPlatform.h" |
| 45 | #define FILECODE PROC_FCH_IR_IRENV_FILECODE |
| 46 | |
| 47 | /** |
| 48 | * FchInitEnvIr - Config Ir controller before PCI emulation |
| 49 | * |
| 50 | * |
| 51 | * |
| 52 | * @param[in] FchDataPtr Fch configuration structure pointer. |
| 53 | * |
| 54 | */ |
| 55 | VOID |
| 56 | FchInitEnvIr ( |
| 57 | IN VOID *FchDataPtr |
| 58 | ) |
| 59 | { |
| 60 | IR_CONFIG FchIrConfig; |
| 61 | UINT8 FchIrPinControl; |
| 62 | UINT8 Data; |
| 63 | FCH_DATA_BLOCK *LocalCfgPtr; |
| 64 | AMD_CONFIG_PARAMS *StdHeader; |
| 65 | |
| 66 | LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; |
| 67 | StdHeader = LocalCfgPtr->StdHeader; |
| 68 | FchIrConfig = LocalCfgPtr->Ir.IrConfig; |
| 69 | FchIrPinControl = LocalCfgPtr->Ir.IrPinControl; |
| 70 | |
| 71 | // |
| 72 | //IR init Logical device 0x05 |
| 73 | // |
| 74 | if (FchIrConfig != IrDisable) { |
| 75 | EnterEcConfig (StdHeader); |
| 76 | |
| 77 | RwEc8 (0x07, 0x00, 0x05, StdHeader); ///Select logical device 05, IR controller |
| 78 | RwEc8 (0x60, 0x00, 0x05, StdHeader); ///Set Base Address to 550h |
| 79 | RwEc8 (0x61, 0x00, 0x50, StdHeader); |
| 80 | RwEc8 (0x70, 0xF0, 0x05, StdHeader); ///Set IRQ to 05h |
| 81 | RwEc8 (0x30, 0x00, 0x01, StdHeader); ///Enable logical device 5, IR controller |
| 82 | |
| 83 | Data = 0xAB; |
| 84 | LibAmdIoWrite (AccessWidth8, 0x550, &Data, StdHeader); |
| 85 | LibAmdIoRead (AccessWidth8, 0x551, &Data, StdHeader); |
| 86 | Data = (UINT8) (FchIrPinControl & 0xFC); ///Take out enable bits |
| 87 | Data |= FchIrPinControl & FchIrConfig & 0x03; ///Put back enable bits |
| 88 | LibAmdIoWrite (AccessWidth8, 0x551, &Data, StdHeader); |
| 89 | |
| 90 | ExitEcConfig (StdHeader); |
| 91 | |
| 92 | Data = 0xA0; /// EC APIC index |
| 93 | LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC00, &Data, StdHeader); |
| 94 | Data = 0x05; /// IRQ5 |
| 95 | LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC01, &Data, StdHeader); |
| 96 | } else { |
| 97 | EnterEcConfig (StdHeader); |
| 98 | |
| 99 | RwEc8 (0x07, 0x00, 0x05, StdHeader); ///Select logical device 05, IR controller |
| 100 | RwEc8 (0x30, 0x00, 0x00, StdHeader); ///Disable logical device 5, IR controller |
| 101 | Data = 0xAB; |
| 102 | LibAmdIoWrite (AccessWidth8, 0x550, &Data, StdHeader); |
| 103 | LibAmdIoRead (AccessWidth8, 0x551, &Data, StdHeader); |
| 104 | Data = ((UINT8) FchIrPinControl) & 0xFC; //Clear Enable bits |
| 105 | LibAmdIoWrite (AccessWidth8, 0x551, &Data, StdHeader); |
| 106 | ExitEcConfig (StdHeader); |
| 107 | } |
| 108 | } |