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review.coreboot.org / coreboot / 9a458e4e58edbfc154dce007961514b5c31cf7aa / . / src / vendorcode / amd / agesa / f15tn / Proc / Fch / Interface / Family / Hudson2 / ResetDefHudson2.c
blob: 9f299a8ff4440387634dda3ab8fdd6d411581496 [file] [log] [blame]
zbao7d94cf92012-07-02 14:19:14 +0800[diff] [blame]1/* $NoKeywords:$ */
2/**
3 * @file
4 *
5 * Graphics Controller family specific service procedure
6 *
7 *
8 *
9 * @xrefitem bom "File Content Label" "Release Content"
10 * @e project: AGESA
11 * @e sub-project: FCH
12 * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
13 *
14 */
15/*
16*****************************************************************************
17*
Siyuan Wang641f00c2013-06-08 11:50:55 +0800[diff] [blame]18 * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
19 * All rights reserved.
20 *
21 * Redistribution and use in source and binary forms, with or without
22 * modification, are permitted provided that the following conditions are met:
23 * * Redistributions of source code must retain the above copyright
24 * notice, this list of conditions and the following disclaimer.
25 * * Redistributions in binary form must reproduce the above copyright
26 * notice, this list of conditions and the following disclaimer in the
27 * documentation and/or other materials provided with the distribution.
28 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
29 * its contributors may be used to endorse or promote products derived
30 * from this software without specific prior written permission.
31 *
32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
34 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
36 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
37 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
38 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
39 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
41 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
zbao7d94cf92012-07-02 14:19:14 +0800[diff] [blame]42* ***************************************************************************
43*
44*/
45
46
47/*----------------------------------------------------------------------------------------
48 * M O D U L E S U S E D
49 *----------------------------------------------------------------------------------------
50 */
51#include "FchPlatform.h"
52#include "Filecode.h"
53/*----------------------------------------------------------------------------------------
54 * D E F I N I T I O N S A N D M A C R O S
55 *----------------------------------------------------------------------------------------
56 */
57
58
59
60/*----------------------------------------------------------------------------------------
61 * Default FCH interface settings at InitReset phase.
62 *----------------------------------------------------------------------------------------
63 */
64CONST FCH_RESET_INTERFACE ROMDATA FchResetInterfaceDefault = {
65 TRUE, // UmiGen2
66 TRUE, // SataEnable
67 TRUE, // IdeEnable
68 TRUE, // GppEnable
69 TRUE, // Xhci0Enable
70 TRUE // Xhci1Enable
71};
72
73
74/*----------------------------------------------------------------
75 * InitReset Phase Data Block Default (Failsafe)
76 *----------------------------------------------------------------
77 */
Arthur Heymans8d3640d2022-05-16 12:27:36 +0200[diff] [blame]78CONST FCH_RESET_DATA_BLOCK InitResetCfgDefault = {
zbao7d94cf92012-07-02 14:19:14 +0800[diff] [blame]79 NULL, // StdHeader
80 {0}, // FchReset
81
82 0, // FastSpeed
83 0, // WriteSpeed
84 0, // Mode
85 0, // AutoMode
86 0, // BurstWrite
87 FALSE, // SataIdeCombMdPriSecOpt
88 0, // Cg2Pll
89 FALSE, // EcKbd
90 FALSE, // LegacyFree
91 FALSE, // SataSetMaxGen2
92 9, // SataClkMode
93 0, // SataModeReg
94 FALSE, // SataInternal100Spread
95 2, // SpiSpeed
96 FALSE, // EcChannel0
97
98 { // FCH_GPP
99 { // Array of FCH_GPP_PORT_CONFIG PortCfg[4]
100 {
101 FALSE, // PortPresent
102 FALSE, // PortDetected
103 FALSE, // PortIsGen2
104 FALSE, // PortHotPlug
105 0, // PortMisc
106 },
107 {
108 FALSE, // PortPresent
109 FALSE, // PortDetected
110 FALSE, // PortIsGen2
111 FALSE, // PortHotPlug
112 0, // PortMisc
113 },
114 {
115 FALSE, // PortPresent
116 FALSE, // PortDetected
117 FALSE, // PortIsGen2
118 FALSE, // PortHotPlug
119 0, // PortMisc
120 },
121 {
122 FALSE, // PortPresent
123 FALSE, // PortDetected
124 FALSE, // PortIsGen2
125 FALSE, // PortHotPlug
126 0, // PortMisc
127 },
128 },
129 PortA1B1C1D1, // GppLinkConfig
130 FALSE, // GppFunctionEnable
131 FALSE, // GppToggleReset
132 0, // GppHotPlugGeventNum
133 0, // GppFoundGfxDev
134 FALSE, // GppGen2
135 0, // GppGen2Strap
136 FALSE, // GppMemWrImprove
137 FALSE, // GppUnhidePorts
138 0, // GppPortAspm
139 FALSE, // GppLaneReversal
140 TRUE, // GppPhyPllPowerDown
141 TRUE , // GppDynamicPowerSaving
142 FALSE, // PcieAer
143 FALSE, // PcieRas
144 FALSE, // PcieCompliance
145 FALSE, // PcieSoftwareDownGrade
146 TRUE, // UmiPhyPllPowerDown
147 FALSE, // SerialDebugBusEnable
148 0, // GppHardwareDownGrade
149 0, // GppL1ImmediateAck
150 TRUE, // NewGppAlgorithm
151 0, // HotPlugPortsStatus
152 0, // FailPortsStatus
153 40, // GppPortMinPollingTime
154 },
155 NULL // OemResetProgrammingTablePtr
156};