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zbao7d94cf92012-07-02 14:19:14 +08001/* $NoKeywords:$ */
2/**
3 * @file
4 *
5 * Config Fch HwAcpi controller
6 *
7 * Init HwAcpi Controller features.
8 *
9 * @xrefitem bom "File Content Label" "Release Content"
10 * @e project: AGESA
11 * @e sub-project: FCH
12 * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
13 *
14 */
15/*
16*****************************************************************************
17*
Siyuan Wang641f00c2013-06-08 11:50:55 +080018 * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
19 * All rights reserved.
20 *
21 * Redistribution and use in source and binary forms, with or without
22 * modification, are permitted provided that the following conditions are met:
23 * * Redistributions of source code must retain the above copyright
24 * notice, this list of conditions and the following disclaimer.
25 * * Redistributions in binary form must reproduce the above copyright
26 * notice, this list of conditions and the following disclaimer in the
27 * documentation and/or other materials provided with the distribution.
28 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
29 * its contributors may be used to endorse or promote products derived
30 * from this software without specific prior written permission.
31 *
32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
34 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
36 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
37 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
38 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
39 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
41 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
zbao7d94cf92012-07-02 14:19:14 +080042****************************************************************************
43*/
44#include "FchPlatform.h"
45#include "amdlib.h"
46#include "cpuServices.h"
47#include "Filecode.h"
48#define FILECODE PROC_FCH_HWACPI_HWACPILATE_FILECODE
49
50#define AMD_CPUID_APICID_LPC_BID 0x00000001ul // Local APIC ID, Logical Processor Count, Brand ID
51
52
53
54
55
56
57
58///
59/// PCI_IRQ_REG_BLOCK- FCH PCI IRQ registers block
60///
61typedef struct _PCI_IRQ_REG_BLOCK {
62 UINT8 PciIrqIndex; // PciIrqIndex - selects which PCI interrupt to map
63 UINT8 PciIrqData; // PciIrqData - Interrupt #
64} PCI_IRQ_REG_BLOCK;
65
66STATIC PCI_IRQ_REG_BLOCK FchInternalDeviceIrqForApicMode[] = {
67 { (FCH_IRQ_INTA | FCH_IRQ_IOAPIC), 0x10},
68 { (FCH_IRQ_INTB | FCH_IRQ_IOAPIC), 0x11},
69 { (FCH_IRQ_INTC | FCH_IRQ_IOAPIC), 0x12},
70 { (FCH_IRQ_INTD | FCH_IRQ_IOAPIC), 0x13},
71 { (FCH_IRQ_INTE | FCH_IRQ_IOAPIC), 0x14},
72 { (FCH_IRQ_INTF | FCH_IRQ_IOAPIC), 0x15},
73 { (FCH_IRQ_INTG | FCH_IRQ_IOAPIC), 0x16},
74 { (FCH_IRQ_INTH | FCH_IRQ_IOAPIC), 0x17},
75 { (FCH_IRQ_HDAUDIO | FCH_IRQ_IOAPIC), 0x10},
76 { (FCH_IRQ_GEC | FCH_IRQ_IOAPIC), 0x10},
77 { (FCH_IRQ_SD | FCH_IRQ_IOAPIC), 0x10},
78 { (FCH_IRQ_GPPINT0 | FCH_IRQ_IOAPIC), 0x10},
79 { (FCH_IRQ_IDE | FCH_IRQ_IOAPIC), 0x11},
80 { (FCH_IRQ_USB18INTB | FCH_IRQ_IOAPIC), 0x11},
81 { (FCH_IRQ_USB19INTB | FCH_IRQ_IOAPIC), 0x11},
82 { (FCH_IRQ_USB22INTB | FCH_IRQ_IOAPIC), 0x11},
83 { (FCH_IRQ_GPPINT1 + FCH_IRQ_IOAPIC), 0x11},
84 { (FCH_IRQ_USB18INTA | FCH_IRQ_IOAPIC), 0x12},
85 { (FCH_IRQ_USB19INTA | FCH_IRQ_IOAPIC), 0x12},
86 { (FCH_IRQ_USB22INTA | FCH_IRQ_IOAPIC), 0x12},
87 { (FCH_IRQ_USB20INTC | FCH_IRQ_IOAPIC), 0x12},
88 { (FCH_IRQ_GPPINT2 | FCH_IRQ_IOAPIC), 0x12},
89 { (FCH_IRQ_SATA | FCH_IRQ_IOAPIC), 0x13},
90 { (FCH_IRQ_GPPINT3 | FCH_IRQ_IOAPIC), 0x13},
91 };
92
Patrick Georgi6b688f52021-02-12 13:49:11 +010093#define NUM_OF_DEVICE_FOR_APICIRQ ARRAY_SIZE(FchInternalDeviceIrqForApicMode)
zbao7d94cf92012-07-02 14:19:14 +080094
95/**
96 * FchInitLateHwAcpi - Prepare HwAcpi controller to boot to OS.
97 *
98 * @param[in] FchDataPtr Fch configuration structure pointer.
99 *
100 */
101VOID
102FchInitLateHwAcpi (
103 IN VOID *FchDataPtr
104 )
105{
106 FCH_DATA_BLOCK *LocalCfgPtr;
107 AMD_CONFIG_PARAMS *StdHeader;
108 UINT8 i;
109
110 LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
111 StdHeader = LocalCfgPtr->StdHeader;
112
113 if ( IsGCPU (LocalCfgPtr) ) {
114 GcpuRelatedSetting (LocalCfgPtr);
115 } else {
116 //TNBU C3PopupSetting (LocalCfgPtr);
117 }
118
119 // Mt C1E Enable
120 MtC1eEnable (LocalCfgPtr);
121
122 if (LocalCfgPtr->Gpp.SerialDebugBusEnable == TRUE ) {
123 RwMem (ACPI_MMIO_BASE + SERIAL_DEBUG_BASE + FCH_SDB_REG00, AccessWidth8, 0xFF, 0x05);
124 }
125
126 StressResetModeLate (LocalCfgPtr);
127 SbSleepTrapControl (FALSE); /* TODO: Checkout if we need to disable sleep trap in Non-SMI mode. */
128 for (i = 0; i < NUM_OF_DEVICE_FOR_APICIRQ; i++) {
129 LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC00, &FchInternalDeviceIrqForApicMode[i].PciIrqIndex, StdHeader);
130 LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC01, &FchInternalDeviceIrqForApicMode[i].PciIrqData, StdHeader);
131 }
132}
133
134/**
135 * IsGCPU - Is Gcpu Cpu?
136 *
137 *
138 * @retval TRUE or FALSE
139 *
140 */
141BOOLEAN
142IsGCPU (
143 IN VOID *FchDataPtr
144 )
145{
146 UINT8 ExtendedFamily;
147 UINT8 ExtendedModel;
148 UINT8 BaseFamily;
149 UINT8 BaseModel;
150 UINT8 Stepping;
151 UINT8 Family;
152 UINT8 Model;
153 CPUID_DATA CpuId;
154 FCH_DATA_BLOCK *LocalCfgPtr;
155 AMD_CONFIG_PARAMS *StdHeader;
156
157 LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
158 StdHeader = LocalCfgPtr->StdHeader;
159
160 LibAmdCpuidRead (AMD_CPUID_APICID_LPC_BID, &CpuId, StdHeader);
161
162 ExtendedFamily = (UINT8) ((CpuId.EAX_Reg >> 20) & 0xff);
163 ExtendedModel = (UINT8) ((CpuId.EAX_Reg >> 16) & 0xf);
164 BaseFamily = (UINT8) ((CpuId.EAX_Reg >> 8) & 0xf);
165 BaseModel = (UINT8) ((CpuId.EAX_Reg >> 4) & 0xf);
166 Stepping = (UINT8) ((CpuId.EAX_Reg >> 0) & 0xf);
167 Family = BaseFamily + ExtendedFamily;
168 Model = (ExtendedModel << 4) + BaseModel;
169
170 if ( (Family == 0x12) || \
171 (Family == 0x14) || \
172 (Family == 0x16) ) {
173 return TRUE;
174 } else {
175 return FALSE;
176 }
177}
178