zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * Config Fch HwAcpi controller |
| 6 | * |
| 7 | * Init HwAcpi Controller features. |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: FCH |
| 12 | * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ |
| 13 | * |
| 14 | */ |
| 15 | /* |
| 16 | ***************************************************************************** |
| 17 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 18 | * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. |
| 19 | * All rights reserved. |
| 20 | * |
| 21 | * Redistribution and use in source and binary forms, with or without |
| 22 | * modification, are permitted provided that the following conditions are met: |
| 23 | * * Redistributions of source code must retain the above copyright |
| 24 | * notice, this list of conditions and the following disclaimer. |
| 25 | * * Redistributions in binary form must reproduce the above copyright |
| 26 | * notice, this list of conditions and the following disclaimer in the |
| 27 | * documentation and/or other materials provided with the distribution. |
| 28 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 29 | * its contributors may be used to endorse or promote products derived |
| 30 | * from this software without specific prior written permission. |
| 31 | * |
| 32 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 33 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 34 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 35 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 36 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 37 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 38 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 39 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 40 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 41 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 42 | **************************************************************************** |
| 43 | */ |
| 44 | #include "FchPlatform.h" |
| 45 | #include "amdlib.h" |
| 46 | #include "cpuServices.h" |
| 47 | #include "Filecode.h" |
| 48 | #define FILECODE PROC_FCH_HWACPI_FAMILY_HUDSON2_HUDSON2HWACPIENVSERVICE_FILECODE |
| 49 | |
| 50 | #define AMD_CPUID_APICID_LPC_BID 0x00000001ul // Local APIC ID, Logical Processor Count, Brand ID |
| 51 | |
| 52 | /** |
| 53 | * FchInitEnvHwAcpiMmioTable - Fch ACPI MMIO initial |
| 54 | * during POST. |
| 55 | * |
| 56 | */ |
| 57 | ACPI_REG_WRITE FchHudson2InitEnvHwAcpiMmioTable[] = |
| 58 | { |
| 59 | {00, 00, 0xB0, 0xAC}, /// Signature |
| 60 | |
| 61 | // |
| 62 | // HPET workaround |
| 63 | // |
| 64 | {PMIO_BASE >> 8, FCH_PMIOA_REG54 + 3, 0xFC, BIT0 + BIT1}, |
| 65 | {PMIO_BASE >> 8, FCH_PMIOA_REG54 + 2, 0x7F, BIT7}, |
| 66 | {PMIO_BASE >> 8, FCH_PMIOA_REG54 + 2, 0x7F, 0x00}, |
| 67 | // |
| 68 | // Enable Hudson-2 A12 ACPI bits at PMIO 0xC0 [30, 10:3] |
| 69 | // ClrAllStsInThermalEvent 3 Set to 1 to allow ASF remote power down/power cycle, Thermal event, Fan slow event to clear all the Gevent status and enabled bits. The bit should be set to 1 all the time. |
| 70 | // UsbGoodClkDlyEn 4 Set to 1 to delay de-assertion of Usb clk by 6 Osc clk. The bit should be set to 1 all the time. |
| 71 | // ForceNBCPUPwr 5 Set to 1 to force CPU pwrGood to be toggled along with NB pwrGood. |
| 72 | // MergeUsbPerReq 6 Set to 1 to merge usb perdical traffic into usb request as one of break event. |
| 73 | // IMCWatchDogRstEn 7 Set to 1 to allow IMC watchdog timer to reset entire acpi block. The bit should be set to 1 when IMC is enabled. |
| 74 | // GeventStsFixEn 8 1: Gevent status is not reset by its enable bit. 0: Gevent status is reset by its enable bit. |
| 75 | // PmeTimerFixEn 9 Set to 1 to reset Pme Timer when going to sleep state. |
| 76 | // UserRst2EcEn 10 Set to 1 to route user reset event to Ec. The bit should be set to 1 when IMC is enabled. |
| 77 | // Smbus0ClkSEn 30 Set to 1 to enable SMBus0 controller clock stretch support. |
| 78 | // |
| 79 | {PMIO_BASE >> 8, FCH_PMIOA_REGC4, (UINT8)~BIT2, BIT2}, |
| 80 | {PMIO_BASE >> 8, FCH_PMIOA_REGC0, 0, 0xF9}, |
| 81 | {PMIO_BASE >> 8, FCH_PMIOA_REGC0 + 1, 0x04, 0x07}, |
| 82 | // |
| 83 | // RtcSts 19-17 RTC_STS set only in Sleep State. |
| 84 | // GppPme 20 Set to 1 to enable PME request from SB GPP. |
| 85 | // Pcireset 22 Set to 1 to allow SW to reset PCIe. |
| 86 | // |
| 87 | {PMIO_BASE >> 8, 0xC2 , 0x20, 0x58}, |
| 88 | {PMIO_BASE >> 8, 0xC2 + 1, 0, 0x40}, |
| 89 | {PMIO_BASE >> 8, 0xC2 , (UINT8)~(BIT4), BIT4}, |
| 90 | |
| 91 | {PMIO_BASE >> 8, FCH_PMIOA_REGCC, 0xF8, 0x01}, |
| 92 | {PMIO_BASE >> 8, FCH_PMIOA_REG74, 0x00, BIT0 + BIT1 + BIT2 + BIT4}, |
| 93 | {PMIO_BASE >> 8, FCH_PMIOA_REG74 + 3, (UINT8)~BIT5, 0}, |
| 94 | {PMIO_BASE >> 8, 0xDE + 1, (UINT8)~(BIT0 + BIT1), BIT0 + BIT1}, |
| 95 | {PMIO_BASE >> 8, 0xDE , (UINT8)~BIT4, BIT4}, |
| 96 | {PMIO_BASE >> 8, FCH_PMIOA_REGBA, (UINT8)~BIT3, BIT3}, |
| 97 | {PMIO_BASE >> 8, FCH_PMIOA_REGBA + 1, (UINT8)~BIT6, BIT6}, |
| 98 | {PMIO_BASE >> 8, FCH_PMIOA_REGBC, (UINT8)~BIT1, BIT1}, |
| 99 | {PMIO_BASE >> 8, FCH_PMIOA_REGED, (UINT8)~(BIT0 + BIT1), 0}, |
| 100 | {PMIO_BASE >> 8, 0xDC , 0x7C, BIT0}, /// Hiding Flash Controller PM_IO 0xDC[7] = 0x0 & PM_IO 0xDC [1:0]=0x01 |
| 101 | {PMIO_BASE >> 8, FCH_PMIOA_REGBF, (UINT8)~BIT0, 0}, |
| 102 | {PMIO_BASE >> 8, FCH_PMIOA_REGBE, (UINT8)~BIT0, BIT0}, |
| 103 | |
| 104 | {SMI_BASE >> 8, 0x41 , 0, 1}, |
| 105 | {SMI_BASE >> 8, 0x43 , 0, 3}, |
| 106 | {SMI_BASE >> 8, 0x44 , 0, 4}, |
| 107 | {SMI_BASE >> 8, 0x45 , 0, 5}, |
| 108 | {SMI_BASE >> 8, 0x46 , 0, 6}, |
| 109 | {SMI_BASE >> 8, 0x57 , 0, 23}, |
| 110 | {SMI_BASE >> 8, 0x78 , 0, 11}, |
| 111 | {SMI_BASE >> 8, 0x79 , 0, 11}, |
| 112 | {SMI_BASE >> 8, 0x58 , 0, 11}, |
| 113 | {SMI_BASE >> 8, 0x59 , 0, 11}, |
| 114 | {SMI_BASE >> 8, 0x5A , 0, 11}, |
| 115 | {SMI_BASE >> 8, 0x5B , 0, 11}, |
| 116 | {SMI_BASE >> 8, 0x68 , 0, 12}, |
| 117 | {SMI_BASE >> 8, 0x6C , 0, 13}, |
| 118 | {SMI_BASE >> 8, 0x5C , 0, 15}, |
| 119 | {SMI_BASE >> 8, 0x5D , 0, 16}, |
| 120 | {SMI_BASE >> 8, 0x5E , 0, 17}, |
| 121 | {SMI_BASE >> 8, 0x5F , 0, 18}, |
| 122 | {SMI_BASE >> 8, 0x67 , 0, 19}, |
| 123 | {SMI_BASE >> 8, 0x6A , 0, 28}, |
| 124 | {SMI_BASE >> 8, 0x48 , 0, 24}, |
| 125 | {SMI_BASE >> 8, 0x64 , 0, 27}, |
| 126 | {SMI_BASE >> 8, 0x65 , 0, 30}, |
| 127 | {SMI_BASE >> 8, 0x66 , 0, 31}, |
| 128 | {SMI_BASE >> 8, FCH_SMI_REG08, 0xE7, 0}, |
| 129 | {SMI_BASE >> 8, FCH_SMI_REG0C + 2, (UINT8)~BIT3, BIT3}, |
| 130 | {SMI_BASE >> 8, 0x70 , 0, 9}, |
| 131 | {SMI_BASE >> 8, FCH_SMI_REG3C, 0, BIT6}, |
| 132 | {SMI_BASE >> 8, 0x84 + 2, 0, BIT7}, |
| 133 | |
| 134 | // |
| 135 | // CG PLL CMOX Clock Driver Setting for power saving |
| 136 | // |
| 137 | {MISC_BASE >> 8, FCH_MISC_REG18 + 0x06, 0, 0xE0}, |
| 138 | {MISC_BASE >> 8, FCH_MISC_REG18 + 0x07, 0, 0x1F}, |
| 139 | |
| 140 | {MISC_BASE >> 8, 0x50 + 3, (UINT8)~BIT5, BIT5}, |
| 141 | {MISC_BASE >> 8, 0x50 + 2, (UINT8)~BIT3, BIT3}, |
| 142 | //{SERIAL_DEBUG_BASE >> 8, FCH_SDB_REG74, 0, 0}, |
| 143 | {0xFF, 0xFF, 0xFF, 0xFF}, |
| 144 | }; |
| 145 | |
| 146 | /** |
| 147 | * FchHudson2InitEnvHwAcpiPciTable - PCI device registers initial |
| 148 | * during early POST. |
| 149 | * |
| 150 | */ |
| 151 | REG8_MASK FchHudson2InitEnvHwAcpiPciTable[] = |
| 152 | { |
| 153 | // |
| 154 | // SMBUS Device (Bus 0, Dev 20, Func 0) |
| 155 | // |
| 156 | {0x00, SMBUS_BUS_DEV_FUN, 0}, |
Subrata Banik | 8e6d5f2 | 2020-08-30 13:51:44 +0530 | [diff] [blame] | 157 | {FCH_CFG_REG10, 0x00, (FCH_VERSION & 0xFF)}, ///Program the version information |
| 158 | {FCH_CFG_REG11, 0x00, (FCH_VERSION >> 8)}, |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 159 | {0xFF, 0xFF, 0xFF}, |
| 160 | }; |
| 161 | |
| 162 | |
| 163 | /** |
| 164 | * ProgramPFchAcpiMmio - Config HwAcpi MMIO registers |
| 165 | * Acpi S3 resume won't execute this procedure (POST only) |
| 166 | * |
| 167 | * @param[in] FchDataPtr Fch configuration structure pointer. |
| 168 | * |
| 169 | */ |
| 170 | VOID |
| 171 | ProgramEnvPFchAcpiMmio ( |
| 172 | IN VOID *FchDataPtr |
| 173 | ) |
| 174 | { |
| 175 | FCH_DATA_BLOCK *LocalCfgPtr; |
| 176 | AMD_CONFIG_PARAMS *StdHeader; |
| 177 | |
| 178 | LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; |
| 179 | StdHeader = LocalCfgPtr->StdHeader; |
| 180 | |
| 181 | ProgramFchAcpiMmioTbl ((ACPI_REG_WRITE*) (&FchHudson2InitEnvHwAcpiMmioTable[0]), StdHeader); |
| 182 | } |
| 183 | |
| 184 | /** |
| 185 | * ProgramFchEnvHwAcpiPciReg - Config HwAcpi PCI controller |
| 186 | * before PCI emulation |
| 187 | * |
| 188 | * |
| 189 | * |
| 190 | * @param[in] FchDataPtr Fch configuration structure pointer. |
| 191 | * |
| 192 | */ |
| 193 | VOID |
| 194 | ProgramFchEnvHwAcpiPciReg ( |
| 195 | IN VOID *FchDataPtr |
| 196 | ) |
| 197 | { |
| 198 | FCH_DATA_BLOCK *LocalCfgPtr; |
| 199 | AMD_CONFIG_PARAMS *StdHeader; |
| 200 | |
| 201 | LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; |
| 202 | StdHeader = LocalCfgPtr->StdHeader; |
| 203 | |
| 204 | // |
| 205 | // FCH CFG programming |
| 206 | // |
| 207 | // Make BAR registers of smbus visible. |
| 208 | // |
| 209 | RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGC8 + 1, AccessWidth8, (UINT8)~BIT6, 0); |
| 210 | |
| 211 | // |
| 212 | //Early post initialization of pci config space |
| 213 | // |
Patrick Georgi | 6b688f5 | 2021-02-12 13:49:11 +0100 | [diff] [blame] | 214 | ProgramPciByteTable ((REG8_MASK*) (&FchHudson2InitEnvHwAcpiPciTable[0]), |
| 215 | ARRAY_SIZE(FchHudson2InitEnvHwAcpiPciTable), StdHeader); |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 216 | |
| 217 | if ( LocalCfgPtr->Smbus.SmbusSsid != 0 ) { |
| 218 | RwPci ((SMBUS_BUS_DEV_FUN << 16) + FCH_CFG_REG2C, AccessWidth32, 0x00, LocalCfgPtr->Smbus.SmbusSsid, StdHeader); |
| 219 | } |
| 220 | |
| 221 | // |
| 222 | //Make BAR registers of smbus invisible. |
| 223 | // |
| 224 | RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGC8 + 1, AccessWidth8, (UINT8)~BIT6, BIT6); |
| 225 | } |
| 226 | |
| 227 | /** |
| 228 | * FchVgaInit - Config VGA CODEC |
| 229 | * |
| 230 | * @param[in] VOID empty |
| 231 | * |
| 232 | */ |
| 233 | VOID |
| 234 | FchVgaInit ( |
| 235 | OUT VOID |
| 236 | ) |
| 237 | { |
| 238 | // |
| 239 | // Cobia_Nutmeg_DP-VGA Electrical SI validation_Lower RGB Luminance level BGADJ=0x1F & DACADJ=0x1B |
| 240 | // |
| 241 | RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGC4, AccessWidth8, 0xff, BIT5 ); |
| 242 | RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0xD8 , AccessWidth8, 0x00, 0x17 ); |
| 243 | RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0xD9 , AccessWidth8, 0x00, ((BGADJ << 2) + (((DACADJ & 0xf0) >> 4) & 0x3))); |
| 244 | RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0xD8 , AccessWidth8, 0x00, 0x16 ); |
| 245 | RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0xD9 , AccessWidth8, 0x0f, ((DACADJ & 0x0f) << 4)); |
| 246 | |
| 247 | *((UINT8*) ((UINTN)(PKT_DATA_REG + 0x00))) = (0x08 << 4) + (UINT8) ((EFUS_DAC_ADJUSTMENT_CONTROL >> 16) & 0xff); |
| 248 | *((UINT8*) ((UINTN)(PKT_DATA_REG + 0x01))) = (UINT8) ((EFUS_DAC_ADJUSTMENT_CONTROL >> 8) & 0xff); |
| 249 | *((UINT8*) ((UINTN)(PKT_DATA_REG + 0x02))) = (UINT8) ((EFUS_DAC_ADJUSTMENT_CONTROL >> 0) & 0xff); |
| 250 | *((UINT8*) ((UINTN)(PKT_DATA_REG + 0x03))) = (UINT8) (0x03); |
| 251 | *((UINT8*) ((UINTN)(PKT_DATA_REG + 0x04))) = (UINT8) (((EFUS_DAC_ADJUSTMENT_CONTROL_DATA) >> 0) & 0xff); |
| 252 | *((UINT8*) ((UINTN)(PKT_DATA_REG + 0x05))) = (UINT8) (((EFUS_DAC_ADJUSTMENT_CONTROL_DATA) >> 8) & 0xff); |
| 253 | *((UINT8*) ((UINTN)(PKT_DATA_REG + 0x06))) = (UINT8) (((EFUS_DAC_ADJUSTMENT_CONTROL_DATA) >> 16) & 0xff); |
| 254 | *((UINT8*) ((UINTN)(PKT_DATA_REG + 0x07))) = (UINT8) (((EFUS_DAC_ADJUSTMENT_CONTROL_DATA) >> 24) & 0xff); |
| 255 | *((UINT8*) ((UINTN)(PKT_LEN_REG))) = 0x08; |
| 256 | *((UINT8*) ((UINTN)(PKT_CTRL_REG))) = 0x01; |
| 257 | } |
| 258 | |
| 259 | /** |
| 260 | * ProgramSpecificFchInitEnvAcpiMmio - Config HwAcpi MMIO before |
| 261 | * PCI emulation |
| 262 | * |
| 263 | * |
| 264 | * |
| 265 | * @param[in] FchDataPtr Fch configuration structure pointer. |
| 266 | * |
| 267 | */ |
| 268 | VOID |
| 269 | ProgramSpecificFchInitEnvAcpiMmio ( |
| 270 | IN VOID *FchDataPtr |
| 271 | ) |
| 272 | { |
| 273 | CPUID_DATA CpuId; |
| 274 | FCH_DATA_BLOCK *LocalCfgPtr; |
| 275 | AMD_CONFIG_PARAMS *StdHeader; |
| 276 | |
| 277 | LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; |
| 278 | StdHeader = LocalCfgPtr->StdHeader; |
| 279 | // |
| 280 | // Set ASF SMBUS master function enabled here (temporary) |
| 281 | // |
| 282 | RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0x28 , AccessWidth16, (UINT32)~(BIT0 + BIT2), BIT0 + BIT2); |
| 283 | |
| 284 | #ifdef ACPI_SLEEP_TRAP |
| 285 | // |
| 286 | // Set SLP_TYPE as SMI event |
| 287 | // |
| 288 | RwMem (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REGB0, AccessWidth8, (UINT32)~(BIT2 + BIT3), BIT2); |
| 289 | |
| 290 | // |
| 291 | // Disabled SLP function for S1/S3/S4/S5 |
| 292 | // |
| 293 | RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGBE, AccessWidth8, (UINT32)~BIT5, 0x00); |
| 294 | |
| 295 | // |
| 296 | // Set S state transition disabled (BIT0) force ACPI to send SMI message when writing to SLP_TYP Acpi register. (BIT1) |
| 297 | // |
| 298 | RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG08 + 3, AccessWidth8, (UINT32)~(BIT0 + BIT1), BIT1); |
| 299 | |
| 300 | // |
| 301 | // Enabled Global Smi ( BIT7 clear as 0 to enable ) |
| 302 | // |
| 303 | RwMem (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REG98 + 3 , AccessWidth8, (UINT32)~BIT7, 0x00); |
| 304 | #endif |
| 305 | |
| 306 | // |
| 307 | // Set Stutter timer settings |
| 308 | // |
| 309 | LibAmdCpuidRead (AMD_CPUID_APICID_LPC_BID, &CpuId, StdHeader); |
| 310 | |
| 311 | RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG80 + 1, AccessWidth8, (UINT32)~(BIT3 + BIT4), BIT3 + BIT4); |
| 312 | |
| 313 | // |
| 314 | // Set LDTSTP# duration to 10us for Specific CPU, or when HT link is 200MHz |
| 315 | // |
| 316 | if ((LocalCfgPtr->HwAcpi.AnyHt200MhzLink) || ((CpuId.EAX_Reg & 0x00ff00f0) == 0x100080) || ((CpuId.EAX_Reg & 0x00ff00f0) == 0x100090) || ((CpuId.EAX_Reg & 0x00ff00f0) == 0x1000A0)) { |
| 317 | RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG94, AccessWidth8, 0, 0x0A); |
| 318 | RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG80 + 3, AccessWidth8, 0xFE, 0x28); |
| 319 | } else { |
| 320 | RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG94, AccessWidth8, 0, 0x01); |
| 321 | RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG80 + 3, AccessWidth8, 0xFE, 0x20); |
| 322 | } |
| 323 | |
| 324 | // |
| 325 | // SSC will provide better jitter margin |
| 326 | // |
| 327 | RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x13, AccessWidth8, 0xFC, 0x01); |
| 328 | // |
| 329 | // Ac Loss Control |
| 330 | // |
| 331 | AcLossControl ((UINT8) LocalCfgPtr->HwAcpi.PwrFailShadow); |
| 332 | // |
| 333 | //FCH VGA Init |
| 334 | // |
| 335 | FchVgaInit (); |
| 336 | |
| 337 | // |
| 338 | // 2.16 Enable DMAACTIVE |
| 339 | // |
| 340 | RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG7F, AccessWidth8, 0xFE, 0x01); |
| 341 | |
| 342 | // |
| 343 | // Set ACPIMMIO by OEM Input table |
| 344 | // |
| 345 | ProgramFchAcpiMmioTbl ((ACPI_REG_WRITE *) (LocalCfgPtr->HwAcpi.OemProgrammingTablePtr), StdHeader); |
| 346 | } |
| 347 | |
| 348 | /** |
| 349 | * ValidateFchVariant - Validate FCH Variant |
| 350 | * |
| 351 | * |
| 352 | * |
| 353 | * @param[in] FchDataPtr |
| 354 | * |
| 355 | */ |
| 356 | VOID |
| 357 | ValidateFchVariant ( |
| 358 | IN VOID *FchDataPtr |
| 359 | ) |
| 360 | { |
| 361 | UINT8 XhciEfuse; |
| 362 | UINT8 PcieEfuse; |
| 363 | FCH_DATA_BLOCK *LocalCfgPtr; |
| 364 | AMD_CONFIG_PARAMS *StdHeader; |
| 365 | |
| 366 | LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; |
| 367 | StdHeader = LocalCfgPtr->StdHeader; |
| 368 | |
| 369 | switch ( LocalCfgPtr->Misc.FchVariant ) { |
| 370 | case FCH_M3T: |
| 371 | //Disable Devices for M3T |
| 372 | LocalCfgPtr->Gec.GecEnable = 1; |
| 373 | LocalCfgPtr->Hwm.HwMonitorEnable = 0; |
| 374 | LocalCfgPtr->Sd.SdConfig = 0; |
| 375 | LocalCfgPtr->Ir.IrConfig = 0; |
| 376 | break; |
| 377 | |
| 378 | default: |
| 379 | break; |
| 380 | } |
| 381 | |
| 382 | // add Efuse checking for Xhci enable/disable |
| 383 | XhciEfuse = XHCI_EFUSE_LOCATION; |
| 384 | GetEfuseStatus (&XhciEfuse, StdHeader); |
| 385 | if ((XhciEfuse & (BIT0 + BIT1)) == (BIT0 + BIT1)) { |
| 386 | LocalCfgPtr->Usb.Xhci0Enable = 0; |
| 387 | LocalCfgPtr->Usb.Xhci1Enable = 0; |
| 388 | } |
| 389 | |
| 390 | // add Efuse checking for PCIE Gen2 enable |
| 391 | PcieEfuse = PCIE_FORCE_GEN1_EFUSE_LOCATION; |
| 392 | GetEfuseStatus (&PcieEfuse, StdHeader); |
| 393 | if ( PcieEfuse & BIT0 ) { |
| 394 | LocalCfgPtr->Gpp.GppGen2 = 0; |
| 395 | } |
| 396 | } |
| 397 | |
| 398 | /** |
| 399 | * IsExternalClockMode - Is External Clock Mode? |
| 400 | * |
| 401 | * |
| 402 | * @retval TRUE or FALSE |
| 403 | * |
| 404 | */ |
| 405 | BOOLEAN |
| 406 | IsExternalClockMode ( |
| 407 | IN VOID *FchDataPtr |
| 408 | ) |
| 409 | { |
| 410 | UINT8 MISC80; |
| 411 | ReadMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG80, AccessWidth8, &MISC80); |
| 412 | return ( (BOOLEAN) ((MISC80 & BIT4) == 0) ); |
| 413 | } |
| 414 | |
| 415 | |
| 416 | /** |
| 417 | * ProgramFchEnvSpreadSpectrum - Config SpreadSpectrum before |
| 418 | * PCI emulation |
| 419 | * |
| 420 | * |
| 421 | * |
| 422 | * @param[in] FchDataPtr Fch configuration structure pointer. |
| 423 | * |
| 424 | */ |
| 425 | VOID |
| 426 | ProgramFchEnvSpreadSpectrum ( |
| 427 | IN VOID *FchDataPtr |
| 428 | ) |
| 429 | { |
| 430 | UINT8 PortStatus; |
| 431 | UINT8 FchSpreadSpectrum; |
| 432 | |
| 433 | FCH_DATA_BLOCK *LocalCfgPtr; |
| 434 | AMD_CONFIG_PARAMS *StdHeader; |
| 435 | |
| 436 | LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; |
| 437 | StdHeader = LocalCfgPtr->StdHeader; |
| 438 | |
| 439 | FchSpreadSpectrum = LocalCfgPtr->HwAcpi.SpreadSpectrum; |
| 440 | |
| 441 | if ((FchSpreadSpectrum > 0) && !(IsExternalClockMode (FchDataPtr))) { |
| 442 | RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x40, AccessWidth32, (UINT32) (~(0x1 << 25)), (0x1 << 25)); |
| 443 | RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x08, AccessWidth32, (UINT32) (~(0x1 << 0)), (0x0 << 0)); |
| 444 | RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x18, AccessWidth32, (UINT32) (~(0x7FF << 5)), (0x318 << 5)); |
| 445 | RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x18, AccessWidth32, (UINT32) (~(0xF << 16)), (0x0 << 16)); |
| 446 | RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x10, AccessWidth32, (UINT32) (~(0xFFFF << 8)), (0x6F83 << 8)); |
| 447 | RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x10, AccessWidth32, (UINT32) (~(0xFF << 0)), (0x90 << 0)); |
| 448 | RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x1C, AccessWidth32, (UINT32) (~(0x3F << 0)), (0x0 << 0)); |
| 449 | RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x08, AccessWidth32, (UINT32) (~(0xF << 28)), (0x7 << 28)); |
| 450 | RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x08, AccessWidth32, (UINT32) (~(0x1 << 7)), (0x0 << 8)); |
| 451 | RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x08, AccessWidth32, (UINT32) (~(0x1 << 8)), (0x1 << 8)); |
| 452 | RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x10, AccessWidth32, (UINT32) (~(0x3 << 24)), (0x1 << 24)); |
| 453 | |
| 454 | RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG08, AccessWidth8, 0xFE, 0x01); |
| 455 | } else { |
| 456 | RwMem (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG08, AccessWidth8, 0xFE, 0x00); |
| 457 | } |
| 458 | |
| 459 | // |
| 460 | // PLL 100Mhz Reference Clock Buffer setting for internal clock generator mode (BIT5) |
| 461 | // OSC Clock setting for internal clock generator mode (BIT6) |
| 462 | // |
| 463 | GetChipSysMode (&PortStatus, StdHeader); |
| 464 | if ( ((PortStatus & ChipSysIntClkGen) == ChipSysIntClkGen) ) { |
| 465 | RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x04 + 1, AccessWidth8, (UINT32)~(BIT5 + BIT6), BIT5 + BIT6); |
| 466 | } |
| 467 | } |
| 468 | |
| 469 | /** |
| 470 | * TurnOffCG2 |
| 471 | * |
| 472 | * |
| 473 | * @retval VOID |
| 474 | * |
| 475 | */ |
| 476 | VOID |
| 477 | TurnOffCG2 ( |
| 478 | OUT VOID |
| 479 | ) |
| 480 | { |
| 481 | RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x40, AccessWidth8, (UINT32)~BIT6, 0); |
| 482 | RwMem (ACPI_MMIO_BASE + PMIO_BASE + 0xDA , AccessWidth8, 0x0F, 0xA0); |
| 483 | RwMem (ACPI_MMIO_BASE + IOMUX_BASE + 0x41, AccessWidth8, (UINT32)~(BIT1 + BIT0), (BIT1 + BIT0)); |
| 484 | RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x41, AccessWidth8, (UINT32)~( BIT4), (BIT4)); |
| 485 | RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x41, AccessWidth8, (UINT32)~(BIT6), (BIT6)); |
| 486 | RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x08, AccessWidth8, (UINT32)~BIT6, BIT6); |
| 487 | RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x1C, AccessWidth8, (UINT32)~BIT6, BIT6); |
| 488 | } |
| 489 | |
| 490 | /** |
| 491 | * BackUpCG2 |
| 492 | * |
| 493 | * |
| 494 | * @retval VOID |
| 495 | * |
| 496 | */ |
| 497 | VOID |
| 498 | BackUpCG2 ( |
| 499 | OUT VOID |
| 500 | ) |
| 501 | { |
| 502 | UINT8 Byte; |
| 503 | ReadMem (ACPI_MMIO_BASE + MISC_BASE + 0x1C, AccessWidth8, &Byte); |
| 504 | if (Byte & BIT6) { |
| 505 | RwMem (ACPI_MMIO_BASE + MISC_BASE + 0x41, AccessWidth8, (UINT32)~(BIT6), (0)); |
| 506 | } |
| 507 | } |
| 508 | |
| 509 | /** |
| 510 | * HpetInit - Program Fch HPET function |
| 511 | * |
| 512 | * |
| 513 | * |
| 514 | * @param[in] FchDataPtr Fch configuration structure pointer. |
| 515 | * |
| 516 | */ |
| 517 | VOID |
| 518 | HpetInit ( |
| 519 | IN VOID *FchDataPtr |
| 520 | ) |
| 521 | { |
| 522 | DESCRIPTION_HEADER *HpetTable; |
| 523 | UINT8 FchHpetTimer; |
| 524 | UINT8 FchHpetMsiDis; |
| 525 | FCH_DATA_BLOCK *LocalCfgPtr; |
| 526 | |
| 527 | LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; |
| 528 | FchHpetTimer = (UINT8) LocalCfgPtr->Hpet.HpetEnable; |
| 529 | FchHpetMsiDis = (UINT8) LocalCfgPtr->Hpet.HpetMsiDis; |
| 530 | |
| 531 | HpetTable = NULL; |
| 532 | if ( FchHpetTimer == TRUE ) { |
| 533 | // |
| 534 | //Program the HPET BAR address |
| 535 | // |
| 536 | RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG50, AccessWidth32, FCH_HPET_REG_MASK, LocalCfgPtr->Hpet.HpetBase); |
| 537 | |
| 538 | // |
| 539 | //Enabling decoding of HPET MMIO |
| 540 | //Enable HPET MSI support |
| 541 | //Enable High Precision Event Timer (also called Multimedia Timer) interrupt |
| 542 | // |
| 543 | if ( FchHpetMsiDis == FALSE ) { |
| 544 | RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG50, AccessWidth32, FCH_HPET_REG_MASK, BIT0 + BIT1 + BIT2 + BIT3 + BIT4); |
| 545 | #ifdef FCH_TIMER_TICK_INTERVAL_WA |
| 546 | RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG50, AccessWidth32, FCH_HPET_REG_MASK, BIT0 + BIT1); |
| 547 | #endif |
| 548 | } else { |
| 549 | RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG50, AccessWidth32, FCH_HPET_REG_MASK, BIT0 + BIT1); |
| 550 | } |
| 551 | |
| 552 | } else { |
| 553 | if ( ! (LocalCfgPtr->Misc.S3Resume) ) { |
| 554 | HpetTable = (DESCRIPTION_HEADER*) AcpiLocateTable (Int32FromChar('H','P','E','T')); /* 'TEPH' */ |
| 555 | } |
| 556 | if ( HpetTable != NULL ) { |
| 557 | HpetTable->Signature = Int32FromChar('T','E','P','H'); /* 'HPET' */ |
| 558 | } |
| 559 | } |
| 560 | } |