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review.coreboot.org / coreboot / 9a458e4e58edbfc154dce007961514b5c31cf7aa / . / src / vendorcode / amd / agesa / f15tn / Proc / Fch / Common / FchDef.h
blob: 7967b1dc4b50c0bb988a795e9572ce24ad70dca5 [file] [log] [blame]
zbao7d94cf92012-07-02 14:19:14 +0800[diff] [blame]1/* $NoKeywords:$ */
2/**
3 * @file
4 *
5 * FCH routine definition
6 *
7 *
8 *
9 * @xrefitem bom "File Content Label" "Release Content"
10 * @e project: AGESA
11 * @e sub-project: FCH
12 * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
13 *
14 */
15/*
16*****************************************************************************
17*
Siyuan Wang641f00c2013-06-08 11:50:55 +0800[diff] [blame]18 * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
19 * All rights reserved.
20 *
21 * Redistribution and use in source and binary forms, with or without
22 * modification, are permitted provided that the following conditions are met:
23 * * Redistributions of source code must retain the above copyright
24 * notice, this list of conditions and the following disclaimer.
25 * * Redistributions in binary form must reproduce the above copyright
26 * notice, this list of conditions and the following disclaimer in the
27 * documentation and/or other materials provided with the distribution.
28 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
29 * its contributors may be used to endorse or promote products derived
30 * from this software without specific prior written permission.
31 *
32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
34 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
36 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
37 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
38 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
39 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
41 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
zbao7d94cf92012-07-02 14:19:14 +0800[diff] [blame]42****************************************************************************
43*/
44#ifndef _FCH_DEF_H_
45#define _FCH_DEF_H_
46
47
48UINT32 ReadAlink (IN UINT32 Index, IN AMD_CONFIG_PARAMS *StdHeader);
49VOID WriteAlink (IN UINT32 Index, IN UINT32 Data, IN AMD_CONFIG_PARAMS *StdHeader);
50VOID RwAlink (IN UINT32 Index, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
51VOID ReadMem (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *ValuePtr);
52VOID WriteMem (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *ValuePtr);
53VOID RwMem (IN UINT32 Address, IN UINT8 OpFlag, IN UINT32 Mask, IN UINT32 Data);
54VOID ReadPci (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
Arthur Heymans8d3640d2022-05-16 12:27:36 +0200[diff] [blame]55VOID WritePci (IN UINT32 Address, IN UINT8 OpFlag, CONST IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
zbao7d94cf92012-07-02 14:19:14 +0800[diff] [blame]56VOID RwPci (IN UINT32 Address, IN UINT8 OpFlag, IN UINT32 Mask, IN UINT32 Data, IN AMD_CONFIG_PARAMS *StdHeader);
57VOID ProgramPciByteTable (IN REG8_MASK* pPciByteTable, IN UINT16 dwTableSize, IN AMD_CONFIG_PARAMS *StdHeader);
58VOID ProgramFchAcpiMmioTbl (IN ACPI_REG_WRITE *pAcpiTbl, IN AMD_CONFIG_PARAMS *StdHeader);
Arthur Heymans8d3640d2022-05-16 12:27:36 +0200[diff] [blame]59VOID ProgramFchSciMapTbl (CONST IN SCI_MAP_CONTROL *pSciMapTbl, IN FCH_RESET_DATA_BLOCK *FchResetDataBlock);
60VOID ProgramFchGpioTbl (CONST IN GPIO_CONTROL *pGpioTbl, IN FCH_RESET_DATA_BLOCK *FchResetDataBlock);
zbao7d94cf92012-07-02 14:19:14 +0800[diff] [blame]61VOID ProgramFchSataPhyTbl (IN SATA_PHY_CONTROL *pSataPhyTbl, IN FCH_RESET_DATA_BLOCK *FchResetDataBlock);
62VOID GetChipSysMode (IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
63BOOLEAN IsImcEnabled (IN AMD_CONFIG_PARAMS *StdHeader);
64VOID ReadPmio (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
65VOID WritePmio (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
66VOID RwPmio (IN UINT8 Address, IN UINT8 OpFlag, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
67VOID ReadPmio2 (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
68VOID WritePmio2 (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
69VOID RwPmio2 (IN UINT8 Address, IN UINT8 OpFlag, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
70VOID ReadBiosram (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
71VOID WriteBiosram (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
72VOID GetFchAcpiMmioBase (OUT UINT32 *AcpiMmioBase, IN AMD_CONFIG_PARAMS *StdHeader);
73VOID GetFchAcpiPmBase (OUT UINT16 *AcpiPmBase, IN AMD_CONFIG_PARAMS *StdHeader);
74UINT8 ReadFchSleepType (IN AMD_CONFIG_PARAMS *StdHeader);
75
76///
77/// Fch Ab Routines
78///
79/// Pei Phase
80///
81VOID FchInitResetAb (IN VOID* FchDataPtr);
82VOID FchProgramAbPowerOnReset (IN VOID* FchDataPtr);
83///
84/// Dxe Phase
85///
86VOID FchInitEnvAb (IN VOID* FchDataPtr);
87VOID FchInitEnvAbSpecial (IN VOID* FchDataPtr);
88VOID FchInitMidAb (IN VOID* FchDataPtr);
89VOID FchInitLateAb (IN VOID* FchDataPtr);
90///
91/// Other Public Routines
92///
93VOID FchInitEnvAbLinkInit (IN VOID* FchDataPtr);
94BOOLEAN IsUmiOneLaneGen1Mode (IN AMD_CONFIG_PARAMS *StdHeader);
95VOID FchAbLateProgram (IN VOID* FchDataPtr);
96
97///
98/// Fch Pcie Routines
99///
100/// Pei Phase
101///
102VOID FchInitResetPcie (IN VOID* FchDataPtr);
103///
104/// Dxe Phase
105///
106VOID FchInitEnvPcie (IN VOID* FchDataPtr);
107VOID FchInitMidPcie (IN VOID* FchDataPtr);
108VOID FchInitLatePcie (IN VOID* FchDataPtr);
109VOID ProgramPcieNativeMode (IN VOID* FchDataPtr);
110
111///
112/// Fch Gpp Routines
113///
114/// Pei Phase
115///
116VOID FchInitResetGpp (IN VOID* FchDataPtr);
117VOID ProgramFchGppInitReset (IN FCH_GPP *FchGpp, IN AMD_CONFIG_PARAMS *StdHeader);
118VOID FchResetPcie (IN RESET_BLOCK ResetBlock, IN RESET_OP ResetOp, IN AMD_CONFIG_PARAMS *StdHeader);
119
120///
121/// Dxe Phase
122///
123VOID FchInitEnvGpp (IN VOID* FchDataPtr);
124VOID FchInitMidGpp (IN VOID* FchDataPtr);
125VOID FchInitLateGpp (IN VOID* FchDataPtr);
126
127///
128/// Common Gpp Routines
129///
130VOID ProgramGppTogglePcieReset (IN BOOLEAN DoToggling, IN AMD_CONFIG_PARAMS *StdHeader);
131VOID FchGppForceGen1 (IN FCH_GPP *FchGpp, IN CONST UINT8 ActivePorts, IN AMD_CONFIG_PARAMS *StdHeader);
132VOID FchGppForceGen2 (IN FCH_GPP *FchGpp, IN CONST UINT8 ActivePorts, IN AMD_CONFIG_PARAMS *StdHeader);
133VOID FchGppDynamicPowerSaving (IN FCH_GPP *FchGpp, IN AMD_CONFIG_PARAMS *StdHeader);
134UINT8 GppPortPollingLtssm (IN FCH_GPP *FchGpp, IN UINT8 ActivePorts, IN BOOLEAN IsGen2, IN AMD_CONFIG_PARAMS *StdHeader);
135VOID GppGen2Workaround (IN FCH_GPP *FchGpp, IN AMD_CONFIG_PARAMS *StdHeader);
136UINT8 FchFindPciCap (IN UINT32 PciAddress, IN UINT8 TargetCapId, IN AMD_CONFIG_PARAMS *StdHeader);
137VOID FchGppPortInit (IN FCH_GPP *FchGpp, IN AMD_CONFIG_PARAMS *StdHeader);
138VOID FchGppPortInitPhaseII (IN FCH_GPP *FchGpp, IN AMD_CONFIG_PARAMS *StdHeader);
139VOID FchGppPortInitS3Phase (IN FCH_GPP *FchGpp, IN AMD_CONFIG_PARAMS *StdHeader);
140UINT32 GppGetFchTempBus (IN AMD_CONFIG_PARAMS *StdHeader);
141
142///
143///
144/// Pei Phase
145///
zbao7598bea2012-08-09 15:08:20 +0800[diff] [blame]146VOID FchInitResetAzalia (IN VOID *FchDataPtr);
zbao7d94cf92012-07-02 14:19:14 +0800[diff] [blame]147///
148/// Dxe Phase
149///
zbao7598bea2012-08-09 15:08:20 +0800[diff] [blame]150VOID FchInitEnvAzalia (IN VOID *FchDataPtr);
151VOID FchInitMidAzalia (IN VOID *FchDataPtr);
152VOID FchInitLateAzalia (IN VOID *FchDataPtr);
zbao7d94cf92012-07-02 14:19:14 +0800[diff] [blame]153
154
155///
156/// Fch GEC Routines
157///
158/// Pei Phase
159///
160VOID FchInitResetGec (IN VOID* FchDataPtr);
161///
162/// Dxe Phase
163///
164VOID FchInitEnvGec (IN VOID* FchDataPtr);
165VOID FchInitMidGec (IN VOID* FchDataPtr);
166VOID FchInitLateGec (IN VOID* FchDataPtr);
167///
168/// Other Public Routines
169///
170VOID FchInitGecController (IN VOID* FchDataPtr);
171VOID FchSwInitGecBootRom (IN VOID* FchDataPtr);
172
173///
174/// Fch HwAcpi Routines
175///
176/// Pei Phase
177///
178VOID FchInitResetHwAcpiP (IN VOID *FchDataPtr);
179VOID FchInitResetHwAcpi (IN VOID *FchDataPtr);
180VOID ProgramFchHwAcpiResetP (IN VOID *FchDataPtr);
181///
182/// Dxe Phase
183///
184VOID FchInitEnvHwAcpiP (IN VOID *FchDataPtr);
185VOID FchInitEnvHwAcpi (IN VOID *FchDataPtr);
186VOID ProgramEnvPFchAcpiMmio (IN VOID *FchDataPtr);
187VOID ProgramFchEnvHwAcpiPciReg (IN VOID *FchDataPtr);
188VOID ProgramSpecificFchInitEnvAcpiMmio (IN VOID *FchDataPtr);
189VOID ProgramFchEnvSpreadSpectrum (IN VOID *FchDataPtr);
190VOID FchInitMidHwAcpi (IN VOID *FchDataPtr);
191VOID FchInitLateHwAcpi (IN VOID *FchDataPtr);
192
193///
194/// Other Public Routines
195///
196VOID HpetInit (IN VOID *FchDataPtr);
197VOID C3PopupSetting (IN VOID *FchDataPtr);
198VOID MtC1eEnable (IN VOID *FchDataPtr);
199VOID GcpuRelatedSetting (IN VOID *FchDataPtr);
200VOID StressResetModeLate (IN VOID *FchDataPtr);
201
202///
203/// Fch Hwm Routines
204///
205/// Pei Phase
206///
207VOID FchInitResetHwm (IN VOID* FchDataPtr);
208///
209/// Dxe Phase
210///
211VOID FchInitEnvHwm (IN VOID* FchDataPtr);
212VOID FchInitMidHwm (IN VOID* FchDataPtr);
213VOID FchInitLateHwm (IN VOID* FchDataPtr);
214///
215/// Other Public Routines
216///
217VOID HwmInitRegister (IN VOID* FchDataPtr);
218VOID HwmProcessParameter (IN VOID* FchDataPtr);
219VOID HwmSetRegister (IN VOID* FchDataPtr);
220VOID HwmGetCalibrationFactor (IN VOID* FchDataPtr);
221VOID HwmFchtsiAutoPolling (IN VOID* FchDataPtr);
222VOID HwmGetRawData (IN VOID* FchDataPtr);
223VOID HwmCaculate (IN VOID* FchDataPtr);
224VOID HwmFchtsiAutoPollingOff (IN VOID* FchDataPtr);
225VOID FchECfancontrolservice (IN VOID* FchDataPtr);
226
227
228///
229/// Fch Ide Routines
230///
231VOID FchInitEnvIde (IN VOID* FchDataPtr);
232VOID FchInitMidIde (IN VOID* FchDataPtr);
233VOID FchInitLateIde (IN VOID* FchDataPtr);
234
235
236///
237/// Fch Imc Routines
238///
239/// Pei Phase
240///
241VOID FchInitResetImc (IN VOID *FchDataPtr);
242VOID FchInitResetEc (IN VOID *FchDataPtr);
243///
244/// Dxe Phase
245///
246VOID FchInitEnvImc (IN VOID *FchDataPtr);
247VOID FchInitMidImc (IN VOID *FchDataPtr);
248VOID FchInitLateImc (IN VOID *FchDataPtr);
249VOID FchInitEnvEc (IN VOID *FchDataPtr);
250VOID FchInitMidEc (IN VOID *FchDataPtr);
251VOID FchInitLateEc (IN VOID *FchDataPtr);
252///
253/// Other Public Routines
254///
255VOID EnterEcConfig (IN AMD_CONFIG_PARAMS *StdHeader);
256VOID ExitEcConfig (IN AMD_CONFIG_PARAMS *StdHeader);
257VOID ReadEc8 (IN UINT8 Address, IN UINT8* Value, IN AMD_CONFIG_PARAMS *StdHeader);
258VOID WriteEc8 (IN UINT8 Address, IN UINT8* Value, IN AMD_CONFIG_PARAMS *StdHeader);
259VOID RwEc8 (IN UINT8 Address, IN UINT8 AndMask, IN UINT8 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
260VOID WriteECmsg (IN UINT8 Address, IN UINT8 OpFlag, IN VOID* Value, IN AMD_CONFIG_PARAMS *StdHeader);
261VOID ReadECmsg (IN UINT8 Address, IN UINT8 OpFlag, OUT VOID* Value, IN AMD_CONFIG_PARAMS *StdHeader);
262VOID WaitForEcLDN9MailboxCmdAck (IN AMD_CONFIG_PARAMS *StdHeader);
263
264VOID ImcSleep (IN VOID *FchDataPtr);
265VOID ImcEnableSurebootTimer (IN VOID *FchDataPtr);
266VOID ImcDisarmSurebootTimer (IN VOID *FchDataPtr);
267VOID ImcDisableSurebootTimer (IN VOID *FchDataPtr);
268VOID ImcWakeup (IN VOID *FchDataPtr);
269VOID ImcIdle (IN VOID *FchDataPtr);
270BOOLEAN ValidateImcFirmware (IN VOID *FchDataPtr);
271VOID SoftwareToggleImcStrapping (IN VOID *FchDataPtr);
272
273
274///
275/// Fch Ir Routines
276///
277/// Dxe Phase
278///
279VOID FchInitEnvIr (IN VOID* FchDataPtr);
280VOID FchInitMidIr (IN VOID* FchDataPtr);
281VOID FchInitLateIr (IN VOID* FchDataPtr);
282
283///
284/// Fch Pcib Routines
285///
286/// Pei Phase
287///
288VOID FchInitResetPcib (IN VOID* FchDataPtr);
289VOID FchInitResetPcibPort80Enable (IN VOID* FchDataPtr);
290
291///
292/// Dxe Phase
293///
294VOID FchInitEnvPcib (IN VOID* FchDataPtr);
295VOID FchInitMidPcib (IN VOID* FchDataPtr);
296VOID FchInitLatePcib (IN VOID* FchDataPtr);
297
298
299///
300/// Fch SATA Routines
301///
302/// Pei Phase
303///
304VOID FchInitResetSata (IN VOID *FchDataPtr);
305VOID FchInitResetSataProgram (IN VOID *FchDataPtr);
306///
307/// Dxe Phase
308///
309VOID FchInitMidSata (IN VOID *FchDataPtr);
310VOID FchInitEnvSata (IN VOID *FchDataPtr);
311VOID FchInitEnvProgramSataPciRegs (IN VOID *FchDataPtr);
312VOID FchInitMidProgramSataRegs (IN VOID *FchDataPtr);
313VOID FchInitLateProgramSataRegs (IN VOID *FchDataPtr);
314
315VOID FchInitLateSata (IN VOID *FchDataPtr);
316VOID FchInitEnvSataIde (IN VOID *FchDataPtr);
317VOID FchInitMidSataIde (IN VOID *FchDataPtr);
318VOID FchInitLateSataIde (IN VOID *FchDataPtr);
319VOID FchInitEnvSataAhci (IN VOID *FchDataPtr);
320VOID FchInitMidSataAhci (IN VOID *FchDataPtr);
321VOID FchInitLateSataAhci (IN VOID *FchDataPtr);
322VOID FchInitEnvSataRaid (IN VOID *FchDataPtr);
323VOID FchInitMidSataRaid (IN VOID *FchDataPtr);
324VOID FchInitLateSataRaid (IN VOID *FchDataPtr);
325VOID FchInitEnvSataIde2Ahci (IN VOID *FchDataPtr);
326VOID FchInitMidSataIde2Ahci (IN VOID *FchDataPtr);
327VOID FchInitLateSataIde2Ahci (IN VOID *FchDataPtr);
328
329VOID SataAhciSetDeviceNumMsi (IN VOID *FchDataPtr);
330VOID SataRaidSetDeviceNumMsi (IN VOID *FchDataPtr);
331VOID SataIde2AhciSetDeviceNumMsi (IN VOID *FchDataPtr);
332VOID SataSetIrqIntResource (IN VOID *FchDataPtr, IN AMD_CONFIG_PARAMS *StdHeader);
333VOID SataBar5setting (IN VOID *FchDataPtr, IN UINT32 *Bar5Ptr);
334VOID SataEnableWriteAccess (IN AMD_CONFIG_PARAMS *StdHeader);
335VOID SataDisableWriteAccess (IN AMD_CONFIG_PARAMS *StdHeader);
336VOID SataSetDeviceNumMsi (IN VOID *FchDataPtr);
337VOID FchSataSetDeviceNumMsi (IN VOID *FchDataPtr);
338VOID ShutdownUnconnectedSataPortClock (IN VOID *FchDataPtr, IN UINT32 Bar5);
339VOID FchShutdownUnconnectedSataPortClock (IN VOID *FchDataPtr, IN UINT32 Bar5);
340VOID SataDriveDetection (IN VOID *FchDataPtr, IN UINT32 *Bar5Ptr);
341VOID FchSataDriveDetection (IN VOID *FchDataPtr, IN UINT32 *Bar5Ptr);
342VOID FchSataGpioInitial (IN VOID *FchDataPtr);
343VOID SataBar5RegSet (IN VOID *FchDataPtr);
344VOID SataSetPortGenMode (IN VOID *FchDataPtr);
345VOID FchSataSetPortGenMode (IN VOID *FchDataPtr);
346VOID FchProgramSataPhy (IN AMD_CONFIG_PARAMS *StdHeader);
347VOID FchSataDriveFpga (IN VOID *FchDataPtr);
348VOID FchInitEnvSataRaidProgram (IN VOID *FchDataPtr);
349
350///
351/// FCH USB Controller Public Function
352///
353/// Pei Phase
354///
355VOID FchInitResetUsb (IN VOID *FchDataPtr);
356VOID FchInitResetOhci (IN VOID *FchDataPtr);
357VOID FchInitResetEhci (IN VOID *FchDataPtr);
358VOID FchInitResetXhci (IN VOID *FchDataPtr);
359VOID FchInitResetXhciProgram (IN VOID *FchDataPtr);
360///
361/// Dxe Phase
362///
363VOID FchInitEnvUsb (IN VOID *FchDataPtr);
364VOID FchInitMidUsb (IN VOID *FchDataPtr);
365VOID FchInitLateUsb (IN VOID *FchDataPtr);
366VOID FchInitEnvUsbOhci (IN VOID *FchDataPtr);
367VOID FchInitMidUsbOhci (IN VOID *FchDataPtr);
368VOID FchInitLateUsbOhci (IN VOID *FchDataPtr);
369VOID FchInitEnvUsbEhci (IN VOID *FchDataPtr);
370VOID FchInitMidUsbEhci (IN VOID *FchDataPtr);
371VOID FchInitLateUsbEhci (IN VOID *FchDataPtr);
372VOID FchInitEnvUsbXhci (IN VOID *FchDataPtr);
373VOID FchInitMidUsbXhci (IN VOID *FchDataPtr);
374VOID FchInitLateUsbXhci (IN VOID *FchDataPtr);
375VOID FchInitMidUsbOhci1 (IN VOID *FchDataPtr);
376VOID FchInitMidUsbOhci2 (IN VOID *FchDataPtr);
377VOID FchInitMidUsbOhci3 (IN VOID *FchDataPtr);
378VOID FchInitMidUsbOhci4 (IN VOID *FchDataPtr);
379VOID FchInitMidUsbEhci1 (IN FCH_DATA_BLOCK *FchDataPtr);
380VOID FchInitMidUsbEhci2 (IN FCH_DATA_BLOCK *FchDataPtr);
381VOID FchInitMidUsbEhci3 (IN FCH_DATA_BLOCK *FchDataPtr);
382///
383/// Other Public Routines
384///
385VOID FchSetUsbEnableReg (IN FCH_DATA_BLOCK *FchDataPtr);
386VOID FchOhciInitAfterPciInit (IN UINT32 Value, IN FCH_DATA_BLOCK* FchDataPtr);
387VOID FchEhciInitAfterPciInit (IN UINT32 Value, IN FCH_DATA_BLOCK* FchDataPtr);
388VOID FchXhciInitBeforePciInit (IN FCH_DATA_BLOCK* FchDataPtr);
389VOID FchXhciInitIndirectReg (IN AMD_CONFIG_PARAMS *StdHeader);
390VOID FchInitLateUsbXhciProgram (IN VOID *FchDataPtr);
391VOID FchXhciPowerSavingProgram (IN FCH_DATA_BLOCK* FchDataPtr);
392
393
394
395///
396/// Fch Sd Routines
397///
398VOID FchInitEnvSd (IN VOID *FchDataPtr);
399VOID FchInitMidSd (IN VOID *FchDataPtr);
400VOID FchInitLateSd (IN VOID *FchDataPtr);
401
402///
403/// Other Public Routines
404///
405
406VOID FchInitEnvSdProgram (IN VOID *FchDataPtr);
407
408///
409/// Fch Spi Routines
410///
411/// Pei Phase
412///
413VOID FchInitResetSpi (IN VOID *FchDataPtr);
414VOID FchInitResetLpc (IN VOID *FchDataPtr);
415VOID FchInitResetLpcProgram (IN VOID *FchDataPtr);
416///
417/// Dxe Phase
418///
419VOID FchInitEnvSpi (IN VOID *FchDataPtr);
420VOID FchInitMidSpi (IN VOID *FchDataPtr);
421VOID FchInitLateSpi (IN VOID *FchDataPtr);
422VOID FchInitEnvLpc (IN VOID *FchDataPtr);
423VOID FchInitMidLpc (IN VOID *FchDataPtr);
424VOID FchInitLateLpc (IN VOID *FchDataPtr);
425VOID FchInitEnvLpcProgram (IN VOID *FchDataPtr);
426///
427/// Other Public Routines
428///
429VOID FchSpiUnlock (IN VOID *FchDataPtr);
430VOID FchSpiLock (IN VOID *FchDataPtr);
431
432/*--------------------------- Documentation Pages ---------------------------*/
433VOID FchStall (IN UINT32 uSec, IN AMD_CONFIG_PARAMS *StdHeader);
434VOID CimFchStall (IN UINT32 uSec, IN AMD_CONFIG_PARAMS *StdHeader);
435VOID FchPciReset (IN AMD_CONFIG_PARAMS *StdHeader);
436VOID OutPort80 (IN UINT32 pcode, IN AMD_CONFIG_PARAMS *StdHeader);
437VOID OutPort1080 (IN UINT32 pcode, IN AMD_CONFIG_PARAMS *StdHeader);
438VOID GetEfuseStatus (IN VOID* Value, IN AMD_CONFIG_PARAMS *StdHeader);
439VOID TurnOffCG2 (OUT VOID);
440VOID BackUpCG2 (OUT VOID);
441VOID FchCopyMem (IN VOID* pDest, IN VOID* pSource, IN UINTN Length);
442VOID* GetRomSigPtr (IN UINTN* RomSigPtr, IN AMD_CONFIG_PARAMS *StdHeader);
443VOID RwXhciIndReg (IN UINT32 Index, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
444VOID RwXhci0IndReg (IN UINT32 Index, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
445VOID RwXhci1IndReg (IN UINT32 Index, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
446VOID AcLossControl (IN UINT8 AcLossControlValue);
447VOID FchVgaInit (OUT VOID);
448VOID RecordFchConfigPtr (IN UINT32 FchConfigPtr);
449VOID ValidateFchVariant (IN VOID *FchDataPtr);
450VOID RecordSmiStatus (IN AMD_CONFIG_PARAMS *StdHeader);
451BOOLEAN IsGCPU (IN VOID *FchDataPtr);
452BOOLEAN IsExternalClockMode (IN VOID *FchDataPtr);
453BOOLEAN IsLpcRom (OUT VOID);
454VOID SbSleepTrapControl (IN BOOLEAN SleepTrap);
455
456#endif