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zbao7d94cf92012-07-02 14:19:14 +08001/* $NoKeywords:$ */
2/**
3 * @file
4 *
5 * Various PCI service routines.
6 *
7 *
8 *
9 * @xrefitem bom "File Content Label" "Release Content"
10 * @e project: AGESA
11 * @e sub-project: GNB
12 * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
13 *
14 */
15/*
16*****************************************************************************
17*
Siyuan Wang641f00c2013-06-08 11:50:55 +080018 * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
19 * All rights reserved.
20 *
21 * Redistribution and use in source and binary forms, with or without
22 * modification, are permitted provided that the following conditions are met:
23 * * Redistributions of source code must retain the above copyright
24 * notice, this list of conditions and the following disclaimer.
25 * * Redistributions in binary form must reproduce the above copyright
26 * notice, this list of conditions and the following disclaimer in the
27 * documentation and/or other materials provided with the distribution.
28 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
29 * its contributors may be used to endorse or promote products derived
30 * from this software without specific prior written permission.
31 *
32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
34 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
36 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
37 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
38 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
39 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
41 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
zbao7d94cf92012-07-02 14:19:14 +080042* ***************************************************************************
43*
44*/
45
46#ifndef _S3SAVESTATE_H_
47#define _S3SAVESTATE_H_
48
49#pragma pack (push, 1)
50
51#ifndef S3_SCRIPT_DEBUG_CODE
52 #define S3_SCRIPT_DEBUG_CODE(Code) Code
53#endif
54
55/// Dispatch function ID repository
56typedef enum {
57 NbSmuIndirectWriteS3Script_ID = 1, ///< GNB SMU service request function ID.
58 NbSmuServiceRequestS3Script_ID, ///< GNB PCIe late restore function ID.
59 PcieLateRestoreS3Script_ID, ///< GNB SMU indirect write.
60 GnbSmuServiceRequestV4S3Script_ID, ///< SMU service request
61 GnbLibStallS3Script_ID, ///< Stall request
62 PcieLateRestoreTNS3Script_ID, ///< GNB PCIe late restore TN
63 PcieLateRestoreKMS3Script_ID, ///< GNB PCIe late restore KM
64 PcieLateRestoreTHS3Script_ID, ///< GNB PCIe late restore KM
65 GfxRequestSclkTNS3Script_ID ///< SCLk setting
66} S3_DISPATCH_FUNCTION_ID;
67
68#define SAVE_STATE_IO_WRITE_OPCODE 0x00
69#define SAVE_STATE_IO_READ_WRITE_OPCODE 0x01
70#define SAVE_STATE_MEM_WRITE_OPCODE 0x02
71#define SAVE_STATE_MEM_READ_WRITE_OPCODE 0x03
72#define SAVE_STATE_PCI_CONFIG_WRITE_OPCODE 0x04
73#define SAVE_STATE_PCI_CONFIG_READ_WRITE_OPCODE 0x05
74#define SAVE_STATE_STALL_OPCODE 0x07
75#define SAVE_STATE_INFORMATION_OPCODE 0x0A
76#define SAVE_STATE_IO_POLL_OPCODE 0x0D
77#define SAVE_STATE_MEM_POLL_OPCODE 0x0E
78#define SAVE_STATE_PCI_CONFIG_POLL_OPCODE 0x0F
79#define SAVE_STATE_DISPATCH_OPCODE 0x20
80#define SAVE_STATE_BREAKPOINT_OPCODE 0x21
81
82
83#define S3_TABLE_LENGTH 8 * 1024
84#define S3_TABLE_LENGTH_INCREMENT 1 * 1024
85
86/// S3 Save Table
87typedef struct {
88 UINT16 TableLength; ///< Table Length
89 UINT32 SaveOffset; ///< Save Location
90 BOOLEAN Locked; ///< Locked
91} S3_SAVE_TABLE_HEADER;
92
93/// S3 write operation header
94typedef struct {
95 UINT16 OpCode; ///< Opcode
96 ACCESS_WIDTH Width; ///< Data width (byte, word, dword)
97 UINT64 Address; ///< Register address
98 UINT32 Count; ///< Write count
99} S3_WRITE_OP_HEADER;
100
101/// S3 Read and Write Operation header
102typedef struct {
103 UINT16 OpCode; ///< Opcode
104 ACCESS_WIDTH Width; ///< Data width (byte, word, dword)
105 UINT64 Address; ///< Register Address
106} S3_READ_WRITE_OP_HEADER;
107
108/// S3 Poll operation header
109typedef struct {
110 UINT16 OpCode; ///< Opcode
111 ACCESS_WIDTH Width; ///< Data width (byte, word, dword)
112 UINT64 Address; ///< Register address
113 UINT64 Delay; ///< Time delay
114} S3_POLL_OP_HEADER;
115
116/// Information operation header
117typedef struct {
118 UINT16 OpCode; ///< Opcode
119 UINT32 Length; ///< Length of info
120} S3_INFO_OP_HEADER;
121
122/// Dispatch operation header
123typedef struct {
124 UINT16 OpCode; ///< Opcode
125 UINT16 FunctionId; ///< Function ID
126 UINT16 Length; ///< Length in bytes of the context
127} S3_DISPATCH_OP_HEADER;
128
129
130typedef VOID S3_DISPATCH_FUNCTION (
131 IN AMD_CONFIG_PARAMS *StdHeader,
132 IN UINT16 ContextLength,
133 IN VOID *Context
134 );
135
136/// Dispatch function table entry
137typedef struct {
138 UINT16 FunctionId; ///<Function ID
139 S3_DISPATCH_FUNCTION *Function; ///<Function pointer
140} S3_DISPATCH_FUNCTION_ENTRY;
141
142typedef AGESA_STATUS (*S3_SCRIPT_INIT) (
143 IN AMD_CONFIG_PARAMS *StdHeader
144 );
145
146typedef AGESA_STATUS (*S3_SCRIPT_RESTORE) (
147 IN AMD_CONFIG_PARAMS *StdHeader
148 );
149
150/// S3 Script Configuration
151typedef struct {
152 S3_SCRIPT_INIT Init; ///< Script initialization
153 S3_SCRIPT_RESTORE Restore; ///< Script restore
154} S3_SCRIPT_CONFIGURATION;
155
156AGESA_STATUS
157S3ScriptInit (
158 IN AMD_CONFIG_PARAMS *StdHeader
159 );
160
161AGESA_STATUS
162S3ScriptInitState (
163 IN AMD_CONFIG_PARAMS *StdHeader
164 );
165
166AGESA_STATUS
167S3ScriptInitStateStub (
168 IN AMD_CONFIG_PARAMS *StdHeader
169 );
170
171AGESA_STATUS
172S3ScriptRestore (
173 IN AMD_CONFIG_PARAMS *StdHeader
174 );
175
176AGESA_STATUS
177S3ScriptRestoreState (
178 IN AMD_CONFIG_PARAMS *StdHeader
179 );
180
181AGESA_STATUS
182S3ScriptRestoreStateStub (
183 IN AMD_CONFIG_PARAMS *StdHeader
184 );
185
186AGESA_STATUS
187S3ScriptGetS3SaveTable (
188 IN AMD_CONFIG_PARAMS *StdHeader,
189 OUT S3_SAVE_TABLE_HEADER **S3SaveTable
190 );
191
192VOID
193S3SaveDebugPrintHexArray (
194 IN AMD_CONFIG_PARAMS *StdHeader,
Arthur Heymans8d3640d2022-05-16 12:27:36 +0200195 CONST IN VOID *Array,
zbao7d94cf92012-07-02 14:19:14 +0800196 IN UINT32 Count,
197 IN ACCESS_WIDTH Width
198 );
199
200CHAR8*
201S3SaveDebugOpcodeString (
202 IN AMD_CONFIG_PARAMS *StdHeader,
203 IN UINT16 Op
204 );
205
206AGESA_STATUS
207S3SaveStateSaveWriteOp (
208 IN AMD_CONFIG_PARAMS *StdHeader,
209 IN UINT16 OpCode,
210 IN ACCESS_WIDTH Width,
211 IN UINT64 Address,
212 IN UINT32 Count,
Arthur Heymans8d3640d2022-05-16 12:27:36 +0200213 CONST IN VOID *Buffer
zbao7d94cf92012-07-02 14:19:14 +0800214 );
215
216AGESA_STATUS
217S3SaveStateSaveReadWriteOp (
218 IN AMD_CONFIG_PARAMS *StdHeader,
219 IN UINT16 OpCode,
220 IN ACCESS_WIDTH Width,
221 IN UINT64 Address,
222 IN VOID *Data,
223 IN VOID *DataMask
224 );
225
226AGESA_STATUS
227S3SaveStateSavePollOp (
228 IN AMD_CONFIG_PARAMS *StdHeader,
229 IN UINT16 OpCode,
230 IN ACCESS_WIDTH Width,
231 IN UINT64 Address,
232 IN VOID *Data,
233 IN VOID *DataMask,
234 IN UINT64 Delay
235 );
236
237AGESA_STATUS
238S3SaveStateSaveInfoOp (
239 IN AMD_CONFIG_PARAMS *StdHeader,
240 IN UINT16 OpCode,
241 IN UINT32 InformationLength,
242 IN VOID *Information
243 );
244
245AGESA_STATUS
246S3SaveStateSaveDispatchOp (
247 IN AMD_CONFIG_PARAMS *StdHeader,
248 IN UINT16 OpCode,
249 IN UINT16 FunctionId,
250 IN UINT16 ContextLength,
251 IN VOID *Context
252 );
253
254//PCI write
255#define S3_SAVE_PCI_WRITE(StdHeader, Address, Width, DataPtr) \
256 S3SaveStateSaveWriteOp ( \
257 StdHeader, \
258 SAVE_STATE_PCI_CONFIG_WRITE_OPCODE, \
259 Width, \
260 Address.AddressValue, \
261 1, \
262 DataPtr \
263 )
264
265//PCI read modify write
266#define S3_SAVE_PCI_RMW (StdHeader, Address, Width, DataPtr, DataMaskPtr) \
267 S3SaveStateSaveWriteOp ( \
268 StdHeader, \
269 SAVE_STATE_PCI_CONFIG_READ_WRITE_OPCODE, \
270 Width, \
271 Address.AddressValue, \
272 DataPtr, \
273 DataMask \
274 )
275
276//PCI read modify write
277#define S3_SAVE_PCI_POLL(StdHeader, Address, Width, DataPtr, DataMaskPtr, Delay) \
278 S3SaveStateSavePollOp ( \
279 StdHeader, \
280 SAVE_STATE_PCI_CONFIG_POLL_OPCODE, \
281 Width, \
282 Address.AddressValue, \
283 DataPtr, \
284 DataMask, \
285 Delay \
286 )
287
288//Memory/MMIO write
289#define S3_SAVE_MEM_WRITE(StdHeader, Address, Width, DataPtr) \
290 S3SaveStateSaveWriteOp ( \
291 StdHeader, \
292 SAVE_STATE_MEM_WRITE_OPCODE, \
293 Width, \
294 Address, \
295 1, \
296 DataPtr \
297 )
298
299//Memory/MMIO read modify write
300#define S3_SAVE_MEM_RMW(StdHeader, Address, Width, DataPtr, DataMaskPtr) \
301 S3SaveStateSaveWriteOp ( \
302 StdHeader, \
303 SAVE_STATE_MEM_READ_WRITE_OPCODE, \
304 Width, \
305 Address, \
306 DataPtr, \
307 DataMask \
308 )
309
310//Memory/MMIO read modify write
311#define S3_SAVE_MEM_POLL(StdHeader, Address, Width, DataPtr, DataMaskPtr, Delay) \
312 S3SaveStateSavePollOp ( \
313 StdHeader, \
314 SAVE_STATE_MEM_POLL_OPCODE, \
315 Width, \
316 Address, \
317 DataPtr, \
318 DataMask, \
319 Delay \
320 )
321
322// I/O write
323#define S3_SAVE_IO_WRITE(StdHeader, Address, Width, DataPtr) \
324 S3SaveStateSaveWriteOp ( \
325 StdHeader, \
326 SAVE_STATE_IO_WRITE_OPCODE, \
327 Width, \
328 Address, \
329 1, \
330 DataPtr \
331 )
332
333// Save information
334#define S3_SAVE_INFORMATION(StdHeader, InformationLength, Information) \
335 S3SaveStateSaveInfoOp ( \
336 StdHeader, \
337 SAVE_STATE_INFORMATION_OPCODE, \
338 InformationLength, \
339 Information \
340 )
341
342// Save information string S3_SAVE_INFORMATION_STRING (StdHeader, "Message")
343#define S3_SAVE_INFORMATION_STRING(StdHeader, Information) \
344 S3SaveStateSaveInfoOp ( \
345 StdHeader, \
346 SAVE_STATE_INFORMATION_OPCODE, \
347 sizeof (Information), \
348 Information \
349 )
350
351// Save dispatch function
352#define S3_SAVE_DISPATCH(StdHeader, FunctionId, ContextLength, Context) \
353 S3SaveStateSaveDispatchOp ( \
354 StdHeader, \
355 SAVE_STATE_DISPATCH_OPCODE, \
356 FunctionId, \
357 ContextLength, \
358 Context \
359 )
360
361#pragma pack (pop)
362#endif