zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * AMD CPU Power Management Multisocket Functions. |
| 6 | * |
| 7 | * Contains code for doing power management for multisocket CPUs |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: CPU |
| 12 | * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ |
| 13 | * |
| 14 | */ |
| 15 | /* |
| 16 | ****************************************************************************** |
| 17 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 18 | * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. |
| 19 | * All rights reserved. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 20 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 21 | * Redistribution and use in source and binary forms, with or without |
| 22 | * modification, are permitted provided that the following conditions are met: |
| 23 | * * Redistributions of source code must retain the above copyright |
| 24 | * notice, this list of conditions and the following disclaimer. |
| 25 | * * Redistributions in binary form must reproduce the above copyright |
| 26 | * notice, this list of conditions and the following disclaimer in the |
| 27 | * documentation and/or other materials provided with the distribution. |
| 28 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 29 | * its contributors may be used to endorse or promote products derived |
| 30 | * from this software without specific prior written permission. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 31 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 32 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 33 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 34 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 35 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 36 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 37 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 38 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 39 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 40 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 41 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 42 | ****************************************************************************** |
| 43 | */ |
| 44 | |
| 45 | /*---------------------------------------------------------------------------------------- |
| 46 | * M O D U L E S U S E D |
| 47 | *---------------------------------------------------------------------------------------- |
| 48 | */ |
| 49 | |
| 50 | #include "AGESA.h" |
| 51 | #include "amdlib.h" |
| 52 | #include "Ids.h" |
| 53 | #include "cpuRegisters.h" |
| 54 | #include "GeneralServices.h" |
| 55 | #include "cpuServices.h" |
| 56 | #include "cpuApicUtilities.h" |
| 57 | #include "cpuFamilyTranslation.h" |
| 58 | #include "cpuPowerMgmtSystemTables.h" |
| 59 | #include "cpuPowerMgmtMultiSocket.h" |
| 60 | #include "GeneralServices.h" |
| 61 | #include "Filecode.h" |
| 62 | CODE_GROUP (G1_PEICC) |
| 63 | RDATA_GROUP (G1_PEICC) |
| 64 | |
| 65 | #define FILECODE PROC_CPU_CPUPOWERMGMTMULTISOCKET_FILECODE |
| 66 | /*---------------------------------------------------------------------------------------- |
| 67 | * D E F I N I T I O N S A N D M A C R O S |
| 68 | *---------------------------------------------------------------------------------------- |
| 69 | */ |
| 70 | |
| 71 | /*---------------------------------------------------------------------------------------- |
| 72 | * T Y P E D E F S A N D S T R U C T U R E S |
| 73 | *---------------------------------------------------------------------------------------- |
| 74 | */ |
| 75 | |
| 76 | /*---------------------------------------------------------------------------------------- |
| 77 | * P R O T O T Y P E S O F L O C A L F U N C T I O N S |
| 78 | *---------------------------------------------------------------------------------------- |
| 79 | */ |
| 80 | VOID |
| 81 | STATIC |
| 82 | GetNextEvent ( |
| 83 | IN OUT VOID *EventLogEntryPtr, |
| 84 | IN AMD_CONFIG_PARAMS *StdHeader |
| 85 | ); |
| 86 | |
| 87 | /*---------------------------------------------------------------------------------------- |
| 88 | * E X P O R T E D F U N C T I O N S |
| 89 | *---------------------------------------------------------------------------------------- |
| 90 | */ |
| 91 | |
| 92 | /*---------------------------------------------------------------------------------------*/ |
| 93 | /** |
| 94 | * Multisocket BSC call to start all system core 0s to perform a standard AP_TASK. |
| 95 | * |
| 96 | * This function loops through all possible socket locations, starting core 0 of |
| 97 | * each populated socket to perform the passed in AP_TASK. After starting all |
| 98 | * other core 0s, the BSC will perform the AP_TASK as well. This must be run by |
| 99 | * the system BSC only. |
| 100 | * |
| 101 | * @param[in] TaskPtr Function descriptor |
| 102 | * @param[in] StdHeader Config handle for library and services |
| 103 | * @param[in] ConfigParams AMD entry point's CPU parameter structure |
| 104 | * |
| 105 | * @return The most severe error code from AP_TASK |
| 106 | * |
| 107 | */ |
| 108 | AGESA_STATUS |
| 109 | RunCodeOnAllSystemCore0sMulti ( |
| 110 | IN AP_TASK *TaskPtr, |
| 111 | IN AMD_CONFIG_PARAMS *StdHeader, |
| 112 | IN VOID *ConfigParams |
| 113 | ) |
| 114 | { |
| 115 | UINT32 BscSocket; |
| 116 | UINT32 BscModule; |
| 117 | UINT32 BscCoreNum; |
| 118 | UINT8 Socket; |
| 119 | UINT32 NumberOfSockets; |
| 120 | AGESA_STATUS DummyStatus; |
| 121 | AGESA_STATUS AgesaStatus; |
| 122 | AGESA_STATUS CalledStatus; |
| 123 | |
| 124 | |
| 125 | ASSERT (IsBsp (StdHeader, &DummyStatus)); |
| 126 | |
| 127 | NumberOfSockets = GetPlatformNumberOfSockets (); |
| 128 | |
| 129 | IdentifyCore (StdHeader, &BscSocket, &BscModule, &BscCoreNum, &DummyStatus); |
| 130 | AgesaStatus = AGESA_SUCCESS; |
| 131 | |
| 132 | for (Socket = 0; Socket < NumberOfSockets; Socket++) { |
| 133 | if (Socket != BscSocket) { |
| 134 | if (IsProcessorPresent (Socket, StdHeader)) { |
| 135 | CalledStatus = ApUtilRunCodeOnSocketCore (Socket, 0, TaskPtr, StdHeader); |
| 136 | if (CalledStatus > AgesaStatus) { |
| 137 | AgesaStatus = CalledStatus; |
| 138 | } |
| 139 | } |
| 140 | } |
| 141 | } |
| 142 | CalledStatus = ApUtilTaskOnExecutingCore (TaskPtr, StdHeader, ConfigParams); |
| 143 | if (CalledStatus > AgesaStatus) { |
| 144 | AgesaStatus = CalledStatus; |
| 145 | } |
| 146 | |
| 147 | return AgesaStatus; |
| 148 | } |
| 149 | |
| 150 | |
| 151 | /*---------------------------------------------------------------------------------------*/ |
| 152 | /** |
| 153 | * Multisocket BSC call to determine the maximum number of steps that any single |
| 154 | * processor needs to execute. |
| 155 | * |
| 156 | * This function loops through all possible socket locations, gathering the number |
| 157 | * of power management steps each populated socket requires, and returns the |
| 158 | * highest number. |
| 159 | * |
| 160 | * @param[out] NumSystemSteps Maximum number of system steps required |
| 161 | * @param[in] StdHeader Config handle for library and services |
| 162 | * |
| 163 | */ |
| 164 | VOID |
| 165 | GetNumberOfSystemPmStepsPtrMulti ( |
| 166 | OUT UINT8 *NumSystemSteps, |
| 167 | IN AMD_CONFIG_PARAMS *StdHeader |
| 168 | ) |
| 169 | { |
| 170 | UINT8 NumberOfSteps; |
| 171 | UINT32 NumberOfSockets; |
| 172 | UINT32 Socket; |
| 173 | SYS_PM_TBL_STEP *Ignored; |
| 174 | CPU_SPECIFIC_SERVICES *FamilySpecificServices; |
| 175 | |
| 176 | NumberOfSockets = GetPlatformNumberOfSockets (); |
| 177 | *NumSystemSteps = 0; |
| 178 | |
| 179 | for (Socket = 0; Socket < NumberOfSockets; Socket++) { |
| 180 | if (IsProcessorPresent (Socket, StdHeader)) { |
| 181 | GetCpuServicesOfSocket (Socket, (CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); |
| 182 | FamilySpecificServices->GetSysPmTableStruct (FamilySpecificServices, (CONST VOID **) &Ignored, &NumberOfSteps, StdHeader); |
| 183 | if (NumberOfSteps > *NumSystemSteps) { |
| 184 | *NumSystemSteps = NumberOfSteps; |
| 185 | } |
| 186 | } |
| 187 | } |
| 188 | } |
| 189 | |
| 190 | |
| 191 | /*---------------------------------------------------------------------------------------*/ |
| 192 | /** |
| 193 | * Multisocket call to determine the frequency that the northbridges must run. |
| 194 | * |
| 195 | * This function loops through all possible socket locations, comparing the |
| 196 | * maximum NB frequencies to determine the slowest. This function also |
| 197 | * determines if all coherent NB frequencies are equivalent. |
| 198 | * |
| 199 | * @param[in] NbPstate NB P-state number to check (0 = fastest) |
| 200 | * @param[in] PlatformConfig Platform profile/build option config structure. |
| 201 | * @param[out] SystemNbCofNumerator NB frequency numerator for the system in MHz |
| 202 | * @param[out] SystemNbCofDenominator NB frequency denominator for the system |
| 203 | * @param[out] SystemNbCofsMatch Whether or not all NB frequencies are equivalent |
| 204 | * @param[out] NbPstateIsEnabledOnAllCPUs Whether or not NbPstate is valid on all CPUs |
| 205 | * @param[in] StdHeader Config handle for library and services |
| 206 | * |
| 207 | * @retval TRUE At least one processor has NbPstate enabled. |
| 208 | * @retval FALSE NbPstate is disabled on all CPUs |
| 209 | * |
| 210 | */ |
| 211 | BOOLEAN |
| 212 | GetSystemNbCofMulti ( |
| 213 | IN UINT32 NbPstate, |
| 214 | IN PLATFORM_CONFIGURATION *PlatformConfig, |
| 215 | OUT UINT32 *SystemNbCofNumerator, |
| 216 | OUT UINT32 *SystemNbCofDenominator, |
| 217 | OUT BOOLEAN *SystemNbCofsMatch, |
| 218 | OUT BOOLEAN *NbPstateIsEnabledOnAllCPUs, |
| 219 | IN AMD_CONFIG_PARAMS *StdHeader |
| 220 | ) |
| 221 | { |
| 222 | UINT32 Socket; |
| 223 | UINT8 Module; |
| 224 | UINT32 CurrentNbCof; |
| 225 | UINT32 CurrentDivisor; |
| 226 | UINT32 CurrentFreq; |
| 227 | UINT32 LowFrequency; |
| 228 | UINT32 Ignored32; |
| 229 | BOOLEAN FirstCofNotFound; |
| 230 | BOOLEAN NbPstateDisabled; |
| 231 | BOOLEAN IsNbPstateEnabledOnAny; |
| 232 | PCI_ADDR PciAddress; |
| 233 | AGESA_STATUS Ignored; |
| 234 | CPU_SPECIFIC_SERVICES *FamilySpecificServices; |
| 235 | |
| 236 | // Find the slowest NB COF in the system & whether or not all are equivalent |
| 237 | LowFrequency = 0xFFFFFFFF; |
| 238 | *SystemNbCofsMatch = TRUE; |
| 239 | *NbPstateIsEnabledOnAllCPUs = FALSE; |
| 240 | IsNbPstateEnabledOnAny = FALSE; |
| 241 | FirstCofNotFound = TRUE; |
| 242 | NbPstateDisabled = FALSE; |
| 243 | for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { |
| 244 | if (IsProcessorPresent (Socket, StdHeader)) { |
| 245 | GetCpuServicesOfSocket (Socket, (CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); |
| 246 | for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { |
| 247 | if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &Ignored)) { |
| 248 | break; |
| 249 | } |
| 250 | } |
| 251 | if (FamilySpecificServices->GetNbPstateInfo (FamilySpecificServices, |
| 252 | PlatformConfig, |
| 253 | &PciAddress, |
| 254 | NbPstate, |
| 255 | &CurrentNbCof, |
| 256 | &CurrentDivisor, |
| 257 | &Ignored32, |
| 258 | StdHeader)) { |
| 259 | ASSERT (CurrentDivisor != 0); |
| 260 | CurrentFreq = (CurrentNbCof / CurrentDivisor); |
| 261 | if (FirstCofNotFound) { |
| 262 | *SystemNbCofNumerator = CurrentNbCof; |
| 263 | *SystemNbCofDenominator = CurrentDivisor; |
| 264 | LowFrequency = CurrentFreq; |
| 265 | IsNbPstateEnabledOnAny = TRUE; |
| 266 | if (!NbPstateDisabled) { |
| 267 | *NbPstateIsEnabledOnAllCPUs = TRUE; |
| 268 | } |
| 269 | FirstCofNotFound = FALSE; |
| 270 | } else { |
| 271 | if (CurrentFreq != LowFrequency) { |
| 272 | *SystemNbCofsMatch = FALSE; |
| 273 | if (CurrentFreq < LowFrequency) { |
| 274 | LowFrequency = CurrentFreq; |
| 275 | *SystemNbCofNumerator = CurrentNbCof; |
| 276 | *SystemNbCofDenominator = CurrentDivisor; |
| 277 | } |
| 278 | } |
| 279 | } |
| 280 | } else { |
| 281 | NbPstateDisabled = TRUE; |
| 282 | *NbPstateIsEnabledOnAllCPUs = FALSE; |
| 283 | } |
| 284 | } |
| 285 | } |
| 286 | return IsNbPstateEnabledOnAny; |
| 287 | } |
| 288 | |
| 289 | |
| 290 | /*---------------------------------------------------------------------------------------*/ |
| 291 | /** |
| 292 | * Multisocket call to determine if the BIOS is responsible for updating the |
| 293 | * northbridge operating frequency and voltage. |
| 294 | * |
| 295 | * This function loops through all possible socket locations, checking whether |
| 296 | * any populated sockets require NB COF VID programming. |
| 297 | * |
| 298 | * @param[in] StdHeader Config handle for library and services |
| 299 | * |
| 300 | * @retval TRUE BIOS needs to set up NB frequency and voltage |
| 301 | * @retval FALSE BIOS does not need to set up NB frequency and voltage |
| 302 | * |
| 303 | */ |
| 304 | BOOLEAN |
| 305 | GetSystemNbCofVidUpdateMulti ( |
| 306 | IN AMD_CONFIG_PARAMS *StdHeader |
| 307 | ) |
| 308 | { |
| 309 | UINT8 Module; |
| 310 | UINT32 Socket; |
| 311 | UINT32 NumberOfSockets; |
| 312 | BOOLEAN IgnoredBool; |
| 313 | BOOLEAN AtLeast1RequiresUpdate; |
| 314 | PCI_ADDR PciAddress; |
| 315 | AGESA_STATUS Ignored; |
| 316 | CPU_SPECIFIC_SERVICES *FamilySpecificServices; |
| 317 | |
| 318 | NumberOfSockets = GetPlatformNumberOfSockets (); |
| 319 | |
| 320 | AtLeast1RequiresUpdate = FALSE; |
| 321 | for (Socket = 0; Socket < NumberOfSockets; Socket++) { |
| 322 | if (IsProcessorPresent (Socket, StdHeader)) { |
| 323 | GetCpuServicesOfSocket (Socket, (CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); |
| 324 | for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { |
| 325 | if (GetPciAddress (StdHeader, (UINT8) Socket, Module, &PciAddress, &Ignored)) { |
| 326 | break; |
| 327 | } |
| 328 | } |
| 329 | if (FamilySpecificServices->IsNbCofInitNeeded (FamilySpecificServices, &PciAddress, &IgnoredBool, StdHeader)) { |
| 330 | AtLeast1RequiresUpdate = TRUE; |
| 331 | break; |
| 332 | } |
| 333 | } |
| 334 | } |
| 335 | return AtLeast1RequiresUpdate; |
| 336 | } |
| 337 | |
| 338 | |
| 339 | /*---------------------------------------------------------------------------------------*/ |
| 340 | /** |
| 341 | * Multisocket call to determine the most severe AGESA_STATUS return value after |
| 342 | * processing the power management initialization tables. |
| 343 | * |
| 344 | * This function loops through all possible socket locations, collecting any |
| 345 | * power management initialization errors that may have occurred. These errors |
| 346 | * are transferred from the core 0s of the socket in which the errors occurred |
| 347 | * to the BSC's heap. The BSC's heap is then searched for the most severe error |
| 348 | * that occurred, and returns it. This function must be called by the BSC only. |
| 349 | * |
| 350 | * @param[in] StdHeader Config handle for library and services |
| 351 | * |
| 352 | * @return The most severe error code from power management init |
| 353 | * |
| 354 | */ |
| 355 | AGESA_STATUS |
| 356 | GetEarlyPmErrorsMulti ( |
| 357 | IN AMD_CONFIG_PARAMS *StdHeader |
| 358 | ) |
| 359 | { |
| 360 | UINT16 i; |
| 361 | UINT32 BscSocket; |
| 362 | UINT32 BscModule; |
| 363 | UINT32 BscCoreNum; |
| 364 | UINT32 Socket; |
| 365 | UINT32 NumberOfSockets; |
| 366 | AP_TASK TaskPtr; |
| 367 | AGESA_EVENT EventLogEntry; |
| 368 | AGESA_STATUS ReturnCode; |
| 369 | AGESA_STATUS DummyStatus; |
| 370 | |
| 371 | ASSERT (IsBsp (StdHeader, &ReturnCode)); |
| 372 | |
| 373 | ReturnCode = AGESA_SUCCESS; |
| 374 | EventLogEntry.EventClass = AGESA_SUCCESS; |
| 375 | EventLogEntry.EventInfo = 0; |
| 376 | EventLogEntry.DataParam1 = 0; |
| 377 | EventLogEntry.DataParam2 = 0; |
| 378 | EventLogEntry.DataParam3 = 0; |
| 379 | EventLogEntry.DataParam4 = 0; |
| 380 | |
| 381 | NumberOfSockets = GetPlatformNumberOfSockets (); |
| 382 | IdentifyCore (StdHeader, &BscSocket, &BscModule, &BscCoreNum, &DummyStatus); |
| 383 | |
| 384 | TaskPtr.FuncAddress.PfApTaskI = GetNextEvent; |
| 385 | TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (AGESA_EVENT); |
| 386 | TaskPtr.DataTransfer.DataPtr = &EventLogEntry; |
| 387 | TaskPtr.DataTransfer.DataTransferFlags = 0; |
| 388 | TaskPtr.ExeFlags = WAIT_FOR_CORE | RETURN_PARAMS; |
| 389 | for (Socket = 0; Socket < NumberOfSockets; Socket++) { |
| 390 | if (Socket != BscSocket) { |
| 391 | if (IsProcessorPresent (Socket, StdHeader)) { |
| 392 | do { |
| 393 | ApUtilRunCodeOnSocketCore ((UINT8)Socket, (UINT8) 0, &TaskPtr, StdHeader); |
| 394 | if ((EventLogEntry.EventInfo & CPU_EVENT_PM_EVENT_MASK) == CPU_EVENT_PM_EVENT_CLASS) { |
| 395 | PutEventLog ( |
| 396 | EventLogEntry.EventClass, |
| 397 | EventLogEntry.EventInfo, |
| 398 | EventLogEntry.DataParam1, |
| 399 | EventLogEntry.DataParam2, |
| 400 | EventLogEntry.DataParam3, |
| 401 | EventLogEntry.DataParam4, |
| 402 | StdHeader |
| 403 | ); |
| 404 | } |
| 405 | } while (EventLogEntry.EventInfo != 0); |
| 406 | } |
| 407 | } |
| 408 | } |
| 409 | |
| 410 | for (i = 0; PeekEventLog (&EventLogEntry, i, StdHeader); i++) { |
| 411 | if ((EventLogEntry.EventInfo & CPU_EVENT_PM_EVENT_MASK) == CPU_EVENT_PM_EVENT_CLASS) { |
| 412 | if (EventLogEntry.EventClass > ReturnCode) { |
| 413 | ReturnCode = EventLogEntry.EventClass; |
| 414 | } |
| 415 | } |
| 416 | } |
| 417 | return (ReturnCode); |
| 418 | } |
| 419 | |
| 420 | /** |
| 421 | * Multisocket call to loop through all possible socket locations and Nb Pstates, |
| 422 | * comparing the NB frequencies to determine the slowest system and P0 frequency |
| 423 | * |
| 424 | * @param[in] PlatformConfig Platform profile/build option config structure. |
| 425 | * @param[out] MinSysNbFreq NB frequency numerator for the system in MHz |
| 426 | * @param[out] MinP0NbFreq NB frequency numerator for P0 in MHz |
| 427 | * @param[in] StdHeader Config handle for library and services |
| 428 | */ |
| 429 | VOID |
| 430 | GetMinNbCofMulti ( |
| 431 | IN PLATFORM_CONFIGURATION *PlatformConfig, |
| 432 | OUT UINT32 *MinSysNbFreq, |
| 433 | OUT UINT32 *MinP0NbFreq, |
| 434 | IN AMD_CONFIG_PARAMS *StdHeader |
| 435 | ) |
| 436 | { |
| 437 | UINT32 Socket; |
| 438 | UINT32 Module; |
| 439 | UINT32 CurrMinFreq; |
| 440 | UINT32 CurrMaxFreq; |
| 441 | PCI_ADDR PciAddress; |
| 442 | AGESA_STATUS Ignored; |
| 443 | CPU_SPECIFIC_SERVICES *FamilySpecificServices; |
| 444 | AGESA_STATUS AgesaStatus; |
| 445 | |
| 446 | *MinSysNbFreq = 0xFFFFFFFF; |
| 447 | *MinP0NbFreq = 0xFFFFFFFF; |
| 448 | |
| 449 | for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { |
| 450 | if (IsProcessorPresent (Socket, StdHeader)) { |
| 451 | GetCpuServicesOfSocket (Socket, (CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); |
| 452 | for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { |
| 453 | if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &Ignored )) { |
| 454 | break; |
| 455 | } |
| 456 | } |
| 457 | |
| 458 | |
| 459 | AgesaStatus = FamilySpecificServices->GetMinMaxNbFrequency (FamilySpecificServices, |
| 460 | PlatformConfig, |
| 461 | &PciAddress, |
| 462 | &CurrMinFreq, |
| 463 | &CurrMaxFreq, |
| 464 | StdHeader); |
| 465 | ASSERT (AgesaStatus == AGESA_SUCCESS); |
| 466 | ASSERT ((CurrMinFreq != 0) && (CurrMaxFreq != 0)); |
| 467 | // Determine the slowest NB Pmin frequency |
| 468 | if (CurrMinFreq < *MinSysNbFreq) { |
| 469 | *MinSysNbFreq = CurrMinFreq; |
| 470 | } |
| 471 | |
| 472 | // Determine the slowest NB P0 frequency |
| 473 | if (CurrMaxFreq < *MinP0NbFreq) { |
| 474 | *MinP0NbFreq = CurrMaxFreq; |
| 475 | } |
| 476 | } |
| 477 | } |
| 478 | } |
| 479 | |
| 480 | /*---------------------------------------------------------------------------------------*/ |
| 481 | /** |
| 482 | * Get PCI Config Space Address for the current running core. |
| 483 | * |
| 484 | * @param[out] PciAddress The Processor's PCI Config Space address (Function 0, Register 0) |
| 485 | * @param[in] StdHeader Header for library and services. |
| 486 | * |
| 487 | * @retval TRUE The core is present, PCI Address valid |
| 488 | * @retval FALSE The core is not present, PCI Address not valid. |
| 489 | */ |
| 490 | BOOLEAN |
| 491 | GetCurrPciAddrMulti ( |
| 492 | OUT PCI_ADDR *PciAddress, |
| 493 | IN AMD_CONFIG_PARAMS *StdHeader |
| 494 | ) |
| 495 | { |
| 496 | UINT8 Node; |
| 497 | UINT32 Socket; |
| 498 | UINT32 Module; |
| 499 | UINT32 Core; |
| 500 | BOOLEAN Result; |
| 501 | AGESA_STATUS IgnoredSts; |
| 502 | |
| 503 | Result = TRUE; |
| 504 | |
| 505 | IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts); |
| 506 | |
| 507 | ASSERT (Socket < MAX_SOCKETS); |
| 508 | ASSERT (Module < MAX_DIES); |
| 509 | |
| 510 | if (GetNodeId (Socket, Module, &Node, StdHeader)) { |
| 511 | // Socket is populated |
| 512 | PciAddress->AddressValue = MAKE_SBDFO (0, 0, 24, 0, 0); |
| 513 | PciAddress->Address.Device = PciAddress->Address.Device + Node; |
| 514 | } else { |
| 515 | // Socket is not populated |
| 516 | PciAddress->AddressValue = ILLEGAL_SBDFO; |
| 517 | Result = FALSE; |
| 518 | } |
| 519 | |
| 520 | return Result; |
| 521 | } |
| 522 | |
| 523 | /*---------------------------------------------------------------------------------------*/ |
| 524 | /** |
| 525 | * Writes to all nodes on the executing core's socket. |
| 526 | * |
| 527 | * @param[in] PciAddress The Function and Register to update |
| 528 | * @param[in] Mask The bitwise AND mask to apply to the current register value |
| 529 | * @param[in] Data The bitwise OR mask to apply to the current register value |
| 530 | * @param[in] StdHeader Header for library and services. |
| 531 | * |
| 532 | */ |
| 533 | VOID |
| 534 | ModifyCurrSocketPciMulti ( |
| 535 | IN PCI_ADDR *PciAddress, |
| 536 | IN UINT32 Mask, |
| 537 | IN UINT32 Data, |
| 538 | IN AMD_CONFIG_PARAMS *StdHeader |
| 539 | ) |
| 540 | { |
| 541 | UINT32 Socket; |
| 542 | UINT32 Module; |
| 543 | UINT32 Core; |
| 544 | UINT32 LocalPciRegister; |
| 545 | AGESA_STATUS AgesaStatus; |
| 546 | PCI_ADDR Reg; |
| 547 | |
| 548 | IdentifyCore (StdHeader, &Socket, &Module, &Core, &AgesaStatus); |
| 549 | |
| 550 | for (Module = 0; Module < (UINT8)GetPlatformNumberOfModules (); Module++) { |
| 551 | if (GetPciAddress (StdHeader, Socket, Module, &Reg, &AgesaStatus)) { |
| 552 | Reg.Address.Function = PciAddress->Address.Function; |
| 553 | Reg.Address.Register = PciAddress->Address.Register; |
| 554 | LibAmdPciRead (AccessWidth32, Reg, &LocalPciRegister, StdHeader); |
| 555 | LocalPciRegister &= Mask; |
| 556 | LocalPciRegister |= Data; |
| 557 | LibAmdPciWrite (AccessWidth32, Reg, &LocalPciRegister, StdHeader); |
| 558 | } |
| 559 | } |
| 560 | } |
| 561 | |
| 562 | /*--------------------------------------------------------------------------------------- |
| 563 | * L O C A L F U N C T I O N S |
| 564 | *--------------------------------------------------------------------------------------- |
| 565 | */ |
| 566 | |
| 567 | /*---------------------------------------------------------------------------------------*/ |
| 568 | /** |
| 569 | * AP task to return the next event log entry to the BSC. |
| 570 | * |
| 571 | * This function calls to the event log manager to retrieve the next error out |
| 572 | * of the heap. |
| 573 | * |
| 574 | * @param[out] EventLogEntryPtr The AP's next event log entry |
| 575 | * @param[in] StdHeader Config handle for library and services |
| 576 | * |
| 577 | */ |
| 578 | VOID |
| 579 | STATIC |
| 580 | GetNextEvent ( |
| 581 | IN OUT VOID *EventLogEntryPtr, |
| 582 | IN AMD_CONFIG_PARAMS *StdHeader |
| 583 | ) |
| 584 | { |
| 585 | GetEventLog ((AGESA_EVENT *) EventLogEntryPtr, StdHeader); |
| 586 | } |