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review.coreboot.org / coreboot / 9a458e4e58edbfc154dce007961514b5c31cf7aa / . / src / vendorcode / amd / agesa / f15tn / Proc / CPU / cpuPostInit.h
blob: db80c56d65876435fcea8ae5cd8d5934e6c6fbba [file] [log] [blame]
zbao7d94cf92012-07-02 14:19:14 +0800[diff] [blame]1/* $NoKeywords:$ */
2/**
3 * @file
4 *
5 * AMD CPU Reset API, and related functions and structures.
6 *
7 * Contains code that initialized the CPU after early reset.
8 *
9 * @xrefitem bom "File Content Label" "Release Content"
10 * @e project: AGESA
11 * @e sub-project: CPU
12 * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
13 *
14 */
15/*
16 ******************************************************************************
17 *
Siyuan Wang641f00c2013-06-08 11:50:55 +0800[diff] [blame]18 * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
19 * All rights reserved.
zbao7d94cf92012-07-02 14:19:14 +0800[diff] [blame]20 *
Siyuan Wang641f00c2013-06-08 11:50:55 +0800[diff] [blame]21 * Redistribution and use in source and binary forms, with or without
22 * modification, are permitted provided that the following conditions are met:
23 * * Redistributions of source code must retain the above copyright
24 * notice, this list of conditions and the following disclaimer.
25 * * Redistributions in binary form must reproduce the above copyright
26 * notice, this list of conditions and the following disclaimer in the
27 * documentation and/or other materials provided with the distribution.
28 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
29 * its contributors may be used to endorse or promote products derived
30 * from this software without specific prior written permission.
zbao7d94cf92012-07-02 14:19:14 +0800[diff] [blame]31 *
Siyuan Wang641f00c2013-06-08 11:50:55 +0800[diff] [blame]32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
34 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
36 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
37 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
38 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
39 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
41 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
zbao7d94cf92012-07-02 14:19:14 +0800[diff] [blame]42 ******************************************************************************
43 */
44
45#ifndef _CPU_POST_INIT_H_
46#define _CPU_POST_INIT_H_
47
48
49/*---------------------------------------------------------------------------------------
50 * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
51 *---------------------------------------------------------------------------------------
52 */
53// Forward declaration needed for multi-structure mutual references
54AGESA_FORWARD_DECLARATION (CPU_CFOH_FAMILY_SERVICES);
55
56/*---------------------------------------------------------------------------------------
57 * D E F I N I T I O N S A N D M A C R O S
58 *---------------------------------------------------------------------------------------
59 */
60#define P_STATE_DATA_GATHER_TEMP_ADDR 0x200000ul ///< Fixed the row data at 2M memory address.
61#define GLOBAL_CPU_FEATURE_LIST_TEMP_ADDR 0x200000ul ///< Fixed the row data at 2M memory address.
62/*---------------------------------------------------------------------------------------
63 * T Y P E D E F S, S T R U C T U R E S, E N U M S
64 *---------------------------------------------------------------------------------------
65 */
66//----------------------------------------------------------------------------
67// CPU FEATURE LEVELING TYPEDEFS, STRUCTURES, ENUMS
68//
69//----------------------------------------------------------------------------
70/// CPU FEATURE LIST
71typedef struct {
72 UINT8 ABM:1; ///< byte 0 bit 0
73 UINT8 AES:1; ///< byte 0 bit 1
74 UINT8 AltMovCr8:1; ///< byte 0 bit 2
75 UINT8 APIC:1; ///< byte 0 bit 3
76 UINT8 AVX:1; ///< byte 0 bit 4
77 UINT8 CLFSH:1; ///< byte 0 bit 5
78 UINT8 CMOV:1; ///< byte 0 bit 6
79 UINT8 CmpLegacy:1; ///< byte 0 bit 7
80 UINT8 CMPXCHG8B:1; ///< byte 1 bit 0
81 UINT8 CMPXCHG16B:1; ///< byte 1 bit 1
82 UINT8 F16C :1; ///< byte 1 bit 2
83 UINT8 DE:1; ///< byte 1 bit 3
84 UINT8 ExtApicSpace:1; ///< byte 1 bit 4
85 UINT8 FFXSR:1; ///< byte 1 bit 5
86 UINT8 FMA:1; ///< byte 1 bit 6
87 UINT8 FMA4:1; ///< byte 1 bit 7
88 UINT8 FPU:1; ///< byte 2 bit 0
89 UINT8 FXSR:1; ///< byte 2 bit 1
90 UINT8 HTT:1; ///< byte 2 bit 2
91 UINT8 IBS:1; ///< byte 2 bit 3
92 UINT8 LahfSahf:1; ///< byte 2 bit 4
93 UINT8 LM:1; ///< byte 2 bit 5
94 UINT8 LWP:1; ///< byte 2 bit 6
95 UINT8 MCA:1; ///< byte 2 bit 7
96 UINT8 MCE:1; ///< byte 3 bit 0
97 UINT8 MisAlignSse:1; ///< byte 3 bit 1
98 UINT8 MMX:1; ///< byte 3 bit 2
99 UINT8 MmxExt:1; ///< byte 3 bit 3
100 UINT8 Monitor:1; ///< byte 3 bit 4
101 UINT8 MSR:1; ///< byte 3 bit 5
102 UINT8 MTRR:1; ///< byte 3 bit 6
103 UINT8 NodeId:1; ///< byte 3 bit 7
104 UINT8 NX:1; ///< byte 4 bit 0
105 UINT8 OSVW:1; ///< byte 4 bit 1
106 UINT8 OSXSAVE:1; ///< byte 4 bit 2
107 UINT8 PAE:1; ///< byte 4 bit 3
108 UINT8 Page1GB:1; ///< byte 4 bit 4
109 UINT8 PAT:1; ///< byte 4 bit 5
110 UINT8 PCLMULQDQ:1; ///< byte 4 bit 6
111 UINT8 PGE:1; ///< byte 4 bit 7
112 UINT8 POPCNT:1; ///< byte 5 bit 0
113 UINT8 PSE:1; ///< byte 5 bit 1
114 UINT8 PSE36:1; ///< byte 5 bit 2
115 UINT8 RDTSCP:1; ///< byte 5 bit 3
116 UINT8 SKINIT:1; ///< byte 5 bit 4
117 UINT8 SSE:1; ///< byte 5 bit 5
118 UINT8 SSE2:1; ///< byte 5 bit 6
119 UINT8 SSE3:1; ///< byte 5 bit 7
120 UINT8 SSE4A:1; ///< byte 6 bit 0
121 UINT8 SSE41:1; ///< byte 6 bit 1
122 UINT8 SSE42:1; ///< byte 6 bit 2
123 UINT8 SSE5:1; ///< byte 6 bit 3
124 UINT8 SSSE3:1; ///< byte 6 bit 4
125 UINT8 SVM:1; ///< byte 6 bit 5
126 UINT8 SysCallSysRet:1; ///< byte 6 bit 6
127 UINT8 SysEnterSysExit:1; ///< byte 6 bit 7
128 UINT8 bit56 :1; ///< byte 7 bit 0
129 UINT8 TCE:1; ///< byte 7 bit 1
130 UINT8 ThreeDNow:1; ///< byte 7 bit 2
131 UINT8 ThreeDNowExt:1; ///< byte 7 bit 3
132 UINT8 ThreeDNowPrefetch:1; ///< byte 7 bit 4
133 UINT8 TimeStampCounter:1; ///< byte 7 bit 5
134 UINT8 VME:1; ///< byte 7 bit 6
135 UINT8 WDT:1; ///< byte 7 bit 7
136 UINT8 X2APIC:1; ///< byte 8 bit 0
137 UINT8 XOP:1; ///< byte 8 bit 1
138 UINT8 XSAVE:1; ///< byte 8 bit 2
139 UINT8 Reserve:5; ///< Reserved
140} CPU_FEATURES_LIST;
141
142//----------------------------------------------------------------------------
143// POST INIT TYPEDEFS, STRUCTURES, ENUMS
144//
145//----------------------------------------------------------------------------
146/// BSC to AP MSR sync up
147typedef struct {
148 UINT32 RegisterAddress; ///< MSR Address
149 UINT64 RegisterValue; ///< BSC's MSR Value
150} BSC_AP_MSR_SYNC;
151
152/**
153 * Set Cache Flush On Halt Register.
154 *
155 * @CpuServiceInstances
156 *
157 * @param[in] FamilySpecificServices The current Family Specific Services.
158 * @param[in] EntryPoint Timepoint designator.
159 * @param[in] PlatformConfig Contains the runtime modifiable feature input data.
160 * @param[in] StdHeader Handle of Header for calling lib functions and services.
161 *
162 */
163typedef VOID (F_CPU_SET_CFOH_REG) (
164 IN CPU_CFOH_FAMILY_SERVICES *FamilySpecificServices,
165 IN UINT64 EntryPoint,
166 IN PLATFORM_CONFIGURATION *PlatformConfig,
167 IN AMD_CONFIG_PARAMS *StdHeader
168 );
169
170 /// Reference to a Method.
171typedef F_CPU_SET_CFOH_REG *PF_CPU_SET_CFOH_REG;
172
173/**
174 * Provide the interface to the Cache Flush On Halt Family Specific Services.
175 *
176 * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!).
177 * Each supported Family must provide an implementation for all methods in this interface, even if the
178 * implementation is a CommonReturn().
179 */
180struct _CPU_CFOH_FAMILY_SERVICES { // See forward reference above
181 UINT16 Revision; ///< Interface version
182 // Public Methods.
183 PF_CPU_SET_CFOH_REG SetCacheFlushOnHaltRegister; ///< Method: Set Cache Flush On Halt register.
184};
185
186/*---------------------------------------------------------------------------------------
187 * F U N C T I O N P R O T O T Y P E
188 *---------------------------------------------------------------------------------------
189 */
190
191// These are P U B L I C functions, used by IBVs
192AGESA_STATUS
193AmdCpuPost (
194 IN AMD_CONFIG_PARAMS *StdHeader,
195 IN PLATFORM_CONFIGURATION *PlatformConfig
196 );
197
198// These are P U B L I C functions, used by AGESA
199
200VOID
201FeatureLeveling (
202 IN OUT AMD_CONFIG_PARAMS *StdHeader
203 );
204
205AGESA_STATUS
206CopyHeapToTempRamAtPost (
207 IN OUT AMD_CONFIG_PARAMS *StdHeader
208 );
209
210VOID
211SyncApMsrsToBsc (
212 IN OUT BSC_AP_MSR_SYNC *ApMsrSync,
213 IN AMD_CONFIG_PARAMS *StdHeader
214 );
215
216AGESA_STATUS
217FinalizeAtPost (
218 IN AMD_CONFIG_PARAMS *StdHeader
219 );
220
221VOID
222SetCoresTscFreqSel (
223 IN AMD_CONFIG_PARAMS *StdHeader
224 );
225
226AGESA_STATUS
227GetPstateGatherDataAddressAtPost (
228 OUT UINT64 **Ptr,
229 IN AMD_CONFIG_PARAMS *StdHeader
230 );
231
232VOID
233SyncAllApMtrrToBsc (
234 IN VOID *MtrrTable,
235 IN AMD_CONFIG_PARAMS *StdHeader
236 );
237#endif // _CPU_POST_INIT_H_
238