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review.coreboot.org / coreboot / 9a458e4e58edbfc154dce007961514b5c31cf7aa / . / src / vendorcode / amd / agesa / f15tn / Proc / CPU / cpuLateInit.h
blob: a965a1d7d9c84d565c4bb6549734fb1fdc0c6497 [file] [log] [blame]
zbao7d94cf92012-07-02 14:19:14 +0800[diff] [blame]1/* $NoKeywords:$ */
2/**
3 * @file
4 *
5 * AMD CPU Late Init API functions Prototypes.
6 *
7 * Contains code for doing any late CPU initialization
8 *
9 * @xrefitem bom "File Content Label" "Release Content"
10 * @e project: AGESA
11 * @e sub-project: CPU
12 * @e \$Revision: 64351 $ @e \$Date: 2012-01-19 03:50:41 -0600 (Thu, 19 Jan 2012) $
13 *
14 */
15/*
16 ******************************************************************************
17 *
Siyuan Wang641f00c2013-06-08 11:50:55 +0800[diff] [blame]18 * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
19 * All rights reserved.
zbao7d94cf92012-07-02 14:19:14 +0800[diff] [blame]20 *
Siyuan Wang641f00c2013-06-08 11:50:55 +0800[diff] [blame]21 * Redistribution and use in source and binary forms, with or without
22 * modification, are permitted provided that the following conditions are met:
23 * * Redistributions of source code must retain the above copyright
24 * notice, this list of conditions and the following disclaimer.
25 * * Redistributions in binary form must reproduce the above copyright
26 * notice, this list of conditions and the following disclaimer in the
27 * documentation and/or other materials provided with the distribution.
28 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
29 * its contributors may be used to endorse or promote products derived
30 * from this software without specific prior written permission.
zbao7d94cf92012-07-02 14:19:14 +0800[diff] [blame]31 *
Siyuan Wang641f00c2013-06-08 11:50:55 +0800[diff] [blame]32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
34 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
36 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
37 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
38 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
39 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
41 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
zbao7d94cf92012-07-02 14:19:14 +0800[diff] [blame]42 ******************************************************************************
43 */
44
45#ifndef _CPU_LATE_INIT_H_
46#define _CPU_LATE_INIT_H_
47
48#include "Filecode.h"
49
50// Forward declaration needed for multi-structure mutual references.
51AGESA_FORWARD_DECLARATION (PROC_FAMILY_TABLE);
52/*----------------------------------------------------------------------------------------
53 * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
54 *----------------------------------------------------------------------------------------
55 */
56
57/*----------------------------------------------------------------------------------------
58 * D E F I N I T I O N S A N D M A C R O S
59 *----------------------------------------------------------------------------------------
60 */
61AGESA_STATUS
62CpuLateInitApTask (
63 IN AP_EXE_PARAMS *ApExeParams
64 );
65
66#define AP_LATE_TASK_CPU_LATE_INIT (PROC_CPU_CPULATEINIT_FILECODE)
67#define CPU_LATE_INIT_AP_TASK {AP_LATE_TASK_CPU_LATE_INIT, (IMAGE_ENTRY) CpuLateInitApTask},
68
69//----------------------------------------------------------------------------
70// DMI DEFINITIONS AND MACROS
71//
72//----------------------------------------------------------------------------
73#define AP_LATE_TASK_GET_TYPE4_TYPE7 (PROC_CPU_FEATURE_CPUDMI_FILECODE)
74// SMBIOS constant definition
75#define CENTRAL_PROCESSOR 0x03
76#define EXTERNAL_CLOCK_DFLT 200
77#define EXTERNAL_CLOCK_100MHZ 100
78#define P_FAMILY_UNKNOWN 0x02
79#define P_ENGINEERING_SAMPLE 0x00
80#define P_CHARACTERISTICS 0x4
81#define CACHE_CFG_L1 0x180
82#define CACHE_CFG_L2 0x181
83#define CACHE_CFG_L3 0x182
84#define SRAM_TYPE 0x10
85#define ERR_CORRECT_TYPE 0x06
86#define CACHE_TYPE 0x05
87#define DMI_ASSOCIATIVE_OTHER 0x01
88#define DMI_ASSOCIATIVE_UNKNOWN 0x02
89#define DMI_ASSOCIATIVE_DIRECT_MAPPED 0x03
90#define DMI_ASSOCIATIVE_2_WAY 0x04
91#define DMI_ASSOCIATIVE_4_WAY 0x05
92#define DMI_ASSOCIATIVE_FULLY 0x06
93#define DMI_ASSOCIATIVE_8_WAY 0x07
94#define DMI_ASSOCIATIVE_16_WAY 0x08
95#define DMI_ASSOCIATIVE_12_WAY 0x09
96#define DMI_ASSOCIATIVE_24_WAY 0x0A
97#define DMI_ASSOCIATIVE_32_WAY 0x0B
98#define DMI_ASSOCIATIVE_48_WAY 0x0C
99#define DMI_ASSOCIATIVE_64_WAY 0x0D
100#define DMI_ASSOCIATIVE_20_WAY 0x0E
101#define SOCKET_POPULATED 0x40
102#define CPU_STATUS_UNKNOWN 0x00
103#define CPU_STATUS_ENABLED 0x01
104
105// Processor Upgrade Definition
106#define P_UPGRADE_UNKNOWN 0x02
107#define P_UPGRADE_NONE 0x06
108#define P_UPGRADE_S1GX 0x16
109#define P_UPGRADE_AM2 0x17
110#define P_UPGRADE_F1207 0x18
111#define P_UPGRADE_G34 0x1A
112#define P_UPGRADE_AM3 0x1B
113#define P_UPGRADE_C32 0x1C
114#define P_UPGRADE_FS1 0x27
115#define P_UPGRADE_FM1 0x29
116#define P_UPGRADE_FM2 0x2A
117
118//----------------------------------------------------------------------------
119// SRAT DEFINITIONS AND MACROS
120//
121//----------------------------------------------------------------------------
122#define NorthbridgeCapabilities 0xE8
123#define DRAMBase0 0x40
124#define MMIOBase0 0x80
125#define TOP_MEM 0xC001001Aul
126#define LOW_NODE_DEVICEID 24
127#define LOW_APICID 0
128
129
130// Miscellaneous AMD related values
131#define MAX_NUMBER_NODES 8
132
133// Flags
134#define ENABLED 1 // Bit 0
135#define DISABLED 0 // Bit 0
136#define HOTPLUGGABLE 2 // Bit 1
137
138// Affinity Entry Structures
139#define AE_APIC 0
140#define AE_MEMORY 1
141
142
143// Memory Types
144#define TYPE_MEMORY 1
145#define TYPE_RESERVED 2
146#define TYPE_ACPI 3
147#define TYPE_NVS 4
148
149//----------------------------------------------------------------------------
150// SLIT DEFINITIONS AND MACROS
151//
152//----------------------------------------------------------------------------
153#define PROBE_FILTER_CTRL_REG 0x1D4
154#define AMD_ACPI_SLIT_SOCKET_NUM_LENGTH 8
155
156//----------------------------------------------------------------------------
157// CDIT DEFINITIONS AND MACROS
158//
159//----------------------------------------------------------------------------
160#define AMD_ACPI_CDIT_NUM_DOMAINS_LENGTH 4 // Num domains is a 4-bytes unsigned integer
161
162
163//----------------------------------------------------------------------------
164// P-STATE DEFINITIONS AND MACROS
165//
166//----------------------------------------------------------------------------
167//-------------------------------------
168// ERROR Codes
169//-------------------------------------
170#define NO_ERROR 0x0
171#define USER_DISABLE_ERROR 0x01 // User disabled SSDT generation
172#define CORES_MISSMATCH_PSS_ERROR 0x02 // No PSS match
173#define PNOW_SUPPORT_ERROR 0x04 // One of the Cores do not support PNOW!
174#define PWR_FREQ_MATCH_ERROR 0x08 // FREQ and PWR mismatch
175#define NO_PSS_SIZE_ERROR 0x10 // Error in PSS Size
176#define INVALID_PSTATE_ERROR 0x20 // Invalid Max or only 1 P-State available
177#define NO_PSS_ENTRY 0x0FFFFul
178#define INVALID_FREQ 0x0FFFFFFFFul
179
180//-------------------------
181// Default definitions
182// AMD BKDG default values
183//-------------------------
184#define DEFAULT_ISOCH_RELIEF_TIME IRT_80uS
185#define DEFAULT_RAMP_VOLTAGE_OFFSET RVO_50mV
186#define DEFAULT_MAX_VOLTAGE_STEP MVS_25mV
187#define DEFAULT_PERF_PRESENT_CAP 0 // default for Desktop
188#define DEFAULT_VOLTAGE_STABLE_TIME (100 / 20) // 100uS
189#define DEFAULT_PLL_LOCK_TIME 2 // 2uS
190#define DEFAULT_TRANSITION_LATENCY 100 // 100uS
191#define DEFAULT_BUS_MASTER_LATENCY 9 // 9uS
192#define DEFAULT_CPU_SCOPE_NUMBER "0UPC"
193
194// Defines for Common ACPI
195// -----------------------------
196#define SCOPE_OPCODE 0x10
197#define NAME_OPCODE 0x08
198#define METHOD_OPCODE 0x14
199#define PACKAGE_OPCODE 0x12
200#define BUFFER_OPCODE 0x11
201#define BYTE_PREFIX_OPCODE 0x0A
202#define WORD_PREFIX_OPCODE 0x0B
203#define DWORD_PREFIX_OPCODE 0x0C
204#define RETURN_OPCODE 0xA4
205#define ACPI_BUFFER 0x080A0B11ul
206
207// Generic Register Descriptor (GDR) Fields
208#define GDR_ASI_SYSTEM_IO 0x01 // Address Space ID
209#define GDR_ASZ_BYTE_ACCESS 0x01 // Address Size
210
211// Defines for ACPI Scope Table
212// ----------------------------
213#define SCOPE_LENGTH (SCOPE_STRUCT_SIZE + \
214 PCT_STRUCT_SIZE + \
215 PSS_HEADER_STRUCT_SIZE + \
216 PSS_BODY_STRUCT_SIZE + \
217 PPC_HEADER_BODY_STRUCT_SIZE)
218#define SCOPE_VALUE1 0x5C
219#define SCOPE_VALUE2 0x2E
220#define SCOPE_NAME__ '_'
221#define SCOPE_NAME_P 'P'
222#define SCOPE_NAME_R 'R'
223#define SCOPE_NAME_S 'S'
224#define SCOPE_NAME_B 'B'
225#define SCOPE_NAME_C 'C'
226#define SCOPE_NAME_U 'U'
227#define SCOPE_NAME_0 '0'
228#define SCOPE_NAME_1 '1'
229#define SCOPE_NAME_2 '2'
230#define SCOPE_NAME_3 '3'
231#define SCOPE_NAME_A 'A'
232
233#ifdef OEM_SCOPE_NAME
234 #if (OEM_SCOPE_NAME > 'Z') || (OEM_SCOPE_NAME < 'A')
235 #error "OEM_SCOPE_NAME: it should be only one char long AND a valid letter (A~Z)"
236 #endif
237 #define SCOPE_NAME_VALUE OEM_SCOPE_NAME
238#else
Angel Ponsdb2e1182020-05-22 21:34:10 +0200[diff] [blame]239 #define SCOPE_NAME_VALUE SCOPE_NAME_P
zbao7d94cf92012-07-02 14:19:14 +0800[diff] [blame]240#endif // OEM_SCOPE_NAME
241
242#ifdef OEM_SCOPE_NAME1
243 #if (!(((OEM_SCOPE_NAME1 >= 'A') && (OEM_SCOPE_NAME1 <= 'Z')) || \
244 ((OEM_SCOPE_NAME1 >= '0') && (OEM_SCOPE_NAME1 <= '9')) || \
245 (OEM_SCOPE_NAME1 == '_')))
246 #error "OEM_SCOPE_NAME1: it should be only one char long AND a valid letter (0~9, A~F)"
247 #endif
248 #define SCOPE_NAME_VALUE1 OEM_SCOPE_NAME1
249#else
250 #define SCOPE_NAME_VALUE1 SCOPE_NAME_0
251#endif // OEM_SCOPE_NAME
252
253// Defines for PCT Control and Status Table
254// ----------------------------------------
255#define PCT_NAME__ '_'
256#define PCT_NAME_P 'P'
257#define PCT_NAME_C 'C'
258#define PCT_NAME_T 'T'
259#define PCT_VALUE1 0x11022C12ul
260#define PCT_VALUE2 0x0A14
261#define PCT_VALUE3 0x11
262#define GENERIC_REG_DESCRIPTION 0x82
263#define PCT_LENGTH 0x0C
264#define PCT_ADDRESS_SPACE_ID 0x7F
265#define PCT_REGISTER_BIT_WIDTH 0x40
266#define PCT_REGISTER_BIT_OFFSET 0x00
267#define PCT_RESERVED 0x00
268#define PCT_CONTROL_REG_LO 0xC0010062ul
269#define PCT_CONTROL_REG_HI 0x00
270#define PCT_VALUE4 0x14110079ul
271#define PCT_VALUE5 0x110A
272#define PCT_STATUS_REG_LO 0x00
273#define PCT_STATUS_REG_HI 0x00
274#define PCT_VALUE6 0x0079
275
276
277// Defines for PSS Header Table
278// ----------------------------
279#define PSS_NAME__ '_'
280#define PSS_NAME_X 'X'
281#define PSS_NAME_P 'P'
282#define PSS_NAME_S 'S'
283#define PSS_LENGTH (sizeof pssBodyStruct + 3)
284#define NUM_OF_ITEMS_IN_PSS 0x00
285
286
287// Defines for PSS Header Table
288// ----------------------------
289#define PSS_PKG_LENGTH 0x20 // PSS_BODY_STRUCT_SIZE - 1
290#define PSS_NUM_OF_ELEMENTS 0x06
291#define PSS_FREQUENCY 0x00
292#define PSS_POWER 0x00
293#define PSS_TRANSITION_LATENCY DEFAULT_TRANSITION_LATENCY
294#define PSS_BUS_MASTER_LATENCY DEFAULT_BUS_MASTER_LATENCY
295#define PSS_CONTROL ((DEFAULT_ISOCH_RELIEF_TIME << 30) + \
296 (DEFAULT_RAMP_VOLTAGE_OFFSET << 28) + \
297 (DEFAULT_EXT_TYPE << 27) + \
298 (DEFAULT_PLL_LOCK_TIME << 20) + \
299 (DEFAULT_MAX_VOLTAGE_STEP << 18) + \
300 (DEFAULT_VOLTAGE_STABLE_TIME << 11) + \
301 (PSS_VID << 6) + PSS_FID)
302#define PSS_STATUS (DEFAULT_EXTENDED_TYPE << 11) + (PSS_VID << 6) + (PSS_FID)
303
304// Defines for XPSS Header Table
305// ----------------------------
306#define XPSS_PKG_LENGTH 0x47 // XPSS_BODY_STRUCT_SIZE - 1
307#define XPSS_NUM_OF_ELEMENTS 0x08
308#define XPSS_ACPI_BUFFER 0x080A0B11ul
309
310
311// Defines for PPC Header Table
312// ----------------------------
313#define PPC_NAME__ '_'
314#define PPC_NAME_P 'P'
315#define PPC_NAME_C 'C'
316#define PPC_NAME_V 'V'
317#define PPC_METHOD_FLAGS 0x00;
318#define PPC_VALUE1 0x0A;
319
320// Defines for PSD Header Table
321// ----------------------------
322#define PSD_NAME__ '_'
323#define PSD_NAME_P 'P'
324#define PSD_NAME_S 'S'
325#define PSD_NAME_D 'D'
326#define PSD_HEADER_LENGTH (PSD_BODY_STRUCT_SIZE + 2)
327#define PSD_VALUE1 0x01
328
329
330// Defines for PSD Header Table
331// ----------------------------
332#define PSD_PKG_LENGTH (PSD_BODY_STRUCT_SIZE - 1)
333#define NUM_OF_ENTRIES 0x05
334#define PSD_NUM_OF_ENTRIES 0x05
335#define PSD_REVISION 0x00
336#define PSD_DEPENDENCY_DOMAIN 0x00
337#define PSD_COORDINATION_TYPE_HW_ALL 0xFE
338#define PSD_COORDINATION_TYPE_SW_ANY 0xFD
339#define PSD_COORDINATION_TYPE_SW_ALL 0xFC
340#define PSD_NUM_OF_PROCESSORS 0x01
341#define PSD_CORE_NUM_PER_COMPUTE_UNIT 0x02
342#define PSD_DOMAIN_COMPUTE_UNIT_MASK 0x7F
343
344
345#define CUSTOM_PSTATE_FLAG 0x55
346#define PSTATE_FLAG_1 0x55
347#define TARGET_PSTATE_FLAG 0xAA
348#define PSTATE_FLAG_2 0xAA
349
350/*----------------------------------------------------------------------------------------
351 * T Y P E D E F S, S T R U C T U R E S, E N U M S
352 *----------------------------------------------------------------------------------------
353 */
354//----------------------------------------------------------------------------
355// ACPI P-States AML TYPEDEFS, STRUCTURES, ENUMS
356//
357//----------------------------------------------------------------------------
358
359//--------------------------------------------
360// AML code definition
361// (Scope)
362//---------------------------------------------
363/// SCOPE
364typedef struct _SCOPE {
365 UINT8 ScopeOpcode; ///< Opcode
366 UINT16 ScopeLength; ///< Scope Length
367 UINT8 ScopeValue1; ///< Value1
368 UINT8 ScopeValue2; ///< Value2
369 UINT8 ScopeNamePt1a__; ///< Name Pointer
370 UINT8 ScopeNamePt1a_P; ///< Name Pointer
371 UINT8 ScopeNamePt1a_R; ///< Name Pointer
372 UINT8 ScopeNamePt1b__; ///< Name Pointer
373 UINT8 ScopeNamePt2a_C; ///< Name Pointer
374 UINT8 ScopeNamePt2a_P; ///< Name Pointer
375 UINT8 ScopeNamePt2a_U; ///< Name Pointer
376 UINT8 ScopeNamePt2a_0; ///< Name Pointer
377} SCOPE;
378#define SCOPE_STRUCT_SIZE 13 // 13 Bytes
379
380//--------------------------------------------
381// AML code definition
382// (PCT Header and Body)
383//---------------------------------------------
384
385///Performance Control Header
386typedef struct _PCT_HEADER_BODY {
387 UINT8 NameOpcode; ///< Opcode
388 UINT8 PctName_a__; ///< String "_"
389 UINT8 PctName_a_P; ///< String "P"
390 UINT8 PctName_a_C; ///< String "C"
391 UINT8 PctName_a_T; ///< String "T"
392 UINT32 Value1; ///< Value1
393 UINT16 Value2; ///< Value2
394 UINT8 Value3; ///< Value3
395 UINT8 GenericRegDescription1; ///< Generic Reg Description
396 UINT16 Length1; ///< Length1
397 UINT8 AddressSpaceId1; ///< PCT Address Space ID
398 UINT8 RegisterBitWidth1; ///< PCT Register Bit Width
399 UINT8 RegisterBitOffset1; ///< PCT Register Bit Offset
400 UINT8 Reserved1; ///< Reserved
401 UINT32 ControlRegAddressLo; ///< Control Register Address Low
402 UINT32 ControlRegAddressHi; ///< Control Register Address High
403 UINT32 Value4; ///< Value4
404 UINT16 Value5; ///< Value 5
405 UINT8 GenericRegDescription2; ///< Generic Reg Description
406 UINT16 Length2; ///< Length2
407 UINT8 AddressSpaceId2; ///< PCT Address Space ID
408 UINT8 RegisterBitWidth2; ///< PCT Register Bit Width
409 UINT8 RegisterBitOffset2; ///< PCT Register Bit Offset
410 UINT8 Reserved2; ///< Reserved
411 UINT32 StatusRegAddressLo; ///< Control Register Address Low
412 UINT32 StatusRegAddressHi; ///< Control Register Address High
413 UINT16 Value6; ///< Values
414} PCT_HEADER_BODY;
415#define PCT_STRUCT_SIZE 50 // 50 Bytes
416
417
418//--------------------------------------------
419// AML code definition
420// (PSS Header)
421//--------------------------------------------
422///Performance Supported States Header
423typedef struct _PSS_HEADER {
424 UINT8 NameOpcode; ///< Opcode
425 UINT8 PssName_a__; ///< String "_"
426 UINT8 PssName_a_P; ///< String "P"
427 UINT8 PssName_a_S; ///< String "S"
428 UINT8 PssName_b_S; ///< String "S"
429 UINT8 PkgOpcode; ///< Package Opcode
430 UINT16 PssLength; ///< PSS Length
431 UINT8 NumOfItemsInPss; ///< Number of Items in PSS
432} PSS_HEADER;
433#define PSS_HEADER_STRUCT_SIZE 9 // 9 Bytes
434
435
436//--------------------------------------------
437// AML code definition
438// (PSS Body)
439//--------------------------------------------
440///Performance Supported States Body
441typedef struct _PSS_BODY {
442 UINT8 PkgOpcode; ///< Package Opcode
443 UINT8 PkgLength; ///< Package Length
444 UINT8 NumOfElements; ///< Number of Elements
445 UINT8 DwordPrefixOpcode1; ///< Prefix Opcode1
446 UINT32 Frequency; ///< Frequency
447 UINT8 DwordPrefixOpcode2; ///< Prefix Opcode2
448 UINT32 Power; ///< Power
449 UINT8 DwordPrefixOpcode3; ///< Prefix Opcode3
450 UINT32 TransitionLatency; ///< Transition Latency
451 UINT8 DwordPrefixOpcode4; ///< Prefix Opcode4
452 UINT32 BusMasterLatency; ///< Bus Master Latency
453 UINT8 DwordPrefixOpcode5; ///< Prefix Opcode5
454 UINT32 Control; ///< Control
455 UINT8 DwordPrefixOpcode6; ///< Prefix Opcode6
456 UINT32 Status; ///< Status
457} PSS_BODY;
458#define PSS_BODY_STRUCT_SIZE 33 // 33 Bytes
459
460
461/*--------------------------------------------
462 * AML code definition
463 * (XPSS Header)
464 *--------------------------------------------
465 */
466/// Extended PSS Header
467typedef struct _XPSS_HEADER {
468 UINT8 NameOpcode; ///< 08h
469 UINT8 XpssName_a_X; ///< String "X"
470 UINT8 XpssName_a_P; ///< String "P"
471 UINT8 XpssName_a_S; ///< String "S"
472 UINT8 XpssName_b_S; ///< String "S"
473 UINT8 PkgOpcode; ///< 12h
474 UINT16 XpssLength; ///< XPSS Length
475 UINT8 NumOfItemsInXpss; ///< Number of Items in XPSS
476} XPSS_HEADER;
477#define XPSS_HEADER_STRUCT_SIZE 9 // 9 Bytes
478
479/*--------------------------------------------
480 * AML code definition
481 * (XPSS Body)
482 *--------------------------------------------
483 */
484/// Extended PSS Body
485typedef struct _XPSS_BODY {
486 UINT8 PkgOpcode; ///< 12h
487 UINT8 PkgLength; ///< Package Length
488 UINT8 XpssValueTbd; ///< XPSS Value
489 UINT8 NumOfElements; ///< Number of Elements
490 UINT8 DwordPrefixOpcode1; ///< Prefix Opcode1
491 UINT32 Frequency; ///< Frequency
492 UINT8 DwordPrefixOpcode2; ///< Prefix Opcode2
493 UINT32 Power; ///< Power
494 UINT8 DwordPrefixOpcode3; ///< Prefix Opcode3
495 UINT32 TransitionLatency; ///< Transition Latency
496 UINT8 DwordPrefixOpcode4; ///< Prefix Opcode4
497 UINT32 BusMasterLatency; ///< Bus Master Latency
498 UINT32 ControlBuffer; ///< Control Buffer
499 UINT32 ControlLo; ///< Control Low
500 UINT32 ControlHi; ///< Control High
501 UINT32 StatusBuffer; ///< Status Buffer
502 UINT32 StatusLo; ///< Status Low
503 UINT32 StatusHi; ///< Status High
504 UINT32 ControlMaskBuffer; ///< Control Mask Buffer
505 UINT32 ControlMaskLo; ///< Control Mask Low
506 UINT32 ControlMaskHi; ///< Control Mask High
507 UINT32 StatusMaskBuffer; ///< Status Mask Buffer
508 UINT32 StatusMaskLo; ///< Status Mask Low
509 UINT32 StatusMaskHi; ///< Status Mask High
510} XPSS_BODY;
511#define XPSS_BODY_STRUCT_SIZE 72 // 72 Bytes
512
513/*--------------------------------------------
514 * AML code definition
515 * (PPC Header and Body)
516 *--------------------------------------------
517 */
518/// Performance Present Capabilities Header
519typedef struct _PPC_HEADER_BODY {
520 UINT8 NameOpcode; ///< Name Opcode
521 UINT8 PpcName_a_P; ///< String "P"
522 UINT8 PpcName_b_P; ///< String "P"
523 UINT8 PpcName_a_C; ///< String "C"
524 UINT8 PpcName_a_V; ///< String "V"
525 UINT8 Value1; ///< Value
526 UINT8 DefaultPerfPresentCap; ///< Default Perf Present Cap
527 UINT8 MethodOpcode; ///< Method Opcode
528 UINT8 PpcLength; ///< Method Length
529 UINT8 PpcName_a__; ///< String "_"
530 UINT8 PpcName_c_P; ///< String "P"
531 UINT8 PpcName_d_P; ///< String "P"
532 UINT8 PpcName_b_C; ///< String "C"
533 UINT8 MethodFlags; ///< Method Flags
534 UINT8 ReturnOpcode; ///< Return Opcoce
535 UINT8 PpcName_e_P; ///< String "P"
536 UINT8 PpcName_f_P; ///< String "P"
537 UINT8 PpcName_c_C; ///< String "C"
538 UINT8 PpcName_b_V; ///< String "V"
539
540} PPC_HEADER_BODY;
541#define PPC_HEADER_BODY_STRUCT_SIZE 19 // 19 Bytes
542#define PPC_METHOD_LENGTH 11 // 11 Bytes
543
544
545/*--------------------------------------------
546 * AML code definition
547 * (PSD Header)
548 *--------------------------------------------
549 */
550/// P-State Dependency Header
551typedef struct _PSD_HEADER {
552 UINT8 NameOpcode; ///< Name Opcode
553 UINT8 PsdName_a__; ///< String "_"
554 UINT8 PsdName_a_P; ///< String "P"
555 UINT8 PsdName_a_S; ///< String "S"
556 UINT8 PsdName_a_D; ///< String "D"
557 UINT8 PkgOpcode; ///< Package Opcode
558 UINT8 PsdLength; ///< PSD Length
559 UINT8 Value1; ///< Value
560} PSD_HEADER;
561#define PSD_HEADER_STRUCT_SIZE 8 // 8 Bytes
562
563/*--------------------------------------------
564 * AML code definition
565 * (PSD Body)
566 *--------------------------------------------
567 */
568/// P-State Dependency Body
569typedef struct _PSD_BODY {
570 UINT8 PkgOpcode; ///< Package Opcode
571 UINT8 PkgLength; ///< Package Length
572 UINT8 NumOfEntries; ///< Number of Entries
573 UINT8 BytePrefixOpcode1; ///< Prefix Opcode1 in Byte
574 UINT8 PsdNumOfEntries; ///< PSD Number of Entries
575 UINT8 BytePrefixOpcode2; ///< Prefix Opcode2 in Byte
576 UINT8 PsdRevision; ///< PSD Revision
577 UINT8 DwordPrefixOpcode1; ///< Prefix Opcode1 in DWord
578 UINT32 DependencyDomain; ///< Dependency Domain
579 UINT8 DwordPrefixOpcode2; ///< Prefix Opcode2 in DWord
580 UINT32 CoordinationType; ///< (0xFC = SW_ALL, 0xFD = SW_ANY, 0xFE = HW_ALL)
581 UINT8 DwordPrefixOpcode3; ///< Prefix Opcode3 in DWord
582 UINT32 NumOfProcessors; ///< Number of Processors
583} PSD_BODY;
584#define PSD_BODY_STRUCT_SIZE 22 // 22 Bytes
585
586//----------------------------------------------------------------------------
587// WHEA TYPEDEFS, STRUCTURES, ENUMS
588//
589//----------------------------------------------------------------------------
590
591/// HEST MCE TABLE
592typedef struct _AMD_HEST_MCE_TABLE {
593 UINT16 TblLength; ///< Length, in bytes, of entire AMD_HEST_MCE structure.
594 UINT32 GlobCapInitDataLSD; ///< Holds the value that the OS will program into
595 UINT32 GlobCapInitDataMSD; ///< the machine check global capability register(MCG_CAP).
596 UINT32 GlobCtrlInitDataLSD; ///< Holds the value that the OS will program into
597 UINT32 GlobCtrlInitDataMSD; ///< the machine check global control register(MCG_CTL).
598 UINT8 NumHWBanks; ///< The number of hardware error reporting banks.
599 UINT8 Rsvd[7]; ///< reserve 7 bytes as spec's required
600} AMD_HEST_MCE_TABLE;
601
602/// HEST CMC TABLE
603typedef struct _AMD_HEST_CMC_TABLE {
604 UINT16 TblLength; ///< Length, in bytes, of entire AMD_HEST_CMC structure.
605 UINT8 NumHWBanks; ///< The number of hardware error reporting banks.
606 UINT8 Rsvd[3]; ///< reserve 3 bytes as spec's required
607} AMD_HEST_CMC_TABLE;
608
609/// HEST BANK
610typedef struct _AMD_HEST_BANK {
611 UINT8 BankNum; ///< Zero-based index identifies the machine check error bank.
612 UINT8 ClrStatusOnInit; ///< Indicates if the status information in this machine check bank
613 ///< is to be cleared during system initialization.
614 UINT8 StatusDataFormat; ///< Indicates the format of the data in the status register
615 UINT8 ConfWriteEn; ///< This field indicates whether configuration parameters may be
616 ///< modified by the OS. If the bit for the associated parameter is
617 ///< set, the parameter is writable by the OS.
618 UINT32 CtrlRegMSRAddr; ///< Address of the hardware bank's control MSR. Ignored if zero.
619
620 UINT32 CtrlInitDataLSD; ///< This is the value the OS will program into the machine check
621 UINT32 CtrlInitDataMSD; ///< bank's control register
622 UINT32 StatRegMSRAddr; ///< Address of the hardware bank's MCi_STAT MSR. Ignored if zero.
623 UINT32 AddrRegMSRAddr; ///< Address of the hardware bank's MCi_ADDR MSR. Ignored if zero.
624 UINT32 MiscRegMSRAddr; ///< Address of the hardware bank's MCi_MISC MSR. Ignored if zero.
625} AMD_HEST_BANK;
626
627/// Initial data of AMD_HEST_BANK
628typedef struct _AMD_HEST_BANK_INIT_DATA {
629 UINT32 CtrlInitDataLSD; ///< Initial data of CtrlInitDataLSD
630 UINT32 CtrlInitDataMSD; ///< Initial data of CtrlInitDataMSD
631 UINT32 CtrlRegMSRAddr; ///< Initial data of CtrlRegMSRAddr
632 UINT32 StatRegMSRAddr; ///< Initial data of StatRegMSRAddr
633 UINT32 AddrRegMSRAddr; ///< Initial data of AddrRegMSRAddr
634 UINT32 MiscRegMSRAddr; ///< Initial data of MiscRegMSRAddr
635} AMD_HEST_BANK_INIT_DATA;
636
637/// MSR179 Global Machine Check Capabilities data struct
638typedef struct _MSR_MCG_CAP_STRUCT {
639 UINT64 Count:8; ///< Indicates the number of
640 ///< error-reporting banks visible to each core
641 UINT64 McgCtlP:1; ///< 1=The machine check control registers
642 UINT64 Rsvd:55; ///< reserved
643} MSR_MCG_CAP_STRUCT;
644
645/// Initial data of WHEA
646typedef struct _AMD_WHEA_INIT_DATA {
647 UINT32 GlobCapInitDataLSD; ///< Holds the value that the OS will program into the machine
648 UINT32 GlobCapInitDataMSD; ///< Check global capability register
649 UINT32 GlobCtrlInitDataLSD; ///< Holds the value that the OS will grogram into the machine
650 UINT32 GlobCtrlInitDataMSD; ///< Check global control register
651 UINT8 ClrStatusOnInit; ///< Indicates if the status information in this machine check
652 ///< bank is to be cleared during system initialization
653 UINT8 StatusDataFormat; ///< Indicates the format of the data in the status register
654 UINT8 ConfWriteEn; ///< This field indicates whether configuration parameters may be
655 ///< modified by the OS. If the bit for the associated parameter is
656 ///< set, the parameter is writable by the OS.
657 UINT8 HestBankNum; ///< Number of HEST Bank
658 AMD_HEST_BANK_INIT_DATA *HestBankInitData; ///< Pointer to Initial data of HEST Bank
659} AMD_WHEA_INIT_DATA;
660
661//----------------------------------------------------------------------------
662// DMI TYPEDEFS, STRUCTURES, ENUMS
663//
664//----------------------------------------------------------------------------
665/// DMI brand information
666typedef struct {
667 UINT16 String1:4; ///< String1
668 UINT16 String2:4; ///< String2
669 UINT16 Model:7; ///< Model
670 UINT16 Pg:1; ///< Page
671} BRAND_ID;
672
673/// DMI cache information
674typedef struct {
675 UINT32 L1CacheSize; ///< L1 cache size
676 UINT8 L1CacheAssoc; ///< L1 cache associativity
677 UINT32 L2CacheSize; ///< L2 cache size
678 UINT8 L2CacheAssoc; ///< L2 cache associativity
679 UINT32 L3CacheSize; ///< L3 cache size
680 UINT8 L3CacheAssoc; ///< L3 cache associativity
681} CPU_CACHE_INFO;
682
683/// DMI processor information
684typedef struct {
685 UINT8 ExtendedFamily; ///< Extended Family
686 UINT8 ExtendedModel; ///< Extended Model
687 UINT8 BaseFamily; ///< Base Family
688 UINT8 BaseModel; ///< Base Model
689 UINT8 Stepping; ///< Stepping
690 UINT8 PackageType; ///< PackageType
691 BRAND_ID BrandId; ///< BrandId which contains information about String1, String2, Model and Page
692 UINT8 TotalCoreNumber; ///< Number of total cores
693 UINT8 EnabledCoreNumber; ///< Number of enabled cores
694 UINT8 ProcUpgrade; ///< ProcUpdrade
695 CPU_CACHE_INFO CacheInfo; ///< CPU cache info
696} CPU_TYPE_INFO;
697
698/// A structure containing processor name string and
699/// the value that should be provide to DMI type 4 processor family
700typedef struct {
701 IN CONST CHAR8 *Stringstart; ///< The literal string
702 IN UINT8 T4ProcFamilySetting; ///< The value set to DMI type 4 processor family
703} CPU_T4_PROC_FAMILY;
704
705/// DMI ECC information
706typedef struct {
707 BOOLEAN EccCapable; ///< ECC Capable
708} CPU_GET_MEM_INFO;
709
710/* Transfer vectors for DMI family specific routines */
711typedef VOID OPTION_DMI_GET_CPU_INFO (
712 IN OUT CPU_TYPE_INFO *CpuInfoPtr,
713 IN AMD_CONFIG_PARAMS *StdHeader
714 );
715
716typedef VOID OPTION_DMI_GET_PROC_FAMILY (
717 IN OUT UINT8 *T4ProcFamily,
718 IN PROC_FAMILY_TABLE *CpuDmiProcFamilyTable,
719 IN CPU_TYPE_INFO *CpuInfo,
720 IN AMD_CONFIG_PARAMS *StdHeader
721 );
722
723typedef UINT8 OPTION_DMI_GET_VOLTAGE (
724 IN AMD_CONFIG_PARAMS *StdHeader
725 );
726
727typedef UINT16 OPTION_DMI_GET_MAX_SPEED (
728 IN AMD_CONFIG_PARAMS *StdHeader
729 );
730
731typedef UINT16 OPTION_DMI_GET_EXT_CLOCK (
732 IN AMD_CONFIG_PARAMS *StdHeader
733 );
734
735typedef VOID OPTION_DMI_GET_MEM_INFO (
736 IN OUT CPU_GET_MEM_INFO *CpuGetMemInfoPtr,
737 IN AMD_CONFIG_PARAMS *StdHeader
738 );
739
740/// Brand table entry format
741typedef struct {
742 UINT8 PackageType; ///< Package type
743 UINT8 PgOfBrandId; ///< Page
744 UINT8 NumberOfCores; ///< Number of cores
745 UINT8 String1ofBrandId; ///< String1
746 UINT8 ValueSetToDmiTable; ///< The value which will should be set to DMI table
747} DMI_BRAND_ENTRY;
748
749/// Family specific data table structure
750struct _PROC_FAMILY_TABLE {
751 UINT64 ProcessorFamily; ///< processor
752 OPTION_DMI_GET_CPU_INFO *DmiGetCpuInfo; ///< transfer vectors
753 OPTION_DMI_GET_PROC_FAMILY *DmiGetT4ProcFamily; ///< Get DMI type 4 processor family information
754 OPTION_DMI_GET_VOLTAGE *DmiGetVoltage; ///< vector for reading voltage
755 OPTION_DMI_GET_MAX_SPEED *DmiGetMaxSpeed; ///< vector for reading speed
756 OPTION_DMI_GET_EXT_CLOCK *DmiGetExtClock; ///< vector for reading external clock speed
757 OPTION_DMI_GET_MEM_INFO *DmiGetMemInfo; ///< Get memory information
758 UINT8 LenBrandList; ///< size of brand table
759 CONST DMI_BRAND_ENTRY *DmiBrandList; ///< translate brand info to DMI identifier
760};
761
762//----------------------------------------------------------------------------
763// SLIT TYPEDEFS, STRUCTURES, ENUMS
764//
765//----------------------------------------------------------------------------
766/// Format for SRAT Header
767typedef struct {
768 UINT8 Sign[4]; ///< Signature
769 UINT32 TableLength; ///< Table Length
770 UINT8 Revision; ///< Revision
771 UINT8 Checksum; ///< Checksum
772 UINT8 OemId[6]; ///< OEM ID
773 UINT8 OemTableId[8]; ///< OEM Tabled ID
774 UINT32 OemRev; ///< OEM Revision
775 UINT8 CreatorId[4]; ///< Creator ID
776 UINT32 CreatorRev; ///< Creator Revision
777} ACPI_TABLE_HEADER;
778
779//----------------------------------------------------------------------------
780// SRAT TYPEDEFS, STRUCTURES, ENUMS
781//
782//----------------------------------------------------------------------------
783/// Format for SRAT Header
784typedef struct _CPU_SRAT_HEADER {
785 UINT8 Sign[4]; ///< Signature
786 UINT32 TableLength; ///< Table Length
787 UINT8 Revision; ///< Revision
788 UINT8 Checksum; ///< Checksum
789 UINT8 OemId[6]; ///< OEM ID
790 UINT8 OemTableId[8]; ///< OEM Tabled ID
791 UINT32 OemRev; ///< OEM Revision
792 UINT8 CreatorId[4]; ///< Creator ID
793 UINT32 CreatorRev; ///< Creator Revision
794 UINT32 TableRev; ///< Table Revision
795 UINT8 Reserved[8]; ///< Reserved
796} CPU_SRAT_HEADER;
797
798
799/// Format for SRAT APIC Affinity Entry
800typedef struct _CPU_SRAT_APIC_ENTRY {
801 UINT8 Type; ///< Type
802 UINT8 Length; ///< Length
803 UINT8 Domain; ///< Domain
804 UINT8 ApicId; ///< Apic ID
805 UINT32 Flags; ///< Flags
806 UINT8 LSApicEid; ///< Local SAPIC EID
807 UINT8 Reserved[7]; ///< Reserved
808} CPU_SRAT_APIC_ENTRY;
809
810
811/// Format for SRAT Memory Affinity Entry
812typedef struct _CPU_SRAT_MEMORY_ENTRY {
813 UINT8 Type; ///< 0: Memory affinity = 1
814 UINT8 Length; ///< 1: Length = 40 bytes
815 UINT32 Domain; ///< 2: Proximity domain
816 UINT8 Reserved1[2]; ///< 6: Reserved
817 UINT32 BaseAddrLow; ///< 8: Low 32bits address base
818 UINT32 BaseAddrHigh; ///< 12: High 32bits address base
819 UINT32 LengthAddrLow; ///< 16: Low 32bits address limit
820 UINT32 LengthAddrHigh; ///< 20: High 32bits address limit
821 UINT8 Reserved2[4]; ///< 24: Memory Type
822 UINT32 Flags; ///< 28: Flags
823 UINT8 Reserved3[8]; ///< 32: Reserved
824} CPU_SRAT_MEMORY_ENTRY;
825
826//----------------------------------------------------------------------------
827// CRAT TYPEDEFS, STRUCTURES, ENUMS
828// Component Resource Affinity Table
829//----------------------------------------------------------------------------
830/// Format for CRAT Header
831typedef struct {
832 UINT8 Sign[4]; ///< CRAT, Signature for the Component Resource Affinity Table.
833 UINT32 Length; ///< Length, in bytes, of the entire CRAT
834 UINT8 Revision; ///< 0
835 UINT8 Checksum; ///< Entire table must sum to zero.
836 UINT8 OemId[6]; ///< OEM ID
837 UINT8 OemTableId[8]; ///< OEM Tabled ID
838 UINT32 OemRev; ///< OEM Revision
839 UINT8 CreatorId[4]; ///< Creator ID
840 UINT32 CreatorRev; ///< Creator Revision
841 UINT32 TotalEntries; ///< total number[n] of entries in the CRAT
842 UINT16 NumDomains; ///< Number of HSA proximity domains
843 UINT8 Reserved[6]; ///< Reserved
844} CRAT_HEADER;
845
846/// Flags field of the CRAT HSA Processing Unit Affinity Structure
847typedef struct {
848 UINT32 Enabled:1; ///< Enabled
849 UINT32 HotPluggable:1; ///< Hot Pluggable
850 UINT32 CpuPresent:1; ///< Cpu Present
851 UINT32 GpuPresent:1; ///< Gpu Present
852 UINT32 IommuPresent:1; ///< IOMMU Present
853 UINT32 :27; ///< Reserved
854} CRAT_HSA_PROCESSING_UNIT_FLAG;
855
856/// CRAT HSA Processing Unit Affinity Structure
857typedef struct {
858 UINT8 Type; ///< 0 - CRAT HSA Processing Unit Structure
859 UINT8 Length; ///< 40
860 UINT16 Reserved; ///< Reserved
861 CRAT_HSA_PROCESSING_UNIT_FLAG Flags; ///< Flags - HSA Processing Unit Affinity Structure
862 UINT32 ProximityDomain; ///< Integer that represents the proximity domain to which the node belongs to
863 UINT32 ProcessorIdLow; ///< Low value of the logical processor included in this HSA proximity domain
864 UINT16 CpuCoreCount; ///< Indicates overall count of x86(-64) -compatible execution units (CPU cores) are present in this (APU-) node (identifiable by SW).
865 UINT16 SimdCount; ///< Indicates overall count of GPU SIMDs present in this node (identifiable by SW).
866 UINT16 SimdWidth; ///< "Width" of a single SIMD unit. SIMDCount*SIMDWidth determines the total number of non-x86 execution units.
867 UINT16 IoCount; ///< Number of discoverable IO Interfaces connecting this node to other components.
868 UINT8 Reserved1[16]; ///< Reserved
869} CRAT_HSA_PROCESSING_UNIT;
870
871/// Flags field of the CRAT Memory Affinity Structure
872typedef struct {
873 UINT32 Enabled:1; ///< Enabled
874 UINT32 HotPluggable:1; ///< Hot Pluggable
875 UINT32 NonVolatile:1; ///< If set, the memory region represents Non-Volatile memory
876 UINT32 :29; ///< Reserved
877} CRAT_MEMORY_FLAG;
878
879/// CRAT Memory Affinity Structure
880typedef struct {
881 UINT8 Type; ///< 1 - CRAT Memory Affinity Structure
882 UINT8 Length; ///< 40
883 UINT16 Reserved; ///< Reserved
884 CRAT_MEMORY_FLAG Flags; ///< Flags - Memory Affinity Structure. Indicates whether the region of memory is enabled and can be hot plugged
885 UINT32 ProximityDomain; ///< Integer that represents the proximity domain to which the node belongs to
886 UINT32 BaseAddressLow; ///< Low 32Bits of the Base Address of the memory range
887 UINT32 BaseAddressHigh; ///< High 32Bits of the Base Address of the memory range
888 UINT32 LengthLow; ///< Low 32Bits of the length of the memory range
889 UINT32 LengthHigh; ///< High 32Bits of the length of the memory range
890 UINT32 Width; ///< Memory width - Specifies the number of parallel bits of the memory interface
891 UINT8 Reserved1[8]; ///< Reserved
892} CRAT_MEMORY;
893
894/// Flags field of the CRAT Cache Affinity structure
895typedef struct {
896 UINT32 Enabled:1; ///< Enabled
897 UINT32 DataCache:1; ///< 1 if cache includes data
898 UINT32 InstructionCache:1; ///< 1 if cache includes instructions
899 UINT32 CpuCache:1; ///< 1 if cache is part of CPU functionality
900 UINT32 SimdCache:1; ///< 1 if cache is part of SIMD functionality
901 UINT32 :27; ///< Reserved
902} CRAT_CACHE_FLAG;
903
904/// CRAT Cache Affinity Structure
905typedef struct {
906 UINT8 Type; ///< 2 - CRAT Cache Affinity Structure
907 UINT8 Length; ///< 64
908 UINT16 Reserved; ///< Reserved
909 CRAT_CACHE_FLAG Flags; ///< Flags - Cache Affinity Structure. Indicates whether the region of cache is enabled
910 UINT32 ProcessorIdLow; ///< Low value of a logical processor which includes this component
911 UINT8 SiblingMap[32]; ///< Bitmask of Processor Id sharing this component. 1 bit per logical processor
912 UINT32 CacheSize; ///< Cache size in KB
913 UINT8 CacheLevel; ///< Integer representing level: 1, 2, 3, 4, etc.
914 UINT8 LinesPerTag; ///< Cache Lines per tag
915 UINT16 CacheLineSize; ///< Cache line size in bytes
916 UINT8 Associativity; ///< Cache associativity
917 ///< The associativity fields are encoded as follows:
918 ///< 00h: Reserved.
919 ///< 01h: Direct mapped.
920 ///< 02h-FEh: Associativity. (e.g., 04h = 4-way associative.)
921 ///< FFh: Fully associative
922 UINT8 CacheProperties; ///< Cache Properties bits [2:0] represent Inclusive/Exclusive property encoded.
923 ///< 0: Cache is strictly exclusive to lower level caches.
924 ///< 1: Cache is mostly exclusive to lower level caches.
925 ///< 2: Cache is strictly inclusive to lower level caches.
926 ///< 3: Cache is mostly inclusive to lower level caches.
927 ///< 4: Cache is a "constant cache" (= explicit update)
928 ///< 5: Cache is a "specialty cache" (e.g. Texture cache)
929 ///< 6-7: Reserved
930 ///< CacheProperties bits [7:3] are reserved
931 UINT16 CacheLatency; ///< Cost of time to access cache described in nanoseconds.
932 UINT8 Reserved1[8]; ///< Reserved
933} CRAT_CACHE;
934
935/// Flags field of the CRAT TLB Affinity structure
936typedef struct {
937 UINT32 Enabled:1; ///< Enabled
938 UINT32 DataTLB:1; ///< 1 if TLB includes translation information for data.
939 UINT32 InstructionTLB:1; ///< 1 if TLB includes translation information for instructions.
940 UINT32 CpuTLB:1; ///< 1 if TLB is part of CPU functionality
941 UINT32 SimdTLB:1; ///< 1 if TLB is part of SIMD functionality
942 UINT32 :27; ///< Reserved
943} CRAT_TLB_FLAG;
944
945/// CRAT TLB Affinity Structure
946typedef struct {
947 UINT8 Type; ///< 3 - CRAT TLB Affinity Structure
948 UINT8 Length; ///< 64
949 UINT16 Reserved; ///< Reserved
950 CRAT_TLB_FLAG Flags; ///< Flags - TLB Affinity Structure. Indicates whether the TLB is enabled and defined
951 UINT32 ProcessorIdLow; ///< Low value of a logical processor which includes this component.
952 UINT8 SiblingMap[32]; ///< Bitmask of Processor Id sharing this component. 1 bit per logical processor
953 UINT32 TLBLevel; ///< Integer representing level: 1, 2, 3, 4, etc.
954 UINT8 DataTLBAssociativity2MB; ///< Data TLB associativity for 2MB pages
955 ///< The associativity fields are encoded as follows:
956 ///< 00h: Reserved.
957 ///< 01h: Direct mapped.
958 ///< 02h-FEh: Associativity. (e.g., 04h = 4-way associative.)
959 ///< FFh: Fully associative.
960 UINT8 DataTLBSize2MB; ///< Data TLB number of entries for 2MB.
961 UINT8 InstructionTLBAssoc2MB; ///< Instruction TLB associativity for 2MB pages
962 ///< The associativity fields are encoded as follows:
963 ///< 00h: Reserved.
964 ///< 01h: Direct mapped.
965 ///< 02h-FEh: Associativity. (e.g., 04h = 4-way associative.)
966 ///< FFh: Fully associative.
967 UINT8 InstructionTLBSize2MB; ///< Instruction TLB number of entries for 2MB pages.
968 UINT8 DTLB4KAssoc; ///< Data TLB Associativity for 4KB pages
969 UINT8 DTLB4KSize; ///< Data TLB number of entries for 4KB pages
970 UINT8 ITLB4KAssoc; ///< Instruction TLB Associativity for 4KB pages
971 UINT8 ITLB4KSize; ///< Instruction TLB number of entries for 4KB pages
972 UINT8 DTLB1GAssoc; ///< Data TLB Associativity for 1GB pages
973 UINT8 DTLB1GSize; ///< Data TLB number of entries for 1GB pages
974 UINT8 ITLB1GAssoc; ///< Instruction TLB Associativity for 1GB pages
975 UINT8 ITLB1GSize; ///< Instruction TLB number of entries for 1GB pages
976 UINT8 Reserved1[4]; ///< Reserved
977} CRAT_TLB;
978
979/// Flags field of the CRAT FPU Affinity structure
980typedef struct {
981 UINT32 Enabled:1; ///< Enabled
982 UINT32 :31; ///< Reserved
983} CRAT_FPU_FLAG;
984
985/// CRAT FPU Affinity Structure
986typedef struct {
987 UINT8 Type; ///< 4 - CRAT FPU Affinity Structure
988 UINT8 Length; ///< 64
989 UINT16 Reserved; ///< Reserved
990 CRAT_FPU_FLAG Flags; ///< Flags - FPU Affinity Structure. Indicates whether the region of FPU affinity structure is enabled and defined
991 UINT32 ProcessorIdLow; ///< Low value of a logical processor which includes this component.
992 UINT8 SiblingMap[32]; ///< Bitmask of Processor Id sharing this component. 1 bit per logical processor
993 UINT32 FPUSize; ///< Product specific
994 UINT8 Reserved1[16]; ///< Reserved
995} CRAT_FPU;
996
997/// Flags field of the CRAT IO Affinity structure
998typedef struct {
999 UINT32 Enabled:1; ///< Enabled
1000 UINT32 Coherency:1; ///< If set, IO interface supports coherent transactions (natively or through protocol extensions)
1001 UINT32 :30; ///< Reserved
1002} CRAT_IO_FLAG;
1003
1004/// CRAT IO Affinity Structure
1005typedef struct {
1006 UINT8 Type; ///< 5 - CRAT IO Affinity Structure
1007 UINT8 Length; ///< 64
1008 UINT16 Reserved; ///< Reserved
1009 CRAT_IO_FLAG Flags; ///< Flags - IO Affinity Structure. Indicates whether the region of IO affinity structure is enabled and defined.
1010 UINT32 ProximityDomainFrom; ///< Integer that represents the proximity domain to which the IO Interface belongs to
1011 UINT32 ProximityDomainTo; ///< Integer that represents the other proximity domain to which the IO Interface belongs to
1012 UINT8 IoType; ///< IO Interface type. Values defined are
1013 ///< 0: Undefined
1014 ///< 1: Hypertransport
1015 ///< 2: PCI Express
1016 ///< 3: Other (e.g. internal)
1017 ///< 4-255: Reserved
1018 UINT8 VersionMajor; ///< Major version of the Bus interface
1019 UINT16 VersionMinor; ///< Minor version of the Bus interface ((optional)
1020 UINT32 MinimumLatency; ///< Cost of time to transfer, described in nanoseconds.
1021 UINT32 MaximumLatency; ///< Cost of time to transfer, described in nanoseconds.
1022 UINT32 MinimumBandwidth; ///< Minimum interface Bandwidth in MB/s
1023 UINT32 MaximumBandwidth; ///< Maximum interface Bandwidth in MB/s
1024 UINT32 RecommendedTransferSize; ///< Recommended transfer size to reach maximum interface bandwidth in Bytes
1025 UINT8 Reserved1[24]; ///< Reserved
1026} CRAT_IO;
1027
1028#define CRAT_MAX_LENGTH 0x400ul ///< Reserve 1K for CRAT
1029/// CRAT entry type
1030typedef enum {
1031 CRAT_TYPE_HSA_PROC_UNIT = 0, ///< 0 - CRAT HSA Processing Unit Structure
1032 CRAT_TYPE_MEMORY, ///< 1 - CRAT Memory Affinity Structure
1033 CRAT_TYPE_CACHE, ///< 2 - CRAT Cache Affinity Structure
1034 CRAT_TYPE_TLB, ///< 3 - CRAT TLB Affinity Structure
1035 CRAT_TYPE_FPU, ///< 4 - CRAT FPU Affinity Structure
1036 CRAT_TYPE_IO, ///< 5 - CRAT IO Affinity Structure
1037} CRAT_ENTRY_TYPE;
1038
1039/*----------------------------------------------------------------------------------------
1040 * F U N C T I O N P R O T O T Y P E
1041 *----------------------------------------------------------------------------------------
1042 */
1043
1044AGESA_STATUS
1045AmdCpuLate (
1046 IN AMD_CONFIG_PARAMS *StdHeader,
1047 IN PLATFORM_CONFIGURATION *PlatformConfig
1048 );
1049
1050AGESA_STATUS
1051CreateAcpiWhea (
1052 IN OUT AMD_CONFIG_PARAMS *StdHeader,
1053 IN OUT VOID **WheaMcePtr,
1054 IN OUT VOID **WheaCmcPtr
1055 );
1056
1057AGESA_STATUS
1058CreateDmiRecords (
1059 IN OUT AMD_CONFIG_PARAMS *StdHeader,
1060 IN OUT DMI_INFO **DmiTable
1061 );
1062
1063AGESA_STATUS
1064GetType4Type7Info (
1065 IN AP_EXE_PARAMS *ApExeParams
1066 );
1067
1068VOID
1069DmiGetT4ProcFamilyFromBrandId (
1070 IN OUT UINT8 *T4ProcFamily,
1071 IN PROC_FAMILY_TABLE *CpuDmiProcFamilyTable,
1072 IN CPU_TYPE_INFO *CpuInfo,
1073 IN AMD_CONFIG_PARAMS *StdHeader
1074 );
1075
1076VOID
1077GetNameString (
1078 IN OUT CHAR8 *String,
1079 IN OUT AMD_CONFIG_PARAMS *StdHeader
1080 );
1081
1082BOOLEAN
1083IsSourceStrContainTargetStr (
1084 IN OUT CHAR8 *SourceStr,
1085 IN OUT CONST CHAR8 *TargetStr,
1086 IN OUT AMD_CONFIG_PARAMS *StdHeader
1087 );
1088
1089AGESA_STATUS
1090CreateAcpiCrat (
1091 IN OUT AMD_CONFIG_PARAMS *StdHeader,
1092 OUT VOID **CratPtr
1093 );
1094
1095AGESA_STATUS
1096CreateAcpiCdit (
1097 IN OUT AMD_CONFIG_PARAMS *StdHeader,
1098 IN PLATFORM_CONFIGURATION *PlatformConfig,
1099 OUT VOID **CditPtr
1100 );
1101
1102AGESA_STATUS
1103CreateAcpiSrat (
1104 IN OUT AMD_CONFIG_PARAMS *StdHeader,
1105 IN OUT VOID **SratPtr
1106 );
1107
1108AGESA_STATUS
1109CreateAcpiSlit (
1110 IN OUT AMD_CONFIG_PARAMS *StdHeader,
1111 IN PLATFORM_CONFIGURATION *PlatformConfig,
1112 IN OUT VOID **SlitPtr
1113 );
1114
1115VOID
1116ChecksumAcpiTable (
1117 IN OUT ACPI_TABLE_HEADER *Table,
1118 IN AMD_CONFIG_PARAMS *StdHeader
1119 );
1120
1121AGESA_STATUS
1122RunLateApTaskOnAllAPs (
1123 IN AP_EXE_PARAMS *ApParams,
1124 IN AMD_CONFIG_PARAMS *StdHeader
1125 );
1126
1127AGESA_STATUS
1128RunLateApTaskOnAllCore0s (
1129 IN AP_EXE_PARAMS *ApParams,
1130 IN AMD_CONFIG_PARAMS *StdHeader
1131 );
1132
1133#endif // _CPU_LATE_INIT_H_