zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * AMD CPU Late Init API |
| 6 | * |
| 7 | * Contains code for doing any late CPU initialization. |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: CPU |
| 12 | * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ |
| 13 | * |
| 14 | */ |
| 15 | /* |
| 16 | ****************************************************************************** |
| 17 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 18 | * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. |
| 19 | * All rights reserved. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 20 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 21 | * Redistribution and use in source and binary forms, with or without |
| 22 | * modification, are permitted provided that the following conditions are met: |
| 23 | * * Redistributions of source code must retain the above copyright |
| 24 | * notice, this list of conditions and the following disclaimer. |
| 25 | * * Redistributions in binary form must reproduce the above copyright |
| 26 | * notice, this list of conditions and the following disclaimer in the |
| 27 | * documentation and/or other materials provided with the distribution. |
| 28 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 29 | * its contributors may be used to endorse or promote products derived |
| 30 | * from this software without specific prior written permission. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 31 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 32 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 33 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 34 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 35 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 36 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 37 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 38 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 39 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 40 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 41 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 42 | ****************************************************************************** |
| 43 | */ |
| 44 | |
| 45 | /*---------------------------------------------------------------------------------------- |
| 46 | * M O D U L E S U S E D |
| 47 | *---------------------------------------------------------------------------------------- |
| 48 | */ |
| 49 | #include "AGESA.h" |
| 50 | #include "amdlib.h" |
| 51 | #include "Ids.h" |
| 52 | #include "cpuLateInit.h" |
| 53 | #include "cpuRegisters.h" |
| 54 | #include "GeneralServices.h" |
| 55 | #include "cpuServices.h" |
| 56 | #include "Filecode.h" |
| 57 | CODE_GROUP (G3_DXE) |
| 58 | RDATA_GROUP (G3_DXE) |
| 59 | |
| 60 | #define FILECODE PROC_CPU_CPULATEINIT_FILECODE |
| 61 | /*---------------------------------------------------------------------------------------- |
| 62 | * D E F I N I T I O N S A N D M A C R O S |
| 63 | *---------------------------------------------------------------------------------------- |
| 64 | */ |
| 65 | |
| 66 | /*---------------------------------------------------------------------------------------- |
| 67 | * T Y P E D E F S A N D S T R U C T U R E S |
| 68 | *---------------------------------------------------------------------------------------- |
| 69 | */ |
| 70 | |
| 71 | /*---------------------------------------------------------------------------------------- |
| 72 | * P R O T O T Y P E S O F L O C A L F U N C T I O N S |
| 73 | *---------------------------------------------------------------------------------------- |
| 74 | */ |
| 75 | VOID |
| 76 | DisableCf8ExtCfg ( |
| 77 | IN AMD_CONFIG_PARAMS *StdHeader |
| 78 | ); |
| 79 | /*---------------------------------------------------------------------------------------- |
| 80 | * E X P O R T E D F U N C T I O N S |
| 81 | *---------------------------------------------------------------------------------------- |
| 82 | */ |
| 83 | |
| 84 | |
| 85 | /*---------------------------------------------------------------------------------------*/ |
| 86 | /** |
| 87 | * Performs CPU related initialization at the late entry point |
| 88 | * |
| 89 | * This function should be the last function run by the AGESA |
| 90 | * CPU module and prepares the processor for the operating system |
| 91 | * bootstrap load process. |
| 92 | * |
| 93 | * @param[in] StdHeader Config handle for library and services |
| 94 | * @param[in] PlatformConfig Contains the runtime modifiable feature input data. |
| 95 | * |
| 96 | * @retval AGESA_SUCCESS |
| 97 | * |
| 98 | */ |
| 99 | AGESA_STATUS |
| 100 | AmdCpuLate ( |
| 101 | IN AMD_CONFIG_PARAMS *StdHeader, |
| 102 | IN PLATFORM_CONFIGURATION *PlatformConfig |
| 103 | ) |
| 104 | { |
| 105 | AP_EXE_PARAMS ApParams; |
| 106 | |
| 107 | if ((PlatformConfig->PlatformProfile.AdvancedPerformanceProfile.HardwarePrefetchMode != HARDWARE_PREFETCHER_AUTO) || |
| 108 | (PlatformConfig->PlatformProfile.AdvancedPerformanceProfile.SoftwarePrefetchMode != SOFTWARE_PREFETCHES_AUTO)) { |
| 109 | ApParams.StdHeader = *StdHeader; |
| 110 | ApParams.FunctionNumber = AP_LATE_TASK_CPU_LATE_INIT; |
| 111 | ApParams.RelatedDataBlock = (VOID *) PlatformConfig; |
| 112 | ApParams.RelatedBlockLength = sizeof (PLATFORM_CONFIGURATION); |
| 113 | RunLateApTaskOnAllAPs (&ApParams, StdHeader); |
| 114 | CpuLateInitApTask (&ApParams); |
| 115 | } |
| 116 | DisableCf8ExtCfg (StdHeader); |
| 117 | return (AGESA_SUCCESS); |
| 118 | } |
| 119 | |
| 120 | /* -----------------------------------------------------------------------------*/ |
| 121 | /** |
| 122 | * |
| 123 | * CpuLateInitApTask |
| 124 | * |
| 125 | * Description: |
| 126 | * This is the last function run on all APs |
| 127 | * |
| 128 | * Parameters: |
| 129 | * @param[in] ApExeParams Handle to config for library and services. |
| 130 | * |
| 131 | * @retval AGESA_STATUS |
| 132 | * |
| 133 | * Processing: |
| 134 | * |
| 135 | */ |
| 136 | AGESA_STATUS |
| 137 | CpuLateInitApTask ( |
| 138 | IN AP_EXE_PARAMS *ApExeParams |
| 139 | ) |
| 140 | { |
| 141 | UINT64 LocalMsrRegister; |
| 142 | PLATFORM_CONFIGURATION *PlatformConfig; |
| 143 | BOOLEAN CuCfg3Exist; |
| 144 | |
| 145 | PlatformConfig = (PLATFORM_CONFIGURATION *) ApExeParams->RelatedDataBlock; |
| 146 | // The processor that has compute unit has CU_CFG3 MSR |
| 147 | switch (GetComputeUnitMapping (&(ApExeParams->StdHeader))) { |
| 148 | case AllCoresMapping: |
| 149 | CuCfg3Exist = FALSE; |
| 150 | break; |
| 151 | case EvenCoresMapping: |
| 152 | CuCfg3Exist = TRUE; |
| 153 | break; |
| 154 | default: |
| 155 | CuCfg3Exist = FALSE; |
| 156 | } |
| 157 | |
| 158 | // DISABLE_HARDWARE_PREFETCH |
| 159 | if (PlatformConfig->PlatformProfile.AdvancedPerformanceProfile.HardwarePrefetchMode == DISABLE_HARDWARE_PREFETCH) { |
| 160 | // DC_CFG (MSR_C001_1022) |
| 161 | // [13] = 1 |
| 162 | // [15] = 1 |
| 163 | LibAmdMsrRead (MSR_DC_CFG, &LocalMsrRegister, &(ApExeParams->StdHeader)); |
| 164 | LocalMsrRegister |= (BIT13 | BIT15); |
| 165 | LibAmdMsrWrite (MSR_DC_CFG, &LocalMsrRegister, &(ApExeParams->StdHeader)); |
| 166 | // CU_CFG3 (MSR_C001_102B) |
| 167 | // [3] = 1 |
| 168 | // [16] = 1 |
| 169 | // [17] = 1 |
| 170 | // [18] = 1 |
| 171 | if ((CuCfg3Exist) && (IsCorePairPrimary (FirstCoreIsComputeUnitPrimary, &(ApExeParams->StdHeader)))) { |
| 172 | LibAmdMsrRead (MSR_CU_CFG3, &LocalMsrRegister, &(ApExeParams->StdHeader)); |
| 173 | LocalMsrRegister |= (BIT3 | BIT16 | BIT17 | BIT18); |
| 174 | LibAmdMsrWrite (MSR_CU_CFG3, &LocalMsrRegister, &(ApExeParams->StdHeader)); |
| 175 | } |
| 176 | } |
| 177 | |
| 178 | // DISABLE_L1_PREFETCHER |
| 179 | if ((PlatformConfig->PlatformProfile.AdvancedPerformanceProfile.HardwarePrefetchMode == DISABLE_L1_PREFETCHER) || |
| 180 | (PlatformConfig->PlatformProfile.AdvancedPerformanceProfile.HardwarePrefetchMode == DISABLE_L1_PREFETCHER_AND_HW_PREFETCHER_TRAINING_ON_SOFTWARE_PREFETCHES )) { |
| 181 | // CU_CFG3 (MSR_C001_102B) |
| 182 | // [3] = 1 |
| 183 | if ((CuCfg3Exist) && (IsCorePairPrimary (FirstCoreIsComputeUnitPrimary, &(ApExeParams->StdHeader)))) { |
| 184 | LibAmdMsrRead (MSR_CU_CFG3, &LocalMsrRegister, &(ApExeParams->StdHeader)); |
| 185 | LocalMsrRegister |= BIT3; |
| 186 | LibAmdMsrWrite (MSR_CU_CFG3, &LocalMsrRegister, &(ApExeParams->StdHeader)); |
| 187 | } |
| 188 | |
| 189 | } |
| 190 | |
| 191 | // DISABLE_HW_PREFETCHER_TRAINING_ON_SOFTWARE_PREFETCHES |
| 192 | if ((PlatformConfig->PlatformProfile.AdvancedPerformanceProfile.HardwarePrefetchMode == DISABLE_HW_PREFETCHER_TRAINING_ON_SOFTWARE_PREFETCHES ) || |
| 193 | (PlatformConfig->PlatformProfile.AdvancedPerformanceProfile.HardwarePrefetchMode == DISABLE_L1_PREFETCHER_AND_HW_PREFETCHER_TRAINING_ON_SOFTWARE_PREFETCHES )) { |
| 194 | // DC_CFG (MSR_C001_1022) |
| 195 | // [15] = 1 |
| 196 | LibAmdMsrRead (MSR_DC_CFG, &LocalMsrRegister, &(ApExeParams->StdHeader)); |
| 197 | LocalMsrRegister |= BIT15; |
| 198 | LibAmdMsrWrite (MSR_DC_CFG, &LocalMsrRegister, &(ApExeParams->StdHeader)); |
| 199 | |
| 200 | } |
| 201 | |
| 202 | // DISABLE_SOFTWARE_PREFETCHES |
| 203 | if (PlatformConfig->PlatformProfile.AdvancedPerformanceProfile.SoftwarePrefetchMode == DISABLE_SOFTWARE_PREFETCHES) { |
| 204 | // MSR_DE_CFG (MSR_C001_1029) |
| 205 | // [7:2] = 0x3F |
| 206 | if (IsCorePairPrimary (FirstCoreIsComputeUnitPrimary, &(ApExeParams->StdHeader))) { |
| 207 | LibAmdMsrRead (MSR_DE_CFG, &LocalMsrRegister, &(ApExeParams->StdHeader)); |
| 208 | LocalMsrRegister |= 0xFC; |
| 209 | LibAmdMsrWrite (MSR_DE_CFG, &LocalMsrRegister, &(ApExeParams->StdHeader)); |
| 210 | } |
| 211 | } |
| 212 | |
| 213 | return AGESA_SUCCESS; |
| 214 | } |
| 215 | |
| 216 | /*---------------------------------------------------------------------------------------*/ |
| 217 | /** |
| 218 | * Clear EnableCf8ExtCfg on all socket |
| 219 | * |
| 220 | * Clear F3x8C bit 14 EnableCf8ExtCfg |
| 221 | * |
| 222 | * @param[in] StdHeader Config handle for library and services |
| 223 | * |
| 224 | * |
| 225 | */ |
| 226 | VOID |
| 227 | DisableCf8ExtCfg ( |
| 228 | IN AMD_CONFIG_PARAMS *StdHeader |
| 229 | ) |
| 230 | { |
| 231 | AGESA_STATUS AgesaStatus; |
| 232 | PCI_ADDR PciAddress; |
| 233 | UINT32 Socket; |
| 234 | UINT32 Module; |
| 235 | UINT32 PciData; |
| 236 | UINT32 LegacyPciAccess; |
| 237 | |
| 238 | ASSERT (IsBsp (StdHeader, &AgesaStatus)); |
| 239 | |
| 240 | for (Socket = 0; Socket < GetPlatformNumberOfSockets (); Socket++) { |
| 241 | for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { |
| 242 | if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &AgesaStatus)) { |
| 243 | PciAddress.Address.Function = FUNC_3; |
| 244 | PciAddress.Address.Register = NB_CFG_HIGH_REG; |
| 245 | LegacyPciAccess = ((1 << 31) + (PciAddress.Address.Register & 0xFC) + (PciAddress.Address.Function << 8) + (PciAddress.Address.Device << 11) + (PciAddress.Address.Bus << 16) + ((PciAddress.Address.Register & 0xF00) << (24 - 8))); |
| 246 | // read from PCI register |
| 247 | LibAmdIoWrite (AccessWidth32, IOCF8, &LegacyPciAccess, StdHeader); |
| 248 | LibAmdIoRead (AccessWidth32, IOCFC, &PciData, StdHeader); |
| 249 | // Disable Cf8ExtCfg |
| 250 | PciData &= 0xFFFFBFFF; |
| 251 | // write to PCI register |
| 252 | LibAmdIoWrite (AccessWidth32, IOCF8, &LegacyPciAccess, StdHeader); |
| 253 | LibAmdIoWrite (AccessWidth32, IOCFC, &PciData, StdHeader); |
| 254 | } |
| 255 | } |
| 256 | } |
| 257 | } |
| 258 | |
| 259 | /*---------------------------------------------------------------------------------------*/ |
| 260 | /** |
| 261 | * Calculate an ACPI style checksum |
| 262 | * |
| 263 | * Computes the checksum and stores the value to the checksum |
| 264 | * field of the passed in ACPI table's header. |
| 265 | * |
| 266 | * @param[in] Table ACPI table to checksum |
| 267 | * @param[in] StdHeader Config handle for library and services |
| 268 | * |
| 269 | */ |
| 270 | VOID |
| 271 | ChecksumAcpiTable ( |
| 272 | IN OUT ACPI_TABLE_HEADER *Table, |
| 273 | IN AMD_CONFIG_PARAMS *StdHeader |
| 274 | ) |
| 275 | { |
| 276 | UINT8 *BuffTempPtr; |
| 277 | UINT8 Checksum; |
| 278 | UINT32 BufferOffset; |
| 279 | |
| 280 | Table->Checksum = 0; |
| 281 | Checksum = 0; |
| 282 | BuffTempPtr = (UINT8 *) Table; |
| 283 | for (BufferOffset = 0; BufferOffset < Table->TableLength; BufferOffset++) { |
| 284 | Checksum = Checksum - *(BuffTempPtr + BufferOffset); |
| 285 | } |
| 286 | |
| 287 | Table->Checksum = Checksum; |
| 288 | } |
| 289 | |
| 290 | /*---------------------------------------------------------------------------------------*/ |
| 291 | /** |
| 292 | * |
| 293 | * Run code on every AP in the system. |
| 294 | * |
| 295 | * @param[in] ApParams AP task pointer. |
| 296 | * @param[in] StdHeader Handle to config for library and services |
| 297 | * |
| 298 | * @return The most severe AGESA_STATUS returned by an AP. |
| 299 | * |
| 300 | */ |
| 301 | AGESA_STATUS |
| 302 | RunLateApTaskOnAllAPs ( |
| 303 | IN AP_EXE_PARAMS *ApParams, |
| 304 | IN AMD_CONFIG_PARAMS *StdHeader |
| 305 | ) |
| 306 | { |
| 307 | UINT32 NumberOfSockets; |
| 308 | UINT32 NumberOfCores; |
| 309 | UINT8 Socket; |
| 310 | UINT8 Core; |
| 311 | UINT8 ApicId; |
| 312 | UINT32 BscSocket; |
| 313 | UINT32 Ignored; |
| 314 | UINT32 BscCoreNum; |
| 315 | AGESA_STATUS CalledStatus; |
| 316 | AGESA_STATUS IgnoredStatus; |
| 317 | AGESA_STATUS AgesaStatus; |
| 318 | |
| 319 | ASSERT (IsBsp (StdHeader, &IgnoredStatus)); |
| 320 | |
| 321 | AgesaStatus = AGESA_SUCCESS; |
| 322 | |
| 323 | IdentifyCore (StdHeader, &BscSocket, &Ignored, &BscCoreNum, &IgnoredStatus); |
| 324 | NumberOfSockets = GetPlatformNumberOfSockets (); |
| 325 | |
| 326 | for (Socket = 0; Socket < NumberOfSockets; Socket++) { |
| 327 | if (GetActiveCoresInGivenSocket (Socket, &NumberOfCores, StdHeader)) { |
| 328 | for (Core = 0; Core < NumberOfCores; Core++) { |
| 329 | if ((Socket != BscSocket) || (Core != BscCoreNum)) { |
| 330 | GetApicId (StdHeader, Socket, Core, &ApicId, &IgnoredStatus); |
| 331 | AGESA_TESTPOINT (TpIfBeforeRunApFromAllAps, StdHeader); |
| 332 | CalledStatus = AgesaRunFcnOnAp ((UINTN) ApicId, ApParams); |
| 333 | AGESA_TESTPOINT (TpIfAfterRunApFromAllAps, StdHeader); |
| 334 | if (CalledStatus > AgesaStatus) { |
| 335 | AgesaStatus = CalledStatus; |
| 336 | } |
| 337 | } |
| 338 | } |
| 339 | } |
| 340 | } |
| 341 | return AgesaStatus; |
| 342 | } |
| 343 | |
| 344 | |
| 345 | /*---------------------------------------------------------------------------------------*/ |
| 346 | /** |
| 347 | * |
| 348 | * Run code on core 0 of every socket in the system. |
| 349 | * |
| 350 | * @param[in] ApParams AP task pointer. |
| 351 | * @param[in] StdHeader Handle to config for library and services |
| 352 | * |
| 353 | * @return The most severe AGESA_STATUS returned by an AP. |
| 354 | * |
| 355 | */ |
| 356 | AGESA_STATUS |
| 357 | RunLateApTaskOnAllCore0s ( |
| 358 | IN AP_EXE_PARAMS *ApParams, |
| 359 | IN AMD_CONFIG_PARAMS *StdHeader |
| 360 | ) |
| 361 | { |
| 362 | UINT32 NumberOfSockets; |
| 363 | UINT8 Socket; |
| 364 | UINT8 ApicId; |
| 365 | UINT32 BscSocket; |
| 366 | UINT32 IgnoredModule; |
| 367 | UINT32 IgnoredCore; |
| 368 | AGESA_STATUS CalledStatus; |
| 369 | AGESA_STATUS IgnoredStatus; |
| 370 | AGESA_STATUS AgesaStatus; |
| 371 | |
| 372 | ASSERT (IsBsp (StdHeader, &IgnoredStatus)); |
| 373 | |
| 374 | AgesaStatus = AGESA_SUCCESS; |
| 375 | |
| 376 | IdentifyCore (StdHeader, &BscSocket, &IgnoredModule, &IgnoredCore, &IgnoredStatus); |
| 377 | NumberOfSockets = GetPlatformNumberOfSockets (); |
| 378 | |
| 379 | for (Socket = 0; Socket < NumberOfSockets; Socket++) { |
| 380 | if (IsProcessorPresent (Socket, StdHeader)) { |
| 381 | if (Socket != BscSocket) { |
| 382 | GetApicId (StdHeader, Socket, 0, &ApicId, &IgnoredStatus); |
| 383 | AGESA_TESTPOINT (TpIfBeforeRunApFromAllCore0s, StdHeader); |
| 384 | CalledStatus = AgesaRunFcnOnAp ((UINTN) ApicId, ApParams); |
| 385 | AGESA_TESTPOINT (TpIfAfterRunApFromAllCore0s, StdHeader); |
| 386 | if (CalledStatus > AgesaStatus) { |
| 387 | AgesaStatus = CalledStatus; |
| 388 | } |
| 389 | } |
| 390 | } |
| 391 | } |
| 392 | return AgesaStatus; |
| 393 | } |