zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * AMD CPU Reset API, and related functions and structures. |
| 6 | * |
| 7 | * Contains code that initialized the CPU after early reset. |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: CPU |
| 12 | * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ |
| 13 | * |
| 14 | */ |
| 15 | /* |
| 16 | ****************************************************************************** |
| 17 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 18 | * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. |
| 19 | * All rights reserved. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 20 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 21 | * Redistribution and use in source and binary forms, with or without |
| 22 | * modification, are permitted provided that the following conditions are met: |
| 23 | * * Redistributions of source code must retain the above copyright |
| 24 | * notice, this list of conditions and the following disclaimer. |
| 25 | * * Redistributions in binary form must reproduce the above copyright |
| 26 | * notice, this list of conditions and the following disclaimer in the |
| 27 | * documentation and/or other materials provided with the distribution. |
| 28 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 29 | * its contributors may be used to endorse or promote products derived |
| 30 | * from this software without specific prior written permission. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 31 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 32 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 33 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 34 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 35 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 36 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 37 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 38 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 39 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 40 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 41 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 42 | ****************************************************************************** |
| 43 | */ |
| 44 | |
| 45 | #ifndef _CPU_EARLY_INIT_H_ |
| 46 | #define _CPU_EARLY_INIT_H_ |
| 47 | |
| 48 | |
| 49 | /*--------------------------------------------------------------------------------------- |
| 50 | * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) |
| 51 | *--------------------------------------------------------------------------------------- |
| 52 | */ |
| 53 | AGESA_FORWARD_DECLARATION (CPU_CORE_LEVELING_FAMILY_SERVICES); |
| 54 | |
| 55 | /*--------------------------------------------------------------------------------------- |
| 56 | * D E F I N I T I O N S A N D M A C R O S |
| 57 | *--------------------------------------------------------------------------------------- |
| 58 | */ |
| 59 | //---------------------------------------------------------------------------- |
| 60 | // CPU BRAND ID TYPEDEFS, STRUCTURES, ENUMS |
| 61 | // |
| 62 | //---------------------------------------------------------------------------- |
| 63 | #define CPU_BRAND_ID_LENGTH 48 // Total number of characters supported |
| 64 | #define LOW_NODE_DEVICEID 24 |
| 65 | #define NB_CAPABILITIES 0xE8 //Function 3 Registers |
| 66 | //---------------------------------------------------------------------------- |
| 67 | // CPU MICROCODE PATCH TYPEDEFS, STRUCTURES, ENUMS |
| 68 | // |
| 69 | //---------------------------------------------------------------------------- |
| 70 | /* All lengths are in bytes */ |
| 71 | #define MICROCODE_TRIADE_SIZE 28 |
| 72 | #define MICROCODE_HEADER_LENGTH 64 |
| 73 | |
| 74 | /** |
| 75 | * @page ucodeflag Microcode Patches Signature Guide |
| 76 | * |
| 77 | * We mark patches in the ROM with a signature so that they can be easily found |
| 78 | * |
| 79 | * @anchor Microcode Patch Signature |
| 80 | * @li @e Microcode Patch Signature @n |
| 81 | * Microcode patches are marked by adding a signature before patches in the ROM image to |
| 82 | * help identify where they are located. |
| 83 | * There're two kind of signatures. One is '$UCODE2K', it indicates there's a following patch with 2K size. |
| 84 | * The other is '$UCODE4K', it indicates there's a following patch with 4K size. |
| 85 | * If you want to know the patch level / equivalent ID, please consult the BKDG for patch header format. |
| 86 | * |
| 87 | * |
| 88 | */ |
| 89 | /// Microcode patch flag for replacement |
| 90 | typedef struct { |
| 91 | IN UINT8 MicrocodePatchesFlag[8]; ///< a flag followed by microcode |
| 92 | } MICROCODE_PATCHES_FLAG; |
| 93 | |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 94 | |
| 95 | /* Offsets in UCODE PATCH Header */ |
| 96 | /* Note: Header is 64 bytes */ |
| 97 | #define DATE_CODE_OFFSET 0 // 4 bytes |
| 98 | #define PATCH_ID 4 // 4 bytes |
| 99 | #define MICROCODE_PATH_DATA_ID 8 // 2 bytes |
| 100 | #define MICROCODE_PATCH_DATA_LENGTH 10 // 1 byte |
| 101 | #define MICROCODE_PATCH_DATA_CHECKSUM 12 // 4 bytes |
| 102 | #define CHIPSET_1_DEVICE_ID 16 // 4 bytes |
| 103 | #define CHIPSET_2_DEVICE_ID 20 // 4 bytes |
| 104 | #define PROCESSOR_REV_ID 24 // 2 bytes |
| 105 | #define CHIPSET_1_REV_ID 26 // 1 byte |
| 106 | #define CHIPSET_2_REV_ID 27 // 1 byte |
| 107 | |
| 108 | #define MICROCODE_PATCH_2K_SIZE 2048 |
| 109 | #define MICROCODE_PATCH_4K_SIZE 4096 |
| 110 | /*--------------------------------------------------------------------------------------- |
| 111 | * T Y P E D E F S, S T R U C T U R E S, E N U M S |
| 112 | *--------------------------------------------------------------------------------------- |
| 113 | */ |
| 114 | //---------------------------------------------------------------------------- |
| 115 | // CPU BRAND ID TYPEDEFS, STRUCTURES, ENUMS |
| 116 | // |
| 117 | //---------------------------------------------------------------------------- |
| 118 | /// A structure representing BrandId[15:0] from |
| 119 | /// CPUID Fn8000_0001_EBX |
| 120 | typedef struct { |
| 121 | UINT8 String1:4; ///< An index to a string value used to create the name string |
| 122 | UINT8 String2:4; ///< An index to a string value used to create the name string |
| 123 | UINT8 Page:1; ///< An index to the appropriate page for the String1, String2, and Model values |
| 124 | UINT8 Model:7; ///< A field used to create the model number in the name string |
| 125 | UINT8 Socket:4; ///< Specifies the package type |
| 126 | UINT8 Cores:4; ///< Identifies how many physical cores are present |
| 127 | } AMD_CPU_BRAND_DATA; |
| 128 | |
| 129 | /// A structure containing string1 and string2 values |
| 130 | /// as well as information pertaining to their usage |
| 131 | typedef struct { |
| 132 | IN UINT8 Cores; ///< Appropriate number of physical cores |
| 133 | IN UINT8 Page; ///< This string's page number |
| 134 | IN UINT8 Index; ///< String index |
| 135 | IN UINT8 Socket; ///< Package type information |
| 136 | IN CONST CHAR8 *Stringstart; ///< The literal string |
| 137 | IN UINT8 Stringlength; ///< Number of characters in the string |
| 138 | } AMD_CPU_BRAND; |
| 139 | |
| 140 | /// An entire CPU brand table. |
| 141 | typedef struct { |
| 142 | UINT8 NumberOfEntries; ///< The number of entries in the table. |
| 143 | CONST AMD_CPU_BRAND *Table; ///< The table entries. |
| 144 | } CPU_BRAND_TABLE; |
| 145 | |
| 146 | //---------------------------------------------------------------------------- |
| 147 | // CPU MICROCODE PATCH TYPEDEFS, STRUCTURES, ENUMS |
| 148 | // |
| 149 | //---------------------------------------------------------------------------- |
| 150 | /// Microcode patch field definitions |
| 151 | typedef struct { |
| 152 | UINT32 DateCode; ///< Date of patch creation |
| 153 | UINT32 PatchID; ///< Patch level |
| 154 | UINT16 MicrocodePatchDataID; ///< Internal use only |
| 155 | UINT8 MicrocodePatchDataLength; ///< Internal use only |
| 156 | UINT8 InitializationFlag; ///< Internal use only |
| 157 | UINT32 MicrocodePatchDataChecksum; ///< Doubleword sum of data block |
| 158 | UINT32 Chipset1DeviceID; ///< Device ID of 1st HT device to match |
| 159 | UINT32 Chipset2DeviceID; ///< Device ID of 2nd HT device to match |
| 160 | UINT16 ProcessorRevisionID; ///< Equivalent ID |
| 161 | UINT8 Chipset1RevisionID; ///< Revision level of 1st HT device to match |
| 162 | UINT8 Chipset2RevisionID; ///< Revision level of 2nd HT device to match |
| 163 | UINT8 BiosApiRevision; ///< BIOS INT 15 API revision required |
| 164 | UINT8 Reserved1[3]; ///< Reserved |
| 165 | UINT32 MatchRegister0; ///< Internal use only |
| 166 | UINT32 MatchRegister1; ///< Internal use only |
| 167 | UINT32 MatchRegister2; ///< Internal use only |
| 168 | UINT32 MatchRegister3; ///< Internal use only |
| 169 | UINT32 MatchRegister4; ///< Internal use only |
| 170 | UINT32 MatchRegister5; ///< Internal use only |
| 171 | UINT32 MatchRegister6; ///< Internal use only |
| 172 | UINT32 MatchRegister7; ///< Internal use only |
| 173 | UINT8 PatchDataBlock[896]; ///< Raw patch data |
| 174 | UINT8 Reserved2[896]; ///< Reserved |
| 175 | UINT8 X86CodePresent; ///< Boolean to determine if executable code exists |
| 176 | UINT8 X86CodeEntry[191]; ///< Code to execute if X86CodePresent != 0 |
| 177 | } MICROCODE_PATCH; |
| 178 | |
| 179 | /// Two kilobyte array containing the raw |
| 180 | /// microcode patch binary data |
| 181 | typedef struct { |
| 182 | IN UINT8 MicrocodePatches[MICROCODE_PATCH_2K_SIZE]; ///< 2k UINT8 elements |
| 183 | } MICROCODE_PATCHES; |
| 184 | |
| 185 | /// Four kilobyte array containing the raw |
| 186 | /// microcode patch binary data |
| 187 | typedef struct { |
| 188 | IN UINT8 MicrocodePatches[MICROCODE_PATCH_4K_SIZE]; ///< 4k UINT8 elements |
| 189 | } MICROCODE_PATCHES_4K; |
| 190 | |
| 191 | /** |
| 192 | * Set down core register |
| 193 | * |
| 194 | * @CpuServiceInstances |
| 195 | * |
| 196 | * @param[in] FamilySpecificServices The current Family Specific Services. |
| 197 | * @param[in] Socket Socket ID. |
| 198 | * @param[in] Module Module ID in socket. |
| 199 | * @param[in] LeveledCores Number of core. |
| 200 | * @param[in] CoreLevelMode Core level mode. |
| 201 | * @param[in] StdHeader Header for library and services. |
| 202 | * |
| 203 | * @retval TRUE Down Core register is updated. |
| 204 | * @retval FALSE Down Core register is not updated. |
| 205 | */ |
| 206 | typedef BOOLEAN (F_CPU_SET_DOWN_CORE_REGISTER) ( |
| 207 | IN CPU_CORE_LEVELING_FAMILY_SERVICES *FamilySpecificServices, |
| 208 | IN UINT32 *Socket, |
| 209 | IN UINT32 *Module, |
| 210 | IN UINT32 *LeveledCores, |
| 211 | IN CORE_LEVELING_TYPE CoreLevelMode, |
| 212 | IN AMD_CONFIG_PARAMS *StdHeader |
| 213 | ); |
| 214 | |
| 215 | /// Reference to a method |
| 216 | typedef F_CPU_SET_DOWN_CORE_REGISTER *PF_CPU_SET_DOWN_CORE_REGISTER; |
| 217 | |
| 218 | /** |
| 219 | * Provide the interface to the Core Leveling Family Specific Services. |
| 220 | * |
| 221 | * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!). |
| 222 | * Each supported Family must provide an implementation for all methods in this interface, even if the |
| 223 | * implementation is a CommonReturn(). |
| 224 | */ |
| 225 | struct _CPU_CORE_LEVELING_FAMILY_SERVICES { // See Forward Declaration above |
| 226 | UINT16 Revision; ///< Interface version |
| 227 | // Public Methods. |
| 228 | PF_CPU_SET_DOWN_CORE_REGISTER SetDownCoreRegister; ///< Method: Set down core register. |
| 229 | }; |
| 230 | |
| 231 | //---------------------------------------------------------------------------- |
| 232 | // CPU PERFORM EARLY INIT ON CORE |
| 233 | // |
| 234 | //---------------------------------------------------------------------------- |
| 235 | /// Flag definition. |
| 236 | #define PERFORM_EARLY_WARM_RESET 0x1 // bit 0 --- the related function needs to be run if it's warm reset |
| 237 | #define PERFORM_EARLY_COLD_BOOT 0x2 // bit 1 --- the related function needs to be run if it's cold boot |
| 238 | |
| 239 | #define PERFORM_EARLY_ANY_CONDITION 0xFFFFFFFFul // the related function always needs to be run |
| 240 | /*--------------------------------------------------------------------------------------- |
| 241 | * F U N C T I O N P R O T O T Y P E |
| 242 | *--------------------------------------------------------------------------------------- |
| 243 | */ |
| 244 | |
| 245 | // These are P U B L I C functions, used by IBVs |
| 246 | AGESA_STATUS |
| 247 | AmdCpuEarly ( |
| 248 | IN AMD_CONFIG_PARAMS *StdHeader, |
| 249 | IN PLATFORM_CONFIGURATION *PlatformConfig |
| 250 | ); |
| 251 | |
| 252 | // These are P U B L I C functions, used by AGESA |
| 253 | VOID |
| 254 | SetBrandIdRegisters ( |
| 255 | IN OUT AMD_CONFIG_PARAMS *StdHeader |
| 256 | ); |
| 257 | |
| 258 | AGESA_STATUS |
| 259 | PmInitializationAtEarly ( |
| 260 | IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams, |
| 261 | IN AMD_CONFIG_PARAMS *StdHeader |
| 262 | ); |
| 263 | |
| 264 | BOOLEAN |
| 265 | LoadMicrocodePatch ( |
| 266 | IN OUT AMD_CONFIG_PARAMS *StdHeader |
| 267 | ); |
| 268 | |
| 269 | BOOLEAN |
| 270 | GetPatchEquivalentId ( |
| 271 | IN OUT UINT16 *ProcessorEquivalentId, |
| 272 | IN OUT AMD_CONFIG_PARAMS *StdHeader |
| 273 | ); |
| 274 | |
| 275 | BOOLEAN |
| 276 | ValidateMicrocode ( |
| 277 | IN MICROCODE_PATCH *MicrocodePatchPtr, |
| 278 | IN UINT16 ProcessorEquivalentId, |
| 279 | IN OUT AMD_CONFIG_PARAMS *StdHeader |
| 280 | ); |
| 281 | |
| 282 | VOID |
| 283 | GetMicrocodeVersion ( |
| 284 | OUT UINT32 *pMicrocodeVersion, |
| 285 | IN OUT AMD_CONFIG_PARAMS *StdHeader |
| 286 | ); |
| 287 | |
| 288 | VOID |
| 289 | AmdCpuEarlyInitializer ( |
| 290 | IN AMD_CONFIG_PARAMS *StdHeader, |
| 291 | IN PLATFORM_CONFIGURATION *PlatformConfig, |
| 292 | IN OUT AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr |
| 293 | ); |
| 294 | |
| 295 | VOID |
| 296 | McaInitialization ( |
| 297 | IN AMD_CONFIG_PARAMS *StdHeader |
| 298 | ); |
| 299 | |
| 300 | #endif // _CPU_EARLY_INIT_H_ |
| 301 | |