zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * AMD CPU Register Table Related Functions |
| 6 | * |
| 7 | * Contains the definition of the CPU CPUID MSRs and PCI registers with BKDG recommended values |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: CPU |
| 12 | * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ |
| 13 | * |
| 14 | */ |
| 15 | /* |
| 16 | ****************************************************************************** |
| 17 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 18 | * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. |
| 19 | * All rights reserved. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 20 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 21 | * Redistribution and use in source and binary forms, with or without |
| 22 | * modification, are permitted provided that the following conditions are met: |
| 23 | * * Redistributions of source code must retain the above copyright |
| 24 | * notice, this list of conditions and the following disclaimer. |
| 25 | * * Redistributions in binary form must reproduce the above copyright |
| 26 | * notice, this list of conditions and the following disclaimer in the |
| 27 | * documentation and/or other materials provided with the distribution. |
| 28 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 29 | * its contributors may be used to endorse or promote products derived |
| 30 | * from this software without specific prior written permission. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 31 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 32 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 33 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 34 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 35 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 36 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 37 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 38 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 39 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 40 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 41 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 42 | ****************************************************************************** |
| 43 | */ |
| 44 | |
| 45 | #ifndef _CPU_FAM_REGISTERS_H_ |
| 46 | #define _CPU_FAM_REGISTERS_H_ |
| 47 | |
| 48 | /* |
| 49 | *-------------------------------------------------------------- |
| 50 | * |
| 51 | * M O D U L E S U S E D |
| 52 | * |
| 53 | *--------------------------------------------------------------- |
| 54 | */ |
| 55 | |
| 56 | /* |
| 57 | *-------------------------------------------------------------- |
| 58 | * |
| 59 | * D E F I N I T I O N S / M A C R O S |
| 60 | * |
| 61 | *--------------------------------------------------------------- |
| 62 | */ |
| 63 | |
| 64 | // This define should be equal to the total number of families |
| 65 | // in the cpuFamily enum. |
| 66 | #define MAX_CPU_FAMILIES 64 |
| 67 | #define MAX_CPU_REVISIONS 63 // Max Cpu Revisions Per Family |
| 68 | |
| 69 | // CPU_LOGICAL_ID.Family equates |
| 70 | // Family 10h equates |
| 71 | #define AMD_FAMILY_10_RB 0x0000000000000001ull |
| 72 | #define AMD_FAMILY_10_BL 0x0000000000000002ull |
| 73 | #define AMD_FAMILY_10_DA 0x0000000000000004ull |
| 74 | #define AMD_FAMILY_10_HY 0x0000000000000008ull |
| 75 | #define AMD_FAMILY_10_PH 0x0000000000000010ull |
| 76 | #define AMD_FAMILY_10_C32 AMD_FAMILY_10_HY |
| 77 | |
| 78 | #define AMD_FAMILY_10 (AMD_FAMILY_10_RB | AMD_FAMILY_10_BL | AMD_FAMILY_10_DA | AMD_FAMILY_10_HY | AMD_FAMILY_10_PH) |
| 79 | #define AMD_FAMILY_GH (AMD_FAMILY_10) |
| 80 | |
| 81 | // Family 12h equates |
| 82 | #define AMD_FAMILY_12_LN 0x0000000000000020ull |
| 83 | #define AMD_FAMILY_12 (AMD_FAMILY_12_LN) |
| 84 | #define AMD_FAMILY_LN (AMD_FAMILY_12_LN) |
| 85 | |
| 86 | // Family 14h equates |
| 87 | #define AMD_FAMILY_14_ON 0x0000000000000040ull |
| 88 | #define AMD_FAMILY_ON (AMD_FAMILY_14_ON) |
| 89 | #define AMD_FAMILY_14_KR 0x0000000000000080ull |
| 90 | #define AMD_FAMILY_KR (AMD_FAMILY_14_KR) |
| 91 | #define AMD_FAMILY_14 (AMD_FAMILY_14_ON | AMD_FAMILY_14_KR) |
| 92 | |
| 93 | // Family 15h equates |
| 94 | #define AMD_FAMILY_15_OR 0x0000000000000100ull |
| 95 | #define AMD_FAMILY_OR (AMD_FAMILY_15_OR) |
| 96 | #define AMD_FAMILY_15_TN 0x0000000000000200ull |
| 97 | #define AMD_FAMILY_TN (AMD_FAMILY_15_TN) |
| 98 | |
| 99 | |
| 100 | // Family Unknown |
| 101 | #define AMD_FAMILY_UNKNOWN 0x8000000000000000ull |
| 102 | |
| 103 | // Family Group equates |
| 104 | #define AMD_FAMILY_GE_12 (AMD_FAMILY_12 | AMD_FAMILY_14 | (AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) | 0x0000000000010000ull ) |
| 105 | |
| 106 | // Family 10h CPU_LOGICAL_ID.Revision equates |
| 107 | // ------------------------------------- |
| 108 | // Family 10h RB steppings |
| 109 | #define AMD_F10_RB_C0 0x0000000000000001ull |
| 110 | #define AMD_F10_RB_C1 0x0000000000000002ull |
| 111 | #define AMD_F10_RB_C2 0x0000000000000004ull |
| 112 | #define AMD_F10_RB_C3 0x0000000000000008ull |
| 113 | // Family 10h BL steppings |
| 114 | #define AMD_F10_BL_C2 0x0000000000000010ull |
| 115 | #define AMD_F10_BL_C3 0x0000000000000020ull |
| 116 | // Family 10h DA steppings |
| 117 | #define AMD_F10_DA_C2 0x0000000000000040ull |
| 118 | #define AMD_F10_DA_C3 0x0000000000000080ull |
| 119 | // Family 10h HY SCM steppings |
| 120 | #define AMD_F10_HY_SCM_D0 0x0000000000000100ull |
| 121 | #define AMD_F10_HY_SCM_D1 0x0000000000000400ull |
| 122 | // Family 10h HY MCM steppings |
| 123 | #define AMD_F10_HY_MCM_D0 0x0000000000000200ull |
| 124 | #define AMD_F10_HY_MCM_D1 0x0000000000000800ull |
| 125 | // Family 10h PH steppings |
| 126 | #define AMD_F10_PH_E0 0x0000000000001000ull |
| 127 | |
| 128 | // Family 10h Unknown stepping |
| 129 | // * This equate is used to ensure that unknown CPU revisions are * |
| 130 | // * identified as the last known revision of the silicon family: * |
| 131 | // * - Update AMD_F10_UNKNOWN whenever newer F10h steppings are added * |
| 132 | #define AMD_F10_UNKNOWN (AMD_FAMILY_UNKNOWN | AMD_F10_C3 | AMD_F10_D1 | AMD_F10_PH_E0) |
| 133 | |
| 134 | // Family 10h Miscellaneous equates |
| 135 | #define AMD_F10_C0 (AMD_F10_RB_C0) |
| 136 | #define AMD_F10_C1 (AMD_F10_RB_C1) |
| 137 | #define AMD_F10_C2 (AMD_F10_RB_C2 | AMD_F10_DA_C2 | AMD_F10_BL_C2) |
| 138 | #define AMD_F10_C3 (AMD_F10_RB_C3 | AMD_F10_DA_C3 | AMD_F10_BL_C3) |
| 139 | #define AMD_F10_Cx (AMD_F10_C0 | AMD_F10_C1 | AMD_F10_C2 | AMD_F10_C3) |
| 140 | |
| 141 | #define AMD_F10_RB_ALL (AMD_F10_RB_C0 | AMD_F10_RB_C1 | AMD_F10_RB_C2 | AMD_F10_RB_C3) |
| 142 | |
| 143 | #define AMD_F10_BL_ALL (AMD_F10_BL_C2 | AMD_F10_BL_C3) |
| 144 | #define AMD_F10_BL_Cx (AMD_F10_BL_C2 | AMD_F10_BL_C3) |
| 145 | |
| 146 | #define AMD_F10_DA_ALL (AMD_F10_DA_C2 | AMD_F10_DA_C3) |
| 147 | #define AMD_F10_DA_Cx (AMD_F10_DA_C2 | AMD_F10_DA_C3) |
| 148 | |
| 149 | #define AMD_F10_D0 (AMD_F10_HY_SCM_D0 | AMD_F10_HY_MCM_D0) |
| 150 | #define AMD_F10_D1 (AMD_F10_HY_SCM_D1 | AMD_F10_HY_MCM_D1) |
| 151 | #define AMD_F10_Dx (AMD_F10_D0 | AMD_F10_D1) |
| 152 | |
| 153 | #define AMD_F10_PH_ALL (AMD_F10_PH_E0) |
| 154 | #define AMD_F10_Ex (AMD_F10_PH_E0) |
| 155 | |
| 156 | #define AMD_F10_HY_ALL (AMD_F10_Dx) |
| 157 | #define AMD_F10_C32_ALL (AMD_F10_HY_SCM_D0 | AMD_F10_HY_SCM_D1) |
| 158 | |
| 159 | #define AMD_F10_GT_B0 (AMD_F10_Cx | AMD_F10_Dx | AMD_F10_Ex) |
| 160 | #define AMD_F10_GT_Bx (AMD_F10_Cx | AMD_F10_Dx | AMD_F10_Ex) |
| 161 | #define AMD_F10_GT_A2 (AMD_F10_Cx | AMD_F10_Dx | AMD_F10_Ex) |
| 162 | #define AMD_F10_GT_Ax (AMD_F10_Cx | AMD_F10_Dx | AMD_F10_Ex) |
| 163 | #define AMD_F10_GT_C0 ((AMD_F10_Cx & ~AMD_F10_C0) | AMD_F10_Dx | AMD_F10_Ex) |
| 164 | #define AMD_F10_GT_D0 (AMD_F10_Dx & ~AMD_F10_D0 | AMD_F10_Ex) |
| 165 | |
| 166 | #define AMD_F10_ALL (AMD_F10_Cx | AMD_F10_Dx | AMD_F10_Ex) |
| 167 | |
| 168 | // Family 12h CPU_LOGICAL_ID.Revision equates |
| 169 | // ------------------------------------- |
| 170 | |
| 171 | // Family 12h LN steppings |
| 172 | #define AMD_F12_LN_A0 0x0000000000000001ull |
| 173 | #define AMD_F12_LN_A1 0x0000000000000002ull |
| 174 | #define AMD_F12_LN_B0 0x0000000000000004ull |
| 175 | |
| 176 | // Family 12h Unknown stepping |
| 177 | // * This equate is used to ensure that unknown CPU revisions are * |
| 178 | // * identified as the last known revision of the silicon family: * |
| 179 | // * - Update AMD_F12_UNKNOWN whenever newer F12h steppings are added * |
| 180 | #define AMD_F12_UNKNOWN (AMD_FAMILY_UNKNOWN | AMD_F12_LN_B0) |
| 181 | |
| 182 | #define AMD_F12_LN_Ax (AMD_F12_LN_A0 | AMD_F12_LN_A1) |
| 183 | #define AMD_F12_LN_Bx (AMD_F12_LN_B0) |
| 184 | |
| 185 | #define AMD_F12_ALL (AMD_F12_LN_Ax | AMD_F12_LN_Bx) |
| 186 | |
| 187 | // Family 14h CPU_LOGICAL_ID.Revision equates |
| 188 | // ------------------------------------- |
| 189 | |
| 190 | // Family 14h ON steppings |
| 191 | #define AMD_F14_ON_A0 0x0000000000000001ull |
| 192 | #define AMD_F14_ON_A1 0x0000000000000002ull |
| 193 | #define AMD_F14_ON_B0 0x0000000000000004ull |
| 194 | #define AMD_F14_ON_C0 0x0000000000000008ull |
| 195 | // Family 14h KR steppings |
| 196 | #define AMD_F14_KR_A0 0x0000000000000100ull |
| 197 | #define AMD_F14_KR_A1 0x0000000000000200ull |
| 198 | #define AMD_F14_KR_B0 0x0000000000000400ull |
| 199 | |
| 200 | // Family 14h Unknown stepping |
| 201 | // * This equate is used to ensure that unknown CPU revisions are * |
| 202 | // * identified as the last known revision of the silicon family: * |
| 203 | // * - Update AMD_F14_UNKNOWN whenever newer F14h steppings are added * |
| 204 | #define AMD_F14_UNKNOWN (AMD_FAMILY_UNKNOWN | AMD_F14_KR_B0 | AMD_F14_ON_C0) |
| 205 | |
| 206 | #define AMD_F14_ON_Ax (AMD_F14_ON_A0 | AMD_F14_ON_A1) |
| 207 | #define AMD_F14_ON_Bx (AMD_F14_ON_B0) |
| 208 | #define AMD_F14_ON_Cx (AMD_F14_ON_C0) |
| 209 | #define AMD_F14_ON_ALL (AMD_F14_ON_Ax | AMD_F14_ON_Bx | AMD_F14_ON_Cx) |
| 210 | |
| 211 | #define AMD_F14_KR_Ax (AMD_F14_KR_A0 | AMD_F14_KR_A1) |
| 212 | #define AMD_F14_KR_Bx AMD_F14_KR_B0 |
| 213 | #define AMD_F14_KR_ALL (AMD_F14_KR_Ax | AMD_F14_KR_Bx) |
| 214 | |
| 215 | #define AMD_F14_ALL (AMD_F14_ON_ALL | AMD_F14_KR_ALL) |
| 216 | |
| 217 | // Family 15h CPU_LOGICAL_ID.Revision equates |
| 218 | // ------------------------------------- |
| 219 | |
| 220 | // Family 15h OROCHI steppings |
| 221 | #define AMD_F15_OR_A0 0x0000000000000001ull |
| 222 | #define AMD_F15_OR_A1 0x0000000000000002ull |
| 223 | #define AMD_F15_OR_B0 0x0000000000000004ull |
| 224 | #define AMD_F15_OR_B1 0x0000000000000008ull |
| 225 | #define AMD_F15_OR_B2 0x0000000000000010ull |
| 226 | // Family 15h TN steppings |
| 227 | #define AMD_F15_TN_A0 0x0000000000000100ull |
| 228 | #define AMD_F15_TN_A1 0x0000000000000200ull |
| 229 | // Family 15h Unknown stepping |
| 230 | // * This equate is used to ensure that unknown CPU revisions are * |
| 231 | // * identified as the last known revision of the silicon family: * |
| 232 | // * - Update AMD_F15_UNKNOWN whenever newer F15h steppings are added * |
| 233 | |
| 234 | #define AMD_F15_OR_Ax (AMD_F15_OR_A0 | AMD_F15_OR_A1) |
| 235 | #define AMD_F15_OR_Bx (AMD_F15_OR_B0 | AMD_F15_OR_B1 | AMD_F15_OR_B2) |
| 236 | #define AMD_F15_OR_GT_Ax (AMD_F15_OR_Bx) |
| 237 | #define AMD_F15_OR_LT_B1 (AMD_F15_OR_Ax | AMD_F15_OR_B0) |
| 238 | #define AMD_F15_OR_ALL (AMD_F15_OR_Ax | AMD_F15_OR_Bx) |
| 239 | |
| 240 | #define AMD_F15_TN_Ax (AMD_F15_TN_A0 | AMD_F15_TN_A1) |
| 241 | #define AMD_F15_TN_GT_A0 (AMD_F15_TN_ALL & ~AMD_F15_TN_A0) |
| 242 | #define AMD_F15_TN_ALL (AMD_F15_TN_Ax) |
| 243 | |
| 244 | |
| 245 | |
| 246 | |
| 247 | #endif // _CPU_FAM_REGISTERS_H_ |
| 248 | |