zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * AMD Family_15 Power Management related registers defination |
| 6 | * |
| 7 | * @xrefitem bom "File Content Label" "Release Content" |
| 8 | * @e project: AGESA |
| 9 | * @e sub-project: CPU/Family/0x15 |
| 10 | * @e \$Revision: 64491 $ @e \$Date: 2012-01-23 12:37:30 -0600 (Mon, 23 Jan 2012) $ |
| 11 | * |
| 12 | */ |
| 13 | /* |
| 14 | ****************************************************************************** |
| 15 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 16 | * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. |
| 17 | * All rights reserved. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 18 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 19 | * Redistribution and use in source and binary forms, with or without |
| 20 | * modification, are permitted provided that the following conditions are met: |
| 21 | * * Redistributions of source code must retain the above copyright |
| 22 | * notice, this list of conditions and the following disclaimer. |
| 23 | * * Redistributions in binary form must reproduce the above copyright |
| 24 | * notice, this list of conditions and the following disclaimer in the |
| 25 | * documentation and/or other materials provided with the distribution. |
| 26 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 27 | * its contributors may be used to endorse or promote products derived |
| 28 | * from this software without specific prior written permission. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 29 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 30 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 31 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 32 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 33 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 34 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 35 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 36 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 37 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 38 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 39 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 40 | ****************************************************************************** |
| 41 | */ |
| 42 | |
| 43 | #ifndef _CPUF15POWERMGMT_H_ |
| 44 | #define _CPUF15POWERMGMT_H_ |
| 45 | |
| 46 | /* |
| 47 | * Family 15h CPU Power Management MSR definitions |
| 48 | * |
| 49 | */ |
| 50 | |
| 51 | |
| 52 | /* Last Branch From IP Register 0x000001DB */ |
| 53 | #define MSR_BR_FROM 0x000001DBul |
| 54 | |
| 55 | /* P-state Current Limit Register 0xC0010061 */ |
| 56 | #define MSR_PSTATE_CURRENT_LIMIT 0xC0010061ul // F15 Shared |
| 57 | |
| 58 | /// Pstate Current Limit MSR Register |
| 59 | typedef struct { |
| 60 | UINT64 CurPstateLimit:3; ///< Current Pstate Limit |
| 61 | UINT64 :1; ///< Reserved |
| 62 | UINT64 PstateMaxVal:3; ///< Pstate Max Value |
| 63 | UINT64 :57; ///< Reserved |
| 64 | } PSTATE_CURLIM_MSR; |
| 65 | |
| 66 | |
| 67 | /* P-state Control Register 0xC0010062 */ |
| 68 | #define MSR_PSTATE_CTL 0xC0010062ul // F15 Shared |
| 69 | |
| 70 | /// Pstate Control MSR Register |
| 71 | typedef struct { |
| 72 | UINT64 PstateCmd:3; ///< Pstate change command |
| 73 | UINT64 :61; ///< Reserved |
| 74 | } PSTATE_CTRL_MSR; |
| 75 | |
| 76 | |
| 77 | /* P-state Status Register 0xC0010063 */ |
| 78 | #define MSR_PSTATE_STS 0xC0010063ul |
| 79 | |
| 80 | /// Pstate Status MSR Register |
| 81 | typedef struct { |
| 82 | UINT64 CurPstate:3; ///< Current Pstate |
| 83 | UINT64 :61; ///< Reserved |
| 84 | } PSTATE_STS_MSR; |
| 85 | |
| 86 | |
| 87 | /* P-state Registers 0xC001006[B:4] */ |
| 88 | #define MSR_PSTATE_0 0xC0010064ul |
| 89 | #define MSR_PSTATE_1 0xC0010065ul |
| 90 | #define MSR_PSTATE_2 0xC0010066ul |
| 91 | #define MSR_PSTATE_3 0xC0010067ul |
| 92 | #define MSR_PSTATE_4 0xC0010068ul |
| 93 | #define MSR_PSTATE_5 0xC0010069ul |
| 94 | #define MSR_PSTATE_6 0xC001006Aul |
| 95 | #define MSR_PSTATE_7 0xC001006Bul |
| 96 | |
| 97 | #define PS_REG_BASE MSR_PSTATE_0 /* P-state Register base */ |
| 98 | #define PS_MAX_REG MSR_PSTATE_7 /* Maximum P-State Register */ |
| 99 | #define PS_MIN_REG MSR_PSTATE_0 /* Minimum P-State Register */ |
| 100 | #define NM_PS_REG 8 /* number of P-state MSR registers */ |
| 101 | |
| 102 | /// P-state MSR with common field |
| 103 | typedef struct { |
| 104 | UINT64 :63; ///< CpuFid |
| 105 | UINT64 PsEnable:1; ///< Pstate Enable |
| 106 | } F15_PSTATE_MSR; |
| 107 | |
| 108 | |
| 109 | /* C-state Address Register 0xC0010073 */ |
| 110 | #define MSR_CSTATE_ADDRESS 0xC0010073ul |
| 111 | |
| 112 | /// C-state Address MSR Register |
| 113 | typedef struct { |
| 114 | UINT64 CstateAddr:16; ///< C-state address |
| 115 | UINT64 :48; ///< Reserved |
| 116 | } CSTATE_ADDRESS_MSR; |
| 117 | |
| 118 | |
| 119 | /* |
| 120 | * Family 15h CPU Power Management PCI definitions |
| 121 | * |
| 122 | */ |
| 123 | |
| 124 | /* Extended Memory Controller Configuration Low Register F2x1B0 */ |
| 125 | #define EXT_MEMCTRL_CFG_LOW_REG 0x1B0 |
| 126 | |
| 127 | /// Extended Memory Controller Configuration Low PCI Register |
| 128 | typedef struct { |
| 129 | UINT32 AdapPrefMissRatio:2; ///< Adaptive prefetch miss ratio |
| 130 | UINT32 AdapPrefPositiveStep:2; ///< Adaptive prefetch positive step |
| 131 | UINT32 AdapPrefNegativeStep:2; ///< Adaptive prefetch negative step |
| 132 | UINT32 :2; ///< Reserved |
| 133 | UINT32 CohPrefPrbLmt:3; ///< Coherent prefetch probe limit |
| 134 | UINT32 DisIoCohPref:1; ///< Disable coherent prefetched for IO |
| 135 | UINT32 EnSplitDctLimits:1; ///< Split DCT write limits enable |
| 136 | UINT32 SpecPrefDis:1; ///< Speculative prefetch disable |
| 137 | UINT32 SpecPrefMis:1; ///< Speculative prefetch predict miss |
| 138 | UINT32 SpecPrefThreshold:3; ///< Speculative prefetch threshold |
| 139 | UINT32 :4; ///< Reserved |
| 140 | UINT32 PrefFourConf:3; ///< Prefetch four-ahead confidence |
| 141 | UINT32 PrefFiveConf:3; ///< Prefetch five-ahead confidence |
| 142 | UINT32 DcqBwThrotWm:4; ///< Dcq bandwidth throttle watermark |
| 143 | } EXT_MEMCTRL_CFG_LOW_REGISTER; |
| 144 | |
| 145 | |
| 146 | /* Hardware thermal control register F3x64 */ |
| 147 | #define HTC_REG 0x64 |
| 148 | #define HTC_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, HTC_REG)) |
| 149 | |
| 150 | /// Hardware Thermal Control PCI Register |
| 151 | typedef struct { |
| 152 | UINT32 HtcEn:1; ///< HTC Enable |
| 153 | UINT32 :3; ///< Reserved |
| 154 | UINT32 HtcAct:1; ///< HTC Active State |
| 155 | UINT32 HtcActSts:1; ///< HTC Active Status |
| 156 | UINT32 PslApicHiEn:1; ///< P-state limit higher APIC interrupt enable |
| 157 | UINT32 PslApicLoEn:1; ///< P-state limit lower APIC interrupt enable |
| 158 | UINT32 :8; ///< Reserved |
| 159 | UINT32 HtcTmpLmt:7; ///< HTC temperature limit |
| 160 | UINT32 HtcSlewSel:1; ///< HTC slew-controlled temp select |
| 161 | UINT32 HtcHystLmt:4; ///< HTC hysteresis |
| 162 | UINT32 HtcPstateLimit:3; ///< HTC P-state limit select |
| 163 | UINT32 :1; ///< Reserved |
| 164 | } HTC_REGISTER; |
| 165 | |
| 166 | |
| 167 | /* Software P-state limit register F3x68 */ |
| 168 | #define SW_PS_LIMIT_REG 0x68 |
| 169 | |
| 170 | /// Software P-state Limit PCI Register |
| 171 | typedef struct { |
| 172 | UINT32 :5; ///< Reserved |
| 173 | UINT32 SwPstateLimitEn:1; ///< Software P-state limit enable |
| 174 | UINT32 :22; ///< Reserved |
| 175 | UINT32 SwPstateLimit:3; ///< HTC P-state limit select |
| 176 | UINT32 :1; ///< Reserved |
| 177 | } SW_PS_LIMIT_REGISTER; |
| 178 | |
| 179 | /* ACPI Power State Control Registers F3x84:80 */ |
| 180 | |
| 181 | /// System Management Action Field (SMAF) Register |
| 182 | typedef struct { |
| 183 | UINT8 CpuPrbEn:1; ///< CPU direct probe enable |
| 184 | UINT8 NbLowPwrEn:1; ///< Northbridge low-power enable |
| 185 | UINT8 NbGateEn:1; ///< Northbridge gate enable |
| 186 | UINT8 Reserved:2; ///< Reserved |
| 187 | UINT8 ClkDivisor:3; ///< Clock divisor |
| 188 | } SMAF_REGISTER; |
| 189 | |
| 190 | /// union type for ACPI State SMAF setting |
| 191 | typedef union { |
| 192 | UINT8 SMAFValue; ///< SMAF raw value |
| 193 | SMAF_REGISTER SMAF; ///< SMAF structure |
| 194 | } ACPI_STATE_SMAF; |
| 195 | |
| 196 | /// ACPI Power State Control Register F3x80 |
| 197 | typedef struct { |
| 198 | ACPI_STATE_SMAF C2; ///< [7:0] SMAF Code 000b - C2 |
| 199 | ACPI_STATE_SMAF C1eLinkInit; ///< [15:8] SMAF Code 001b - C1e or Link init |
| 200 | ACPI_STATE_SMAF SmafAct2; ///< [23:16] SMAF Code 010b |
| 201 | ACPI_STATE_SMAF S1; ///< [31:24] SMAF Code 011b - S1 |
| 202 | } ACPI_PSC_0_REGISTER; |
| 203 | |
| 204 | /// ACPI Power State Control Register F3x84 |
| 205 | typedef struct { |
| 206 | ACPI_STATE_SMAF S3; ///< [7:0] SMAF Code 100b - S3 |
| 207 | ACPI_STATE_SMAF Throttling; ///< [15:8] SMAF Code 101b - Throttling |
| 208 | ACPI_STATE_SMAF S4S5; ///< [23:16] SMAF Code 110b - S4/S5 |
| 209 | ACPI_STATE_SMAF C1; ///< [31:24] SMAF Code 111b - C1 |
| 210 | } ACPI_PSC_4_REGISTER; |
| 211 | |
| 212 | |
| 213 | /* Popup P-state Register F3xA8 */ |
| 214 | #define POPUP_PSTATE_REG 0xA8 |
| 215 | #define POPUP_PSTATE_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, POPUP_PSTATE_REG)) |
| 216 | |
| 217 | /// Popup P-state Register |
| 218 | typedef struct { |
| 219 | UINT32 :29; ///< Reserved |
| 220 | UINT32 PopDownPstate:3; ///< PopDownPstate |
| 221 | } POPUP_PSTATE_REGISTER; |
| 222 | |
| 223 | |
| 224 | /* Clock Power/Timing Control 2 Register F3xDC */ |
| 225 | #define CPTC2_REG 0xDC |
| 226 | #define CPTC2_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, CPTC2_REG)) |
| 227 | |
| 228 | /// Clock Power Timing Control 2 PCI Register |
| 229 | typedef struct { |
| 230 | UINT32 :8; ///< Reserved |
| 231 | UINT32 PstateMaxVal:3; ///< P-state maximum value |
| 232 | UINT32 :1; ///< Reserved |
| 233 | UINT32 NbsynPtrAdj:3; ///< NB/Core sync FIFO ptr adjust |
| 234 | UINT32 :1; ///< Reserved |
| 235 | UINT32 CacheFlushOnHaltCtl:3; ///< Cache flush on halt control |
| 236 | UINT32 CacheFlushOnHaltTmr:7; ///< Cache flush on halt timer |
| 237 | UINT32 IgnCpuPrbEn:1; ///< ignore CPU probe enable |
| 238 | UINT32 :5; ///< Reserved |
| 239 | } CLK_PWR_TIMING_CTRL2_REGISTER; |
| 240 | |
| 241 | |
| 242 | /* Core Performance Boost Control Register D18F4x15C */ |
| 243 | #define CPB_CTRL_REG 0x15C |
| 244 | #define CPB_CTRL_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CPB_CTRL_REG)) |
| 245 | |
| 246 | /// Core Performance Boost Control Register of Family 15h common aceess |
| 247 | typedef struct { |
| 248 | UINT32 BoostSrc:2; ///< Boost source |
| 249 | UINT32 NumBoostStates:3; ///< Number of boosted states |
| 250 | UINT32 :2; ///< Reserved |
| 251 | UINT32 ApmMasterEn:1; ///< APM master enable |
| 252 | UINT32 :23; ///< Reserved |
| 253 | UINT32 BoostLock:1; ///< |
| 254 | } F15_CPB_CTRL_REGISTER; |
| 255 | |
| 256 | |
| 257 | #define NM_NB_PS_REG 4 /* Number of NB P-state registers */ |
| 258 | |
| 259 | /* Northbridge P-state */ |
| 260 | #define NB_PSTATE_0 0x160 |
| 261 | #define NB_PSTATE_0_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_5, NB_PSTATE_0)) |
| 262 | |
| 263 | #define NB_PSTATE_1 0x164 |
| 264 | #define NB_PSTATE_1_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_5, NB_PSTATE_1)) |
| 265 | |
| 266 | #define NB_PSTATE_2 0x168 |
| 267 | #define NB_PSTATE_2_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_5, NB_PSTATE_2)) |
| 268 | |
| 269 | #define NB_PSTATE_3 0x16C |
| 270 | #define NB_PSTATE_3_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_5, NB_PSTATE_3)) |
| 271 | |
| 272 | |
| 273 | /* Northbridge P-state Status */ |
| 274 | #define F15_NB_PSTATE_CTRL 0x170 |
| 275 | #define F15_NB_PSTATE_CTRL_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_5, F15_NB_PSTATE_CTRL)) |
| 276 | |
| 277 | /// Northbridge P-state Control Register |
| 278 | typedef struct { |
| 279 | UINT32 NbPstateMaxVal:2; ///< NB P-state maximum value |
| 280 | UINT32 :1; ///< Reserved |
| 281 | UINT32 NbPstateLo:2; ///< NB P-state low |
| 282 | UINT32 :1; ///< Reserved |
| 283 | UINT32 NbPstateHi:2; ///< NB P-state high |
| 284 | UINT32 :1; ///< Reserved |
| 285 | UINT32 NbPstateThreshold:3; ///< NB P-state threshold |
| 286 | UINT32 :1; ///< Reserved |
| 287 | UINT32 NbPstateDisOnP0:1; ///< NB P-state disable on P0 |
| 288 | UINT32 SwNbPstateLoDis:1; ///< Software NB P-state low disable |
| 289 | UINT32 :17; ///< Reserved |
| 290 | } F15_NB_PSTATE_CTRL_REGISTER; |
| 291 | |
| 292 | |
| 293 | #endif /* _CPUF15POWERMGMT_H */ |