zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * AMD Family_15 P-State power check |
| 6 | * |
| 7 | * Performs the "Processor-Systemboard Power Delivery Compatibility Check" as |
| 8 | * described in the BKDG. |
| 9 | * |
| 10 | * @xrefitem bom "File Content Label" "Release Content" |
| 11 | * @e project: AGESA |
| 12 | * @e sub-project: CPU/Family/0x15 |
| 13 | * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ |
| 14 | * |
| 15 | */ |
| 16 | /* |
| 17 | ****************************************************************************** |
| 18 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 19 | * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. |
| 20 | * All rights reserved. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 21 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 22 | * Redistribution and use in source and binary forms, with or without |
| 23 | * modification, are permitted provided that the following conditions are met: |
| 24 | * * Redistributions of source code must retain the above copyright |
| 25 | * notice, this list of conditions and the following disclaimer. |
| 26 | * * Redistributions in binary form must reproduce the above copyright |
| 27 | * notice, this list of conditions and the following disclaimer in the |
| 28 | * documentation and/or other materials provided with the distribution. |
| 29 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 30 | * its contributors may be used to endorse or promote products derived |
| 31 | * from this software without specific prior written permission. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 32 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 33 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 34 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 35 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 36 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 37 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 38 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 39 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 40 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 41 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 42 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 43 | ****************************************************************************** |
| 44 | */ |
| 45 | |
| 46 | /*---------------------------------------------------------------------------------------- |
| 47 | * M O D U L E S U S E D |
| 48 | *---------------------------------------------------------------------------------------- |
| 49 | */ |
| 50 | #include "AGESA.h" |
| 51 | #include "amdlib.h" |
| 52 | #include "cpuF15PowerMgmt.h" |
| 53 | #include "cpuRegisters.h" |
| 54 | #include "cpuApicUtilities.h" |
| 55 | #include "cpuFamilyTranslation.h" |
| 56 | #include "cpuF15PowerCheck.h" |
| 57 | #include "cpuServices.h" |
| 58 | #include "GeneralServices.h" |
| 59 | #include "OptionMultiSocket.h" |
| 60 | #include "Filecode.h" |
| 61 | CODE_GROUP (G3_DXE) |
| 62 | RDATA_GROUP (G3_DXE) |
| 63 | |
| 64 | #define FILECODE PROC_CPU_FAMILY_0X15_CPUF15POWERCHECK_FILECODE |
| 65 | |
| 66 | /*---------------------------------------------------------------------------------------- |
| 67 | * D E F I N I T I O N S A N D M A C R O S |
| 68 | *---------------------------------------------------------------------------------------- |
| 69 | */ |
| 70 | |
| 71 | /*---------------------------------------------------------------------------------------- |
| 72 | * T Y P E D E F S A N D S T R U C T U R E S |
| 73 | *---------------------------------------------------------------------------------------- |
| 74 | */ |
| 75 | |
| 76 | /*---------------------------------------------------------------------------------------- |
| 77 | * P R O T O T Y P E S O F L O C A L F U N C T I O N S |
| 78 | *---------------------------------------------------------------------------------------- |
| 79 | */ |
| 80 | VOID |
| 81 | STATIC |
| 82 | F15PmPwrCheckCore ( |
| 83 | IN VOID *ErrorData, |
| 84 | IN AMD_CONFIG_PARAMS *StdHeader |
| 85 | ); |
| 86 | |
| 87 | VOID |
| 88 | STATIC |
| 89 | F15PmPwrChkCopyPstate ( |
| 90 | IN UINT8 Dest, |
| 91 | IN UINT8 Src, |
| 92 | IN AMD_CONFIG_PARAMS *StdHeader |
| 93 | ); |
| 94 | |
| 95 | /*---------------------------------------------------------------------------------------- |
| 96 | * E X P O R T E D F U N C T I O N S |
| 97 | *---------------------------------------------------------------------------------------- |
| 98 | */ |
| 99 | extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration; |
| 100 | /*---------------------------------------------------------------------------------------*/ |
| 101 | /** |
| 102 | * Family 15h core 0 entry point for performing the family 15h Processor- |
| 103 | * Systemboard Power Delivery Check. |
| 104 | * |
| 105 | * The steps are as follows: |
| 106 | * 1. Starting with P0, loop through all P-states until a passing state is |
| 107 | * found. A passing state is one in which the current required by the |
| 108 | * CPU is less than the maximum amount of current that the system can |
| 109 | * provide to the CPU. If P0 is under the limit, no further action is |
| 110 | * necessary. |
| 111 | * 2. If at least one P-State is under the limit & at least one P-State is |
| 112 | * over the limit, the BIOS must: |
| 113 | * a. If the processor's current P-State is disabled by the power check, |
| 114 | * then the BIOS must request a transition to an enabled P-state |
| 115 | * using MSRC001_0062[PstateCmd] and wait for MSRC001_0063[CurPstate] |
| 116 | * to reflect the new value. |
| 117 | * b. Copy the contents of the enabled P-state MSRs to the highest |
| 118 | * performance P-state locations. |
| 119 | * c. Request a P-state transition to the P-state MSR containing the |
| 120 | * COF/VID values currently applied. |
| 121 | * d. If a subset of boosted P-states are disabled, then copy the contents |
| 122 | * of the highest performance boosted P-state still enabled to the |
| 123 | * boosted P-states that have been disabled. |
| 124 | * e. If all boosted P-states are disabled, then program D18F4x15C[BoostSrc] |
| 125 | * to zero. |
| 126 | * f. Adjust the following P-state parameters affected by the P-state |
| 127 | * MSR copy by subtracting the number of P-states that are disabled |
| 128 | * by the power check. |
| 129 | * 1. F3x64[HtcPstateLimit] |
| 130 | * 2. F3x68[SwPstateLimit] |
| 131 | * 3. F3xDC[PstateMaxVal] |
| 132 | * 3. If all P-States are over the limit, the BIOS must: |
| 133 | * a. If the processor's current P-State is !=F3xDC[PstateMaxVal], then |
| 134 | * write F3xDC[PstateMaxVal] to MSRC001_0062[PstateCmd] and wait for |
| 135 | * MSRC001_0063[CurPstate] to reflect the new value. |
| 136 | * b. If MSRC001_0061[PstateMaxVal]!=000b, copy the contents of the P-state |
| 137 | * MSR pointed to by F3xDC[PstateMaxVal] to the software P0 MSR. |
| 138 | * Write 000b to MSRC001_0062[PstateCmd] and wait for MSRC001_0063 |
| 139 | * [CurPstate] to reflect the new value. |
| 140 | * c. Adjust the following P-state parameters to zero: |
| 141 | * 1. F3x64[HtcPstateLimit] |
| 142 | * 2. F3x68[SwPstateLimit] |
| 143 | * 3. F3xDC[PstateMaxVal] |
| 144 | * d. Program D18F4x15C[BoostSrc] to zero. |
| 145 | * |
| 146 | * @param[in] FamilySpecificServices The current Family Specific Services. |
| 147 | * @param[in] CpuEarlyParams Service parameters |
| 148 | * @param[in] StdHeader Config handle for library and services. |
| 149 | * |
| 150 | */ |
| 151 | VOID |
| 152 | F15PmPwrCheck ( |
| 153 | IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, |
| 154 | IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams, |
| 155 | IN AMD_CONFIG_PARAMS *StdHeader |
| 156 | ) |
| 157 | { |
| 158 | UINT8 DisPsNum; |
| 159 | UINT8 PsMaxVal; |
| 160 | UINT8 Pstate; |
| 161 | UINT32 ProcIddMax; |
| 162 | UINT32 LocalPciRegister; |
| 163 | UINT32 Socket; |
| 164 | UINT32 Module; |
| 165 | UINT32 Core; |
| 166 | UINT32 AndMask; |
| 167 | UINT32 OrMask; |
| 168 | UINT32 PstateLimit; |
| 169 | PCI_ADDR PciAddress; |
| 170 | UINT64 LocalMsrRegister; |
| 171 | AP_TASK TaskPtr; |
| 172 | AGESA_STATUS IgnoredSts; |
| 173 | PWRCHK_ERROR_DATA ErrorData; |
| 174 | UINT32 NumModules; |
| 175 | UINT32 HighCore; |
| 176 | UINT32 LowCore; |
| 177 | UINT32 ModuleIndex; |
| 178 | |
| 179 | |
| 180 | // get the socket number |
| 181 | IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts); |
| 182 | ErrorData.SocketNumber = (UINT8) Socket; |
| 183 | |
| 184 | ASSERT (Core == 0); |
| 185 | |
| 186 | // get the Max P-state value |
| 187 | for (PsMaxVal = NM_PS_REG - 1; PsMaxVal != 0; --PsMaxVal) { |
| 188 | LibAmdMsrRead (PS_REG_BASE + PsMaxVal, &LocalMsrRegister, StdHeader); |
| 189 | if (((F15_PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1) { |
| 190 | break; |
| 191 | } |
| 192 | } |
| 193 | |
| 194 | ErrorData.HwPstateNumber = (UINT8) (PsMaxVal + 1); |
| 195 | |
| 196 | // Starting with P0, loop through all P-states until a passing state is |
| 197 | // found. A passing state is one in which the current required by the |
| 198 | // CPU is less than the maximum amount of current that the system can |
| 199 | // provide to the CPU. If P0 is under the limit, no further action is |
| 200 | // necessary. |
| 201 | DisPsNum = 0; |
| 202 | for (Pstate = 0; Pstate < ErrorData.HwPstateNumber; Pstate++) { |
| 203 | if (FamilySpecificServices->GetProcIddMax (FamilySpecificServices, Pstate, &ProcIddMax, StdHeader)) { |
| 204 | if (ProcIddMax > CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].CurrentLimit) { |
| 205 | // Add to event log the Pstate that exceeded the current limit |
| 206 | PutEventLog (AGESA_WARNING, |
| 207 | CPU_EVENT_PM_PSTATE_OVERCURRENT, |
| 208 | Socket, Pstate, 0, 0, StdHeader); |
| 209 | DisPsNum++; |
| 210 | } else { |
| 211 | break; |
| 212 | } |
| 213 | } |
| 214 | } |
| 215 | |
| 216 | ErrorData.AllowablePstateNumber = ((PsMaxVal + 1) - DisPsNum); |
| 217 | |
| 218 | if (ErrorData.AllowablePstateNumber == 0) { |
| 219 | PutEventLog (AGESA_FATAL, |
| 220 | CPU_EVENT_PM_ALL_PSTATE_OVERCURRENT, |
| 221 | Socket, 0, 0, 0, StdHeader); |
| 222 | } |
| 223 | |
| 224 | if (DisPsNum != 0) { |
| 225 | GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts); |
| 226 | PciAddress.Address.Function = FUNC_4; |
| 227 | PciAddress.Address.Register = CPB_CTRL_REG; |
| 228 | LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F4x15C |
| 229 | ErrorData.NumberOfBoostStates = (UINT8) ((F15_CPB_CTRL_REGISTER *) &LocalPciRegister)->NumBoostStates; |
| 230 | |
| 231 | if (DisPsNum >= ErrorData.NumberOfBoostStates) { |
| 232 | // If all boosted P-states are disabled, then program D18F4x15C[BoostSrc] to zero. |
| 233 | AndMask = 0xFFFFFFFF; |
| 234 | ((F15_CPB_CTRL_REGISTER *) &AndMask)->BoostSrc = 0; |
| 235 | OrMask = 0x00000000; |
| 236 | OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F4x15C |
| 237 | |
| 238 | ErrorData.NumberOfSwPstatesDisabled = DisPsNum - ErrorData.NumberOfBoostStates; |
| 239 | } else { |
| 240 | ErrorData.NumberOfSwPstatesDisabled = 0; |
| 241 | } |
| 242 | |
| 243 | NumModules = GetPlatformNumberOfModules (); |
| 244 | |
| 245 | // Only execute this loop if this is an MCM. |
| 246 | if (NumModules > 1) { |
| 247 | |
| 248 | // Since the P-State MSRs are shared across a |
| 249 | // node, we only need to set one core in the node for the modified number of supported p-states |
| 250 | // to be reported across all of the cores in the module. |
| 251 | TaskPtr.FuncAddress.PfApTaskI = F15PmPwrCheckCore; |
| 252 | TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (PWRCHK_ERROR_DATA); |
| 253 | TaskPtr.DataTransfer.DataPtr = &ErrorData; |
| 254 | TaskPtr.DataTransfer.DataTransferFlags = 0; |
| 255 | TaskPtr.ExeFlags = WAIT_FOR_CORE; |
| 256 | |
| 257 | for (ModuleIndex = 0; ModuleIndex < NumModules; ModuleIndex++) { |
| 258 | // Execute the P-State reduction code on the module's primary core only. |
| 259 | // Skip this code for the BSC's module. |
| 260 | if (ModuleIndex != Module) { |
| 261 | if (GetGivenModuleCoreRange (Socket, ModuleIndex, &LowCore, &HighCore, StdHeader)) { |
| 262 | ApUtilRunCodeOnSocketCore ((UINT8)Socket, (UINT8)LowCore, &TaskPtr, StdHeader); |
| 263 | } |
| 264 | } |
| 265 | } |
| 266 | } |
| 267 | |
| 268 | // Path for SCM and the BSC |
| 269 | F15PmPwrCheckCore (&ErrorData, StdHeader); |
| 270 | |
| 271 | // Final Step |
| 272 | // F3x64[HtPstatelimit] -= disPsNum |
| 273 | // F3x68[SwPstateLimit] -= disPsNum |
| 274 | // F3xDC[PstateMaxVal] -= disPsNum |
| 275 | |
| 276 | PciAddress.Address.Function = FUNC_3; |
| 277 | PciAddress.Address.Register = HTC_REG; |
| 278 | AndMask = 0xFFFFFFFF; |
| 279 | ((HTC_REGISTER *) &AndMask)->HtcPstateLimit = 0; |
| 280 | OrMask = 0x00000000; |
| 281 | LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F3x64 |
| 282 | PstateLimit = ((HTC_REGISTER *) &LocalPciRegister)->HtcPstateLimit; |
| 283 | if (PstateLimit > ErrorData.NumberOfSwPstatesDisabled) { |
| 284 | PstateLimit -= ErrorData.NumberOfSwPstatesDisabled; |
| 285 | ((HTC_REGISTER *) &OrMask)->HtcPstateLimit = PstateLimit; |
| 286 | } |
| 287 | OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3x64 |
| 288 | |
| 289 | PciAddress.Address.Register = SW_PS_LIMIT_REG; |
| 290 | AndMask = 0xFFFFFFFF; |
| 291 | ((SW_PS_LIMIT_REGISTER *) &AndMask)->SwPstateLimit = 0; |
| 292 | OrMask = 0x00000000; |
| 293 | LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F3x68 |
| 294 | PstateLimit = ((SW_PS_LIMIT_REGISTER *) &LocalPciRegister)->SwPstateLimit; |
| 295 | if (PstateLimit > ErrorData.NumberOfSwPstatesDisabled) { |
| 296 | PstateLimit -= ErrorData.NumberOfSwPstatesDisabled; |
| 297 | ((SW_PS_LIMIT_REGISTER *) &OrMask)->SwPstateLimit = PstateLimit; |
| 298 | } |
| 299 | OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3x68 |
| 300 | |
| 301 | PciAddress.Address.Register = CPTC2_REG; |
| 302 | AndMask = 0xFFFFFFFF; |
| 303 | ((CLK_PWR_TIMING_CTRL2_REGISTER *) &AndMask)->PstateMaxVal = 0; |
| 304 | OrMask = 0x00000000; |
| 305 | LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F3xDC |
| 306 | PstateLimit = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &LocalPciRegister)->PstateMaxVal; |
| 307 | if (PstateLimit > ErrorData.NumberOfSwPstatesDisabled) { |
| 308 | PstateLimit -= ErrorData.NumberOfSwPstatesDisabled; |
| 309 | ((CLK_PWR_TIMING_CTRL2_REGISTER *) &OrMask)->PstateMaxVal = PstateLimit; |
| 310 | } |
| 311 | OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3xDC |
| 312 | } |
| 313 | } |
| 314 | |
| 315 | |
| 316 | /*---------------------------------------------------------------------------------------*/ |
| 317 | /** |
| 318 | * Core-level error handler called if any p-states were determined to be out |
| 319 | * of range for the mother board. |
| 320 | * |
| 321 | * This function implements steps 2a-c and 3a-c on each core. |
| 322 | * |
| 323 | * @param[in] ErrorData Details about the error condition. |
| 324 | * @param[in] StdHeader Config handle for library and services. |
| 325 | * |
| 326 | */ |
| 327 | VOID |
| 328 | STATIC |
| 329 | F15PmPwrCheckCore ( |
| 330 | IN VOID *ErrorData, |
| 331 | IN AMD_CONFIG_PARAMS *StdHeader |
| 332 | ) |
| 333 | { |
| 334 | UINT8 i; |
| 335 | UINT8 HwPsMaxVal; |
| 336 | UINT8 SwPsMaxVal; |
| 337 | UINT8 HwDisPsNum; |
| 338 | UINT8 CurrentSwPs; |
| 339 | UINT8 PsDisableCount; |
| 340 | UINT64 LocalMsrRegister; |
| 341 | CPU_SPECIFIC_SERVICES *FamilySpecificServices; |
| 342 | |
| 343 | if (IsCorePairPrimary (FirstCoreIsComputeUnitPrimary, StdHeader)) { |
| 344 | // P-state MSRs are shared, so only 1 core per compute unit needs to perform this |
| 345 | GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); |
| 346 | HwPsMaxVal = (((PWRCHK_ERROR_DATA *) ErrorData)->HwPstateNumber - 1); |
| 347 | HwDisPsNum = (((PWRCHK_ERROR_DATA *) ErrorData)->HwPstateNumber - |
| 348 | ((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber); |
| 349 | |
| 350 | LibAmdMsrRead (MSR_PSTATE_STS, &LocalMsrRegister, StdHeader); |
| 351 | CurrentSwPs = (UINT8) (((PSTATE_STS_MSR *) &LocalMsrRegister)->CurPstate); |
| 352 | LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &LocalMsrRegister, StdHeader); |
| 353 | SwPsMaxVal = (UINT8) (((PSTATE_CURLIM_MSR *) &LocalMsrRegister)->PstateMaxVal); |
| 354 | PsDisableCount = 0; |
| 355 | |
| 356 | if (((PWRCHK_ERROR_DATA *) ErrorData)->AllowablePstateNumber == 0) { |
| 357 | // All P-States are over the limit. |
| 358 | |
| 359 | // Step 1 |
| 360 | // Transition to Pstate Max if not there already |
| 361 | if (CurrentSwPs != SwPsMaxVal) { |
| 362 | FamilySpecificServices->TransitionPstate (FamilySpecificServices, SwPsMaxVal, (BOOLEAN) TRUE, StdHeader); |
| 363 | } |
| 364 | |
| 365 | // Step 2 |
| 366 | // If Pstate Max is not P0, copy Pstate max contents to P0 and switch |
| 367 | // to P0. |
| 368 | if (SwPsMaxVal != 0) { |
| 369 | F15PmPwrChkCopyPstate (((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfBoostStates, HwPsMaxVal, StdHeader); |
| 370 | FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 0, (BOOLEAN) TRUE, StdHeader); |
| 371 | } |
| 372 | |
| 373 | // Disable all SW P-states except P0 |
| 374 | PsDisableCount = ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled - 1; |
| 375 | } else { |
| 376 | // At least one P-State is under the limit & at least one P-State is |
| 377 | // over the limit. |
| 378 | if (((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfBoostStates > HwDisPsNum) { |
| 379 | // A subset of boosted P-states are disabled. Copy the contents of the |
| 380 | // highest performance boosted P-state still enabled to the boosted |
| 381 | // P-states that have been disabled. |
| 382 | for (i = 0; i < HwDisPsNum; i++) { |
| 383 | F15PmPwrChkCopyPstate (i, HwDisPsNum, StdHeader); |
| 384 | } |
| 385 | } else if (((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled != 0) { |
| 386 | // Move remaining P-state register(s) up |
| 387 | // Step 1 |
| 388 | // Transition to a valid Pstate if current Pstate has been disabled |
| 389 | if (CurrentSwPs < ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled) { |
| 390 | FamilySpecificServices->TransitionPstate (FamilySpecificServices, ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled, (BOOLEAN) TRUE, StdHeader); |
| 391 | CurrentSwPs = ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled; |
| 392 | } |
| 393 | |
| 394 | // Step 2 |
| 395 | // Move enabled Pstates up and disable the remainder |
| 396 | for (i = ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfBoostStates; (i + ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled) <= HwPsMaxVal; i++) { |
| 397 | F15PmPwrChkCopyPstate (i, (i + ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled), StdHeader); |
| 398 | } |
| 399 | |
| 400 | // Step 3 |
| 401 | // Transition to current COF/VID at shifted location |
| 402 | CurrentSwPs = (CurrentSwPs - ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled); |
| 403 | FamilySpecificServices->TransitionPstate (FamilySpecificServices, CurrentSwPs, (BOOLEAN) TRUE, StdHeader); |
| 404 | |
| 405 | // Disable the appropriate number of P-states |
| 406 | PsDisableCount = ((PWRCHK_ERROR_DATA *) ErrorData)->NumberOfSwPstatesDisabled; |
| 407 | } |
| 408 | } |
| 409 | // Disable the appropriate P-states if any, starting from HW Pmin |
| 410 | for (i = 0; i < PsDisableCount; i++) { |
| 411 | FamilySpecificServices->DisablePstate (FamilySpecificServices, (HwPsMaxVal - i), StdHeader); |
| 412 | } |
| 413 | } |
| 414 | } |
| 415 | |
| 416 | |
| 417 | /*---------------------------------------------------------------------------------------*/ |
| 418 | /** |
| 419 | * Copies the contents of one P-State MSR to another. |
| 420 | * |
| 421 | * @param[in] Dest Destination p-state number |
| 422 | * @param[in] Src Source p-state number |
| 423 | * @param[in] StdHeader Config handle for library and services |
| 424 | * |
| 425 | */ |
| 426 | VOID |
| 427 | STATIC |
| 428 | F15PmPwrChkCopyPstate ( |
| 429 | IN UINT8 Dest, |
| 430 | IN UINT8 Src, |
| 431 | IN AMD_CONFIG_PARAMS *StdHeader |
| 432 | ) |
| 433 | { |
| 434 | UINT64 LocalMsrRegister; |
| 435 | |
| 436 | LibAmdMsrRead ((UINT32) (PS_REG_BASE + Src), &LocalMsrRegister, StdHeader); |
| 437 | LibAmdMsrWrite ((UINT32) (PS_REG_BASE + Dest), &LocalMsrRegister, StdHeader); |
| 438 | } |
| 439 | |