Gitiles
Code Review Sign In
review.coreboot.org / coreboot / 9a458e4e58edbfc154dce007961514b5c31cf7aa / . / src / vendorcode / amd / agesa / f15tn / Proc / CPU / Family / 0x15 / cpuF15MmioMap.h
blob: 2a5d7f6adfb69be2bd129b580d5cc3c89c09b3af [file] [log] [blame]
zbao7d94cf92012-07-02 14:19:14 +0800[diff] [blame]1/* $NoKeywords:$ */
2/**
3 * @file
4 *
5 * AMD Family_15 MMIO map manager
6 *
7 * manage MMIO base/limit registers.
8 *
9 * @xrefitem bom "File Content Label" "Release Content"
10 * @e project: AGESA
11 * @e sub-project: CPU/Family/0x15
12 * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
13 *
14 */
15/*
16 ******************************************************************************
17 *
Siyuan Wang641f00c2013-06-08 11:50:55 +0800[diff] [blame]18 * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
19 * All rights reserved.
zbao7d94cf92012-07-02 14:19:14 +0800[diff] [blame]20 *
Siyuan Wang641f00c2013-06-08 11:50:55 +0800[diff] [blame]21 * Redistribution and use in source and binary forms, with or without
22 * modification, are permitted provided that the following conditions are met:
23 * * Redistributions of source code must retain the above copyright
24 * notice, this list of conditions and the following disclaimer.
25 * * Redistributions in binary form must reproduce the above copyright
26 * notice, this list of conditions and the following disclaimer in the
27 * documentation and/or other materials provided with the distribution.
28 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
29 * its contributors may be used to endorse or promote products derived
30 * from this software without specific prior written permission.
zbao7d94cf92012-07-02 14:19:14 +0800[diff] [blame]31 *
Siyuan Wang641f00c2013-06-08 11:50:55 +0800[diff] [blame]32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
34 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
36 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
37 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
38 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
39 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
41 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
zbao7d94cf92012-07-02 14:19:14 +0800[diff] [blame]42 ******************************************************************************
43 */
44
45#ifndef _CPU_F15_MMIO_MAP_H_
46#define _CPU_F15_MMIO_MAP_H_
47
48
49/*---------------------------------------------------------------------------------------
50 * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
51 *---------------------------------------------------------------------------------------
52 */
53
54
55/*---------------------------------------------------------------------------------------
56 * D E F I N I T I O N S A N D M A C R O S
57 *---------------------------------------------------------------------------------------
58 */
59#define MMIO_REG_PAIR_NUM 12
60
61#define CONF_MAP_RANGE_0 0xE0
62#define CONF_MAP_RANGE_1 0xE4
63#define CONF_MAP_RANGE_2 0xE8
64#define CONF_MAP_RANGE_3 0xEC
65#define CONF_MAP_NUM 4
66/*---------------------------------------------------------------------------------------
67 * T Y P E D E F S, S T R U C T U R E S, E N U M S
68 *---------------------------------------------------------------------------------------
69 */
70/// MMIO base low
71typedef struct {
72 UINT32 RE:1; ///< Read enable
73 UINT32 WE:1; ///< Write enable
74 UINT32 CpuDis:1; ///< CPU Disable
75 UINT32 Lock:1; ///< Lock
76 UINT32 :4; ///< Reserved
77 UINT32 MmioBase:24; ///< MMIO base address register bits[39:16]
78} MMIO_BASE_LOW;
79
80/// MMIO limit low
81typedef struct {
82 UINT32 DstNode:3; ///< Destination node ID bits
83 UINT32 :1; ///< Reserved
84 UINT32 DstLink:2; ///< Destination link ID
85 UINT32 DstSubLink:1; ///< Destination sublink
86 UINT32 NP:1; ///< Non-posted
87 UINT32 MmioLimit:24; ///< MMIO limit address register bits[39:16]
88} MMIO_LIMIT_LOW;
89
90/// MMIO base/limit high
91typedef struct {
92 UINT32 MmioBase:8; ///< MMIO base address register bits[47:40]
93 UINT32 :8; ///< Reserved
94 UINT32 MmioLimit:8; ///< MMIO limit address register bits[47:40]
95 UINT32 :8; ///< Reserved
96} MMIO_BASE_LIMIT_HI;
97
98/// MMIO base/limit high
99typedef struct {
100 UINT32 RE:1; ///< Read enable
101 UINT32 WE:1; ///< Write enable
102 UINT32 DevCmpEn:1; ///< Device number compare mode enable
103 UINT32 :1; ///< Reserved
104 UINT32 DstNode:3; ///< Destination node ID bits
105 UINT32 :1; ///< Reserved
106 UINT32 DstLink:2; ///< Destination link ID
107 UINT32 DstSubLink:1; ///< Destination sublink
108 UINT32 :5; ///< Reserved
109 UINT32 BusNumBase:8; ///< Bus number base bits
110 UINT32 BusNumLimit:8; ///< Bus number limit bits
111} CONFIGURATION_MAP;
112
113/*---------------------------------------------------------------------------------------
114 * F U N C T I O N P R O T O T Y P E
115 *---------------------------------------------------------------------------------------
116 */
117
118#endif // _CPU_F15_MMIO_MAP_H_