zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * AMD CRAT Record Creation API, and related functions for Family 15h. |
| 6 | * |
| 7 | * Contains code that produce the CRAT related information. |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: CPU/Family/0x15 |
| 12 | * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ |
| 13 | * |
| 14 | */ |
| 15 | /***************************************************************************** |
| 16 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 17 | * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. |
| 18 | * All rights reserved. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 19 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 20 | * Redistribution and use in source and binary forms, with or without |
| 21 | * modification, are permitted provided that the following conditions are met: |
| 22 | * * Redistributions of source code must retain the above copyright |
| 23 | * notice, this list of conditions and the following disclaimer. |
| 24 | * * Redistributions in binary form must reproduce the above copyright |
| 25 | * notice, this list of conditions and the following disclaimer in the |
| 26 | * documentation and/or other materials provided with the distribution. |
| 27 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 28 | * its contributors may be used to endorse or promote products derived |
| 29 | * from this software without specific prior written permission. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 30 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 31 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 32 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 33 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 34 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 35 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 36 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 37 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 38 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 39 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 40 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 41 | ****************************************************************************** |
| 42 | */ |
| 43 | |
| 44 | /*---------------------------------------------------------------------------------------- |
| 45 | * M O D U L E S U S E D |
| 46 | *---------------------------------------------------------------------------------------- |
| 47 | */ |
| 48 | #include "AGESA.h" |
| 49 | #include "amdlib.h" |
| 50 | #include "cpuRegisters.h" |
| 51 | #include "cpuFamilyTranslation.h" |
| 52 | #include "cpuLateInit.h" |
| 53 | #include "OptionCrat.h" |
| 54 | #include "cpuCrat.h" |
| 55 | #include "cpuServices.h" |
| 56 | #include "Filecode.h" |
| 57 | CODE_GROUP (G3_DXE) |
| 58 | RDATA_GROUP (G3_DXE) |
| 59 | |
| 60 | #define FILECODE PROC_CPU_FAMILY_0X15_CPUF15CRAT_FILECODE |
| 61 | |
| 62 | |
| 63 | /*---------------------------------------------------------------------------------------- |
| 64 | * D E F I N I T I O N S A N D M A C R O S |
| 65 | *---------------------------------------------------------------------------------------- |
| 66 | */ |
| 67 | |
| 68 | /*---------------------------------------------------------------------------------------- |
| 69 | * T Y P E D E F S A N D S T R U C T U R E S |
| 70 | *---------------------------------------------------------------------------------------- |
| 71 | */ |
| 72 | extern CONST UINT8 ROMDATA L2L3Associativity[]; |
| 73 | |
| 74 | /*---------------------------------------------------------------------------------------- |
| 75 | * P R O T O T Y P E S O F L O C A L F U N C T I O N S |
| 76 | *---------------------------------------------------------------------------------------- |
| 77 | */ |
| 78 | |
| 79 | /*---------------------------------------------------------------------------------------- |
| 80 | * E X P O R T E D F U N C T I O N S |
| 81 | *---------------------------------------------------------------------------------------- |
| 82 | */ |
| 83 | |
| 84 | /* -----------------------------------------------------------------------------*/ |
| 85 | /** |
| 86 | * |
| 87 | * generate CRAT cache entry for F15 processor |
| 88 | * |
| 89 | * |
| 90 | * @param[in] CratHeaderStructPtr CRAT header pointer |
| 91 | * @param[in, out] TableEnd The end of CRAT |
| 92 | * @param[in, out] StdHeader Standard Head Pointer |
| 93 | * |
| 94 | */ |
| 95 | VOID |
| 96 | STATIC |
| 97 | F15GenerateCratCacheEntry ( |
| 98 | IN CRAT_HEADER *CratHeaderStructPtr, |
| 99 | IN OUT UINT8 **TableEnd, |
| 100 | IN AMD_CONFIG_PARAMS *StdHeader |
| 101 | ) |
| 102 | { |
| 103 | UINT8 i; |
| 104 | UINT8 NodeNum; |
| 105 | UINT8 NodeCount; |
| 106 | UINT8 CoreNumPerCU; |
| 107 | UINT32 Socket; |
| 108 | UINT32 Module; |
| 109 | UINT32 CoreNum; |
| 110 | UINT32 LowCore; |
| 111 | UINT32 HighCore; |
| 112 | UINT32 RegVal; |
| 113 | CPUID_DATA L1CpuId; |
| 114 | CPUID_DATA L2L3CpuId; |
| 115 | CRAT_CACHE *EntryPtr; |
| 116 | AMD_APIC_PARAMS ApicParams; |
| 117 | PCI_ADDR PciAddress; |
| 118 | |
| 119 | // Get Node count |
| 120 | PciAddress.AddressValue = MAKE_SBDFO (0, 0, LOW_NODE_DEVICEID, FUNC_0, 0x60); |
| 121 | LibAmdPciRead (AccessWidth32 , PciAddress, &RegVal, StdHeader); |
| 122 | NodeCount = (UINT8) (((RegVal >> 4) & 0x7) + 1); |
| 123 | |
| 124 | // Get compute unit info |
| 125 | switch (GetComputeUnitMapping (StdHeader)) { |
| 126 | case AllCoresMapping: |
| 127 | CoreNumPerCU = 1; |
| 128 | break; |
| 129 | case EvenCoresMapping: |
| 130 | CoreNumPerCU = 2; |
| 131 | break; |
| 132 | default: |
| 133 | CoreNumPerCU = 1; |
| 134 | } |
| 135 | // Get L1 L2 cache information from CPUID |
| 136 | LibAmdCpuidRead (AMD_CPUID_TLB_L1Cache, &L1CpuId, StdHeader); |
| 137 | LibAmdCpuidRead (AMD_CPUID_L2L3Cache_L2TLB, &L2L3CpuId, StdHeader); |
| 138 | |
| 139 | NodeNum = 0; |
| 140 | ApicParams.StdHeader = *StdHeader; |
| 141 | while (NodeNum < NodeCount) { |
| 142 | GetSocketModuleOfNode ((UINT32) NodeNum, &Socket, &Module, StdHeader); |
| 143 | GetGivenModuleCoreRange (Socket, Module, &LowCore, &HighCore, StdHeader); |
| 144 | |
| 145 | for (CoreNum = LowCore; CoreNum <= HighCore; CoreNum++) { |
| 146 | ApicParams.Socket = (UINT8) Socket; |
| 147 | ApicParams.Core = (UINT8) CoreNum; |
| 148 | AmdGetApicId (&ApicParams); |
| 149 | if (ApicParams.IsPresent) { |
| 150 | // L1 Data cache |
| 151 | EntryPtr = (CRAT_CACHE *) AddOneCratEntry (CRAT_TYPE_CACHE, CratHeaderStructPtr, TableEnd, StdHeader); |
| 152 | EntryPtr->Flags.Enabled = 1; |
| 153 | EntryPtr->Flags.DataCache = 1; |
| 154 | EntryPtr->Flags.CpuCache = 1; |
| 155 | EntryPtr->ProcessorIdLow = ApicParams.ApicAddress; |
| 156 | i = ApicParams.ApicAddress / 8; |
| 157 | EntryPtr->SiblingMap[i] = 1 << (ApicParams.ApicAddress % 8); |
| 158 | EntryPtr->CacheSize = L1CpuId.ECX_Reg >> 24; // bits[31:24] L1 data cache size |
| 159 | EntryPtr->CacheLevel = 1; |
| 160 | EntryPtr->LinesPerTag = (UINT8) ((L1CpuId.ECX_Reg >> 8) & 0xFF); // bits[15:8] L1 data cache lines per tag; |
| 161 | EntryPtr->CacheLineSize = (UINT16) (L1CpuId.ECX_Reg & 0xFF); // bits[7:0] L1 data cache line size; |
| 162 | EntryPtr->Associativity = (UINT8) ((L1CpuId.ECX_Reg >> 16) & 0xFF); // bits[23:16] L1 data cache associativity; |
| 163 | /// @todo which value should set here? |
| 164 | //EntryPtr->CacheProperties = ; |
| 165 | EntryPtr->CacheLatency = 1; |
| 166 | |
| 167 | if (CoreNum % CoreNumPerCU == 0) { |
| 168 | // L1 Instruction cache, shared by compute unit |
| 169 | EntryPtr = (CRAT_CACHE *) AddOneCratEntry (CRAT_TYPE_CACHE, CratHeaderStructPtr, TableEnd, StdHeader); |
| 170 | EntryPtr->Flags.Enabled = 1; |
| 171 | EntryPtr->Flags.DataCache = 1; |
| 172 | EntryPtr->Flags.CpuCache = 1; |
| 173 | EntryPtr->ProcessorIdLow = ApicParams.ApicAddress; |
| 174 | i = ApicParams.ApicAddress / 8; |
| 175 | EntryPtr->SiblingMap[i] = 3 << (ApicParams.ApicAddress % 8); |
| 176 | EntryPtr->CacheSize = L1CpuId.EDX_Reg >> 24; // bits[31:24] L1 instruction cache size |
| 177 | EntryPtr->CacheLevel = 1; |
| 178 | EntryPtr->LinesPerTag = (UINT8) ((L1CpuId.EDX_Reg >> 8) & 0xFF); // bits[15:8] L1 instruction cache lines per tag |
| 179 | EntryPtr->CacheLineSize = (UINT16) (L1CpuId.EDX_Reg & 0xFF); // bits[7:0] L1 data instruction line size |
| 180 | EntryPtr->Associativity = (UINT8) ((L1CpuId.EDX_Reg >> 16) & 0xFF); // bits[23:16] L1 instruction cache associativity |
| 181 | /// @todo which value should be set here? |
| 182 | //EntryPtr->CacheProperties = ; |
| 183 | EntryPtr->CacheLatency = 1; |
| 184 | |
| 185 | // L2 cache, shared by compute unit |
| 186 | EntryPtr = (CRAT_CACHE *) AddOneCratEntry (CRAT_TYPE_CACHE, CratHeaderStructPtr, TableEnd, StdHeader); |
| 187 | EntryPtr->Flags.Enabled = 1; |
| 188 | EntryPtr->Flags.CpuCache = 1; |
| 189 | EntryPtr->ProcessorIdLow = ApicParams.ApicAddress; |
| 190 | i = ApicParams.ApicAddress / 8; |
| 191 | EntryPtr->SiblingMap[i] = 3 << (ApicParams.ApicAddress % 8); |
| 192 | EntryPtr->CacheSize = L2L3CpuId.ECX_Reg >> 16; // bits[31:16] L2 cache size |
| 193 | EntryPtr->CacheLevel = 2; |
| 194 | EntryPtr->LinesPerTag = (UINT8) ((L2L3CpuId.ECX_Reg >> 8) & 0xF); // bits[11:8] L2 cache lines per tag |
| 195 | EntryPtr->CacheLineSize = (UINT16) (L2L3CpuId.ECX_Reg & 0xFF); // bits[7:0] L2 cache line size |
| 196 | EntryPtr->Associativity = L2L3Associativity[(L2L3CpuId.ECX_Reg >> 12) & 0xF]; // bits[15:12] L2 cache associativity |
| 197 | } |
| 198 | // L3 cache, shared by node |
| 199 | // bits[31:18] L3 cache size |
| 200 | if (((L2L3CpuId.EDX_Reg & 0xFFFC0000) != 0) && (CoreNum == 0)) { |
| 201 | EntryPtr = (CRAT_CACHE *) AddOneCratEntry (CRAT_TYPE_CACHE, CratHeaderStructPtr, TableEnd, StdHeader); |
| 202 | EntryPtr->Flags.Enabled = 1; |
| 203 | EntryPtr->Flags.CpuCache = 1; |
| 204 | EntryPtr->ProcessorIdLow = ApicParams.ApicAddress; |
| 205 | i = ApicParams.ApicAddress / 8; |
| 206 | EntryPtr->SiblingMap[i] = ((1 << (UINT8) (HighCore - LowCore + 1)) - 1) << (ApicParams.ApicAddress % 8); |
| 207 | EntryPtr->CacheSize = (L2L3CpuId.EDX_Reg >> 18) * 512; // bits[31:18] L3 cache size |
| 208 | EntryPtr->CacheLevel = 3; |
| 209 | EntryPtr->LinesPerTag = (UINT8) ((L2L3CpuId.EDX_Reg >> 8) & 0xF); // bits[11:8] L3 cache lines per tag |
| 210 | EntryPtr->CacheLineSize = (UINT16) (L2L3CpuId.EDX_Reg & 0xFF); // bits[7:0] L3 cache line size |
| 211 | EntryPtr->Associativity = L2L3Associativity[(L2L3CpuId.EDX_Reg >> 12) & 0xF]; // bits[15:12] L3 cache associativity |
| 212 | |
| 213 | } |
| 214 | } |
| 215 | } |
| 216 | |
| 217 | NodeNum++; |
| 218 | } |
| 219 | |
| 220 | return; |
| 221 | } |
| 222 | |
| 223 | /* -----------------------------------------------------------------------------*/ |
| 224 | /** |
| 225 | * |
| 226 | * generate CRAT TLB entry for F15 processor |
| 227 | * |
| 228 | * |
| 229 | * @param[in] CratHeaderStructPtr CRAT header pointer |
| 230 | * @param[in, out] TableEnd The end of CRAT |
| 231 | * @param[in, out] StdHeader Standard Head Pointer |
| 232 | * |
| 233 | */ |
| 234 | VOID |
| 235 | STATIC |
| 236 | F15GenerateCratTLBEntry ( |
| 237 | IN CRAT_HEADER *CratHeaderStructPtr, |
| 238 | IN OUT UINT8 **TableEnd, |
| 239 | IN AMD_CONFIG_PARAMS *StdHeader |
| 240 | ) |
| 241 | { |
| 242 | return; |
| 243 | } |
| 244 | |
| 245 | CONST CRAT_FAMILY_SERVICES ROMDATA F15CratSupport = |
| 246 | { |
| 247 | 0, |
| 248 | F15GenerateCratCacheEntry, |
| 249 | F15GenerateCratTLBEntry |
| 250 | }; |
| 251 | |