zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * AMD Family_15 Trinity after warm reset sequence for NB P-states |
| 6 | * |
| 7 | * Performs the "NB COF and VID Transition Sequence After Warm Reset" |
| 8 | * as described in the BKDG. |
| 9 | * |
| 10 | * @xrefitem bom "File Content Label" "Release Content" |
| 11 | * @e project: AGESA |
| 12 | * @e sub-project: CPU/Family/0x15/TN |
| 13 | * @e \$Revision: 64197 $ @e \$Date: 2012-01-17 16:18:33 -0600 (Tue, 17 Jan 2012) $ |
| 14 | * |
| 15 | */ |
| 16 | /* |
| 17 | ****************************************************************************** |
| 18 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 19 | * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. |
| 20 | * All rights reserved. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 21 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 22 | * Redistribution and use in source and binary forms, with or without |
| 23 | * modification, are permitted provided that the following conditions are met: |
| 24 | * * Redistributions of source code must retain the above copyright |
| 25 | * notice, this list of conditions and the following disclaimer. |
| 26 | * * Redistributions in binary form must reproduce the above copyright |
| 27 | * notice, this list of conditions and the following disclaimer in the |
| 28 | * documentation and/or other materials provided with the distribution. |
| 29 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 30 | * its contributors may be used to endorse or promote products derived |
| 31 | * from this software without specific prior written permission. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 32 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 33 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 34 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 35 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 36 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 37 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 38 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 39 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 40 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 41 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 42 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 43 | ****************************************************************************** |
| 44 | */ |
| 45 | |
| 46 | /*---------------------------------------------------------------------------------------- |
| 47 | * M O D U L E S U S E D |
| 48 | *---------------------------------------------------------------------------------------- |
| 49 | */ |
| 50 | #include "AGESA.h" |
| 51 | #include "amdlib.h" |
| 52 | #include "cpuF15PowerMgmt.h" |
| 53 | #include "cpuF15TnPowerMgmt.h" |
| 54 | #include "cpuRegisters.h" |
| 55 | #include "cpuApicUtilities.h" |
| 56 | #include "cpuFamilyTranslation.h" |
| 57 | #include "GeneralServices.h" |
| 58 | #include "cpuServices.h" |
| 59 | #include "heapManager.h" |
| 60 | #include "cpuF15TnNbAfterReset.h" |
| 61 | #include "GnbRegisterAccTN.h" |
| 62 | #include "GnbRegistersTN.h" |
| 63 | #include "Filecode.h" |
| 64 | CODE_GROUP (G3_DXE) |
| 65 | RDATA_GROUP (G3_DXE) |
| 66 | |
| 67 | #define FILECODE PROC_CPU_FAMILY_0X15_TN_CPUF15TNNBAFTERRESET_FILECODE |
| 68 | |
| 69 | /*---------------------------------------------------------------------------------------- |
| 70 | * D E F I N I T I O N S A N D M A C R O S |
| 71 | *---------------------------------------------------------------------------------------- |
| 72 | */ |
| 73 | |
| 74 | /*---------------------------------------------------------------------------------------- |
| 75 | * T Y P E D E F S A N D S T R U C T U R E S |
| 76 | *---------------------------------------------------------------------------------------- |
| 77 | */ |
| 78 | |
| 79 | /*---------------------------------------------------------------------------------------- |
| 80 | * P R O T O T Y P E S O F L O C A L F U N C T I O N S |
| 81 | *---------------------------------------------------------------------------------------- |
| 82 | */ |
| 83 | VOID |
| 84 | STATIC |
| 85 | F15TnPmNbAfterResetOnCore ( |
| 86 | IN AMD_CONFIG_PARAMS *StdHeader |
| 87 | ); |
| 88 | |
| 89 | VOID |
| 90 | STATIC |
| 91 | TransitionToNbLow ( |
| 92 | IN PCI_ADDR PciAddress, |
| 93 | IN AMD_CONFIG_PARAMS *StdHeader |
| 94 | ); |
| 95 | |
| 96 | VOID |
| 97 | STATIC |
| 98 | TransitionToNbHigh ( |
| 99 | IN PCI_ADDR PciAddress, |
| 100 | IN AMD_CONFIG_PARAMS *StdHeader |
| 101 | ); |
| 102 | |
| 103 | VOID |
| 104 | STATIC |
| 105 | WaitForNbTransitionToComplete ( |
| 106 | IN PCI_ADDR PciAddress, |
| 107 | IN UINT32 PstateIndex, |
| 108 | IN AMD_CONFIG_PARAMS *StdHeader |
| 109 | ); |
| 110 | |
| 111 | /*---------------------------------------------------------------------------------------- |
| 112 | * E X P O R T E D F U N C T I O N S |
| 113 | *---------------------------------------------------------------------------------------- |
| 114 | */ |
| 115 | |
| 116 | /*---------------------------------------------------------------------------------------*/ |
| 117 | /** |
| 118 | * Family 15h Trinity core 0 entry point for performing the necessary steps after |
| 119 | * a warm reset has occurred. |
| 120 | * |
| 121 | * The steps are as follows: |
| 122 | * |
| 123 | * 1. Temp1=D18F5x170[SwNbPstateLoDis]. |
| 124 | * 2. Temp2=D18F5x170[NbPstateDisOnP0]. |
| 125 | * 3. Temp3=D18F5x170[NbPstateThreshold]. |
| 126 | * 4. Temp4=D18F5x170[NbPstateGnbSlowDis]. |
| 127 | * 5. If MSRC001_0070[NbPstate]=0, go to step 6. If MSRC001_0070[NbPstate]=1, go to step 11. |
| 128 | * 6. Write 1 to D18F5x170[NbPstateGnbSlowDis]. |
| 129 | * 7. Write 0 to D18F5x170[SwNbPstateLoDis, NbPstateDisOnP0, NbPstateThreshold]. |
| 130 | * 8. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateLo] and D18F5x174[CurNbFid, CurNb- |
| 131 | * Did]=[NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateLo]. |
| 132 | * 9. Set D18F5x170[SwNbPstateLoDis]=1. |
| 133 | * 10. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateHi] and D18F5x174[CurNbFid, CurNb- |
| 134 | * Did]=[NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateHi]. Go to step 15. |
| 135 | * 11. Write 1 to D18F5x170[SwNbPstateLoDis]. |
| 136 | * 12. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateHi] and D18F5x174[CurNbFid, CurNb- |
| 137 | * Did]=[NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateHi]. |
| 138 | * 13. Write 0 to D18F5x170[SwNbPstateLoDis, NbPstateDisOnP0, NbPstateThreshold]. |
| 139 | * 14. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateLo] and D18F5x174[CurNbFid, CurNb- |
| 140 | * Did]=[NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateLo]. |
| 141 | * 15. Set D18F5x170[SwNbPstateLoDis]=Temp1, D18F5x170[NbPstateDisOnP0]=Temp2, D18F5x170[NbP- |
| 142 | * stateThreshold]=Temp3, and D18F5x170[NbPstateGnbSlowDis]=Temp4. |
| 143 | * |
| 144 | * @param[in] FamilySpecificServices The current Family Specific Services. |
| 145 | * @param[in] CpuEarlyParamsPtr Service parameters |
| 146 | * @param[in] StdHeader Config handle for library and services. |
| 147 | * |
| 148 | */ |
| 149 | VOID |
| 150 | F15TnPmNbAfterReset ( |
| 151 | IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, |
| 152 | IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr, |
| 153 | IN AMD_CONFIG_PARAMS *StdHeader |
| 154 | ) |
| 155 | { |
| 156 | UINT32 Socket; |
| 157 | UINT32 Module; |
| 158 | UINT32 Core; |
| 159 | UINT32 TaskedCore; |
| 160 | UINT32 Ignored; |
| 161 | AP_TASK TaskPtr; |
| 162 | PCI_ADDR PciAddress; |
| 163 | AGESA_STATUS IgnoredSts; |
| 164 | LOCATE_HEAP_PTR Locate; |
| 165 | |
| 166 | IDS_HDT_CONSOLE (CPU_TRACE, " F15TnPmNbAfterReset\n"); |
| 167 | |
| 168 | IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts); |
| 169 | |
| 170 | ASSERT (Core == 0); |
| 171 | |
| 172 | if (FamilySpecificServices->IsNbPstateEnabled (FamilySpecificServices, &CpuEarlyParamsPtr->PlatformConfig, StdHeader)) { |
| 173 | PciAddress.AddressValue = NB_PSTATE_CTRL_PCI_ADDR; |
| 174 | Locate.BufferHandle = AMD_CPU_NB_PSTATE_FIXUP_HANDLE; |
| 175 | if (HeapLocateBuffer (&Locate, StdHeader) == AGESA_SUCCESS) { |
| 176 | LibAmdPciWrite (AccessWidth32, PciAddress, Locate.BufferPtr, StdHeader); |
| 177 | } else { |
| 178 | ASSERT (FALSE); |
| 179 | } |
| 180 | } |
| 181 | |
| 182 | // Launch one core per node. |
| 183 | TaskPtr.FuncAddress.PfApTask = F15TnPmNbAfterResetOnCore; |
| 184 | TaskPtr.DataTransfer.DataSizeInDwords = 0; |
| 185 | TaskPtr.ExeFlags = WAIT_FOR_CORE; |
| 186 | for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) { |
| 187 | if (GetGivenModuleCoreRange (Socket, Module, &TaskedCore, &Ignored, StdHeader)) { |
| 188 | if (TaskedCore != 0) { |
| 189 | ApUtilRunCodeOnSocketCore ((UINT8) Socket, (UINT8) TaskedCore, &TaskPtr, StdHeader); |
| 190 | } |
| 191 | } |
| 192 | } |
| 193 | ApUtilTaskOnExecutingCore (&TaskPtr, StdHeader, (VOID *) CpuEarlyParamsPtr); |
| 194 | } |
| 195 | |
| 196 | /*---------------------------------------------------------------------------------------*/ |
| 197 | /** |
| 198 | * Family 15h Trinity core 0 entry point for performing the necessary Nb P-state VID adjustment |
| 199 | * after a cold reset has occurred. |
| 200 | * |
| 201 | * @param[in] FamilySpecificServices The current Family Specific Services. |
| 202 | * @param[in] CpuEarlyParamsPtr Service parameters |
| 203 | * @param[in] StdHeader Config handle for library and services. |
| 204 | * |
| 205 | */ |
| 206 | VOID |
| 207 | F15TnNbPstateVidAdjustAfterReset ( |
| 208 | IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, |
| 209 | IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr, |
| 210 | IN AMD_CONFIG_PARAMS *StdHeader |
| 211 | ) |
| 212 | { |
| 213 | PCI_ADDR PciAddress; |
| 214 | BOOLEAN NeitherHiNorLo; |
| 215 | NB_PSTATE_REGISTER NbPsReg; |
| 216 | UINT32 NbPsVid; |
| 217 | UINT32 i; |
| 218 | NB_PSTATE_CTRL_REGISTER NbPsCtrl; |
| 219 | NB_PSTATE_CTRL_REGISTER NbPsCtrlSave; |
| 220 | NB_PSTATE_STS_REGISTER NbPsSts; |
| 221 | CLK_PWR_TIMING_CTRL_5_REGISTER ClkPwrTimgCtrl5; |
| 222 | D0F0xBC_x1F400_STRUCT D0F0xBC_x1F400; |
| 223 | |
| 224 | // Check if D18F5x188[NbOffsetTrim] has been programmed to 01b (-25mV) |
| 225 | PciAddress.AddressValue = CPTC5_PCI_ADDR; |
| 226 | LibAmdPciRead (AccessWidth32, PciAddress, &ClkPwrTimgCtrl5, StdHeader); |
| 227 | if (ClkPwrTimgCtrl5.NbOffsetTrim == 1) { |
| 228 | return; |
| 229 | } |
| 230 | |
| 231 | // Add 25mV (-4 VID steps) to all VddNb VIDs. |
| 232 | PciAddress.AddressValue = NB_PSTATE_0_PCI_ADDR; |
| 233 | |
| 234 | for (i = 0; i < NM_NB_PS_REG; i++) { |
| 235 | PciAddress.Address.Register = NB_PSTATE_0 + (i * 4); |
| 236 | LibAmdPciRead (AccessWidth32, PciAddress, &NbPsReg, StdHeader); |
| 237 | if (NbPsReg.NbPstateEn == 1) { |
| 238 | NbPsVid = GetF15TnNbVid (&NbPsReg); |
| 239 | NbPsVid -= 4; |
| 240 | SetF15TnNbVid (&NbPsReg, &NbPsVid); |
| 241 | LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsReg, StdHeader); |
| 242 | } |
| 243 | } |
| 244 | |
| 245 | // Check if D18F5x174[CurNbPstate] equals NbPstateHi or NbPstateLo |
| 246 | PciAddress.Address.Register = NB_PSTATE_STATUS; |
| 247 | LibAmdPciRead (AccessWidth32, PciAddress, &NbPsSts, StdHeader); |
| 248 | PciAddress.Address.Register = NB_PSTATE_CTRL; |
| 249 | LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader); |
| 250 | // Save NB P-state control setting |
| 251 | NbPsCtrlSave = NbPsCtrl; |
| 252 | |
| 253 | // Force a NB P-state Transition. |
| 254 | NeitherHiNorLo = FALSE; |
| 255 | if (NbPsSts.CurNbPstate == NbPsCtrl.NbPstateHi) { |
| 256 | TransitionToNbLow (PciAddress, StdHeader); |
| 257 | } else if (NbPsSts.CurNbPstate == NbPsCtrl.NbPstateLo) { |
| 258 | TransitionToNbHigh (PciAddress, StdHeader); |
| 259 | } else { |
| 260 | NeitherHiNorLo = TRUE; |
| 261 | } |
| 262 | |
| 263 | // Set OffsetTrim to -25mV: |
| 264 | // D18F5x188[NbOffsetTrim]=01b (-25mV) |
| 265 | // D0F0xBC_x1F400[SviLoadLineOffsetVddNB]=01b (-25mV) |
| 266 | PciAddress.Address.Register = CPTC5_REG; |
| 267 | LibAmdPciRead (AccessWidth32, PciAddress, &ClkPwrTimgCtrl5, StdHeader); |
| 268 | ClkPwrTimgCtrl5.NbOffsetTrim = 1; |
| 269 | LibAmdPciWrite (AccessWidth32, PciAddress, &ClkPwrTimgCtrl5, StdHeader); |
| 270 | |
| 271 | GnbRegisterReadTN (D0F0xBC_x1F400_TYPE, D0F0xBC_x1F400_ADDRESS, &D0F0xBC_x1F400, 0, StdHeader); |
| 272 | D0F0xBC_x1F400.Field.SviLoadLineOffsetVddNB = 1; |
| 273 | GnbRegisterWriteTN (D0F0xBC_x1F400_TYPE, D0F0xBC_x1F400_ADDRESS, &D0F0xBC_x1F400, 0, StdHeader); |
| 274 | |
| 275 | // Unforce NB P-state back to CurNbPstate value upon entry. |
| 276 | if (NeitherHiNorLo || (NbPsSts.CurNbPstate == NbPsCtrl.NbPstateHi)) { |
| 277 | TransitionToNbHigh (PciAddress, StdHeader); |
| 278 | } else { |
| 279 | // if (NbPsSts.CurNbPstate == NbPsCtrl.NbPstateLo) |
| 280 | TransitionToNbLow (PciAddress, StdHeader); |
| 281 | } |
| 282 | |
| 283 | // Restore NB P-state control setting |
| 284 | PciAddress.Address.Register = NB_PSTATE_CTRL; |
| 285 | NbPsCtrl = NbPsCtrlSave; |
| 286 | LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader); |
| 287 | } |
| 288 | |
| 289 | |
| 290 | /*--------------------------------------------------------------------------------------- |
| 291 | * L O C A L F U N C T I O N S |
| 292 | *--------------------------------------------------------------------------------------- |
| 293 | */ |
| 294 | |
| 295 | /*---------------------------------------------------------------------------------------*/ |
| 296 | /** |
| 297 | * Support routine for F15TnPmNbAfterReset to perform MSR initialization on one |
| 298 | * core of each die in a family 15h socket. |
| 299 | * |
| 300 | * This function implements steps 1 - 15 on each core. |
| 301 | * |
| 302 | * @param[in] StdHeader Config handle for library and services. |
| 303 | * |
| 304 | */ |
| 305 | VOID |
| 306 | STATIC |
| 307 | F15TnPmNbAfterResetOnCore ( |
| 308 | IN AMD_CONFIG_PARAMS *StdHeader |
| 309 | ) |
| 310 | { |
| 311 | UINT32 NbPsCtrlOnEntry; |
| 312 | UINT32 NbPsCtrlOnExit; |
| 313 | UINT64 LocalMsrRegister; |
| 314 | PCI_ADDR PciAddress; |
| 315 | |
| 316 | IDS_HDT_CONSOLE (CPU_TRACE, " F15TnPmNbAfterResetOnCore\n"); |
| 317 | |
| 318 | // 1. Temp1 = D18F5x170[SwNbPstateLoDis]. |
| 319 | // 2. Temp2 = D18F5x170[NbPstateDisOnP0]. |
| 320 | // 3. Temp3 = D18F5x170[NbPstateThreshold]. |
| 321 | // 4. Temp4 = D18F5x170[NbPstateGnbSlowDis]. |
| 322 | PciAddress.AddressValue = NB_PSTATE_CTRL_PCI_ADDR; |
| 323 | LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrlOnEntry, StdHeader); |
| 324 | |
| 325 | // Check if NB P-states were disabled, and if so, prevent any changes from occurring. |
| 326 | if (((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnEntry)->SwNbPstateLoDis == 0) { |
| 327 | // 5. If MSRC001_0070[NbPstate] = 1, go to step 11 |
| 328 | LibAmdMsrRead (MSR_COFVID_CTL, &LocalMsrRegister, StdHeader); |
| 329 | if (((COFVID_CTRL_MSR *) &LocalMsrRegister)->NbPstate == 0) { |
| 330 | // 6. Write 1 to D18F5x170[NbPstateGnbSlowDis]. |
| 331 | PciAddress.AddressValue = NB_PSTATE_CTRL_PCI_ADDR; |
| 332 | LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrlOnExit, StdHeader); |
| 333 | ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnExit)->NbPstateGnbSlowDis = 1; |
| 334 | LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCtrlOnExit, StdHeader); |
| 335 | |
| 336 | // 7. Write 0 to D18F5x170[SwNbPstateLoDis, NbPstateDisOnP0, NbPstateThreshold]. |
| 337 | // 8. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateLo] and D18F5x174[CurNbFid, |
| 338 | // CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateLo]. |
| 339 | TransitionToNbLow (PciAddress, StdHeader); |
| 340 | |
| 341 | // 9. Set D18F5x170[SwNbPstateLoDis] = 1. |
| 342 | // 10. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateHi] and D18F5x174[CurNbFid, |
| 343 | // CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateHi]. |
| 344 | // Go to step 15. |
| 345 | TransitionToNbHigh (PciAddress, StdHeader); |
| 346 | } else { |
| 347 | // 11. Set D18F5x170[SwNbPstateLoDis] = 1. |
| 348 | // 12. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateHi] and D18F5x174[CurNbFid, |
| 349 | // CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateHi]. |
| 350 | TransitionToNbHigh (PciAddress, StdHeader); |
| 351 | |
| 352 | // 13. Write 0 to D18F5x170[SwNbPstateLoDis, NbPstateDisOnP0, NbPstateThreshold]. |
| 353 | // 14. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateLo] and D18F5x174[CurNbFid, |
| 354 | // CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateLo]. |
| 355 | TransitionToNbLow (PciAddress, StdHeader); |
| 356 | } |
| 357 | |
| 358 | // 15. Set D18F5x170[SwNbPstateLoDis]=Temp1, D18F5x170[NbPstateDisOnP0]=Temp2, D18F5x170[NbP- |
| 359 | // stateThreshold]=Temp3, and D18F5x170[NbPstateGnbSlowDis]=Temp4. |
| 360 | LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrlOnExit, StdHeader); |
| 361 | ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnExit)->SwNbPstateLoDis = ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnEntry)->SwNbPstateLoDis; |
| 362 | ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnExit)->NbPstateDisOnP0 = ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnEntry)->NbPstateDisOnP0; |
| 363 | ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnExit)->NbPstateThreshold = ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnEntry)->NbPstateThreshold; |
| 364 | ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnExit)->NbPstateGnbSlowDis = ((NB_PSTATE_CTRL_REGISTER *) &NbPsCtrlOnEntry)->NbPstateGnbSlowDis; |
| 365 | LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCtrlOnExit, StdHeader); |
| 366 | } |
| 367 | } |
| 368 | |
| 369 | /*---------------------------------------------------------------------------------------*/ |
| 370 | /** |
| 371 | * Support routine for F15TnPmNbAfterResetOnCore to transition to the low NB P-state. |
| 372 | * |
| 373 | * This function implements steps 7, 8, 13, and 14 as needed. |
| 374 | * |
| 375 | * @param[in] PciAddress Segment, bus, device number of the node to transition. |
| 376 | * @param[in] StdHeader Config handle for library and services. |
| 377 | * |
| 378 | */ |
| 379 | VOID |
| 380 | STATIC |
| 381 | TransitionToNbLow ( |
| 382 | IN PCI_ADDR PciAddress, |
| 383 | IN AMD_CONFIG_PARAMS *StdHeader |
| 384 | ) |
| 385 | { |
| 386 | NB_PSTATE_CTRL_REGISTER NbPsCtrl; |
| 387 | |
| 388 | IDS_HDT_CONSOLE (CPU_TRACE, " TransitionToNbLow\n"); |
| 389 | |
| 390 | // 7/13. Write 0 to D18F5x170[SwNbPstateLoDis, NbPstateDisOnP0, NbPstateThreshold]. |
| 391 | PciAddress.AddressValue = NB_PSTATE_CTRL_PCI_ADDR; |
| 392 | LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader); |
| 393 | NbPsCtrl.SwNbPstateLoDis = 0; |
| 394 | NbPsCtrl.NbPstateDisOnP0 = 0; |
| 395 | NbPsCtrl.NbPstateThreshold = 0; |
| 396 | LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader); |
| 397 | |
| 398 | // 8/14. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateLo] and D18F5x174[CurNbFid, |
| 399 | // CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateLo]. |
| 400 | WaitForNbTransitionToComplete (PciAddress, NbPsCtrl.NbPstateLo, StdHeader); |
| 401 | } |
| 402 | |
| 403 | /*---------------------------------------------------------------------------------------*/ |
| 404 | /** |
| 405 | * Support routine for F15TnPmNbAfterResetOnCore to transition to the high NB P-state. |
| 406 | * |
| 407 | * This function implements steps 9, 10, 11, and 12 as needed. |
| 408 | * |
| 409 | * @param[in] PciAddress Segment, bus, device number of the node to transition. |
| 410 | * @param[in] StdHeader Config handle for library and services. |
| 411 | * |
| 412 | */ |
| 413 | VOID |
| 414 | STATIC |
| 415 | TransitionToNbHigh ( |
| 416 | IN PCI_ADDR PciAddress, |
| 417 | IN AMD_CONFIG_PARAMS *StdHeader |
| 418 | ) |
| 419 | { |
| 420 | NB_PSTATE_CTRL_REGISTER NbPsCtrl; |
| 421 | |
| 422 | IDS_HDT_CONSOLE (CPU_TRACE, " TransitionToNbHigh\n"); |
| 423 | |
| 424 | // 9/10. Set D18F5x170[SwNbPstateLoDis] = 1. |
| 425 | PciAddress.AddressValue = NB_PSTATE_CTRL_PCI_ADDR; |
| 426 | LibAmdPciRead (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader); |
| 427 | NbPsCtrl.SwNbPstateLoDis = 1; |
| 428 | LibAmdPciWrite (AccessWidth32, PciAddress, &NbPsCtrl, StdHeader); |
| 429 | |
| 430 | // 11/12. Wait for D18F5x174[CurNbPstate] = D18F5x170[NbPstateHi] and D18F5x174[CurNbFid, |
| 431 | // CurNbDid] = [NbFid, NbDid] from D18F5x1[6C:60] indexed by D18F5x170[NbPstateHi]. |
| 432 | WaitForNbTransitionToComplete (PciAddress, NbPsCtrl.NbPstateHi, StdHeader); |
| 433 | } |
| 434 | |
| 435 | /*---------------------------------------------------------------------------------------*/ |
| 436 | /** |
| 437 | * Support routine for F15TnPmAfterResetCore to wait for NB FID and DID to |
| 438 | * match a specific P-state. |
| 439 | * |
| 440 | * This function implements steps 8, 10, 12, and 14 as needed. |
| 441 | * |
| 442 | * @param[in] PciAddress Segment, bus, device number of the node to transition. |
| 443 | * @param[in] PstateIndex P-state settings to match. |
| 444 | * @param[in] StdHeader Config handle for library and services. |
| 445 | * |
| 446 | */ |
| 447 | VOID |
| 448 | STATIC |
| 449 | WaitForNbTransitionToComplete ( |
| 450 | IN PCI_ADDR PciAddress, |
| 451 | IN UINT32 PstateIndex, |
| 452 | IN AMD_CONFIG_PARAMS *StdHeader |
| 453 | ) |
| 454 | { |
| 455 | NB_PSTATE_REGISTER TargetNbPs; |
| 456 | NB_PSTATE_STS_REGISTER NbPsSts; |
| 457 | |
| 458 | IDS_HDT_CONSOLE (CPU_TRACE, " WaitForNbTransitionToComplete\n"); |
| 459 | |
| 460 | PciAddress.Address.Function = FUNC_5; |
| 461 | PciAddress.Address.Register = NB_PSTATE_0 + (PstateIndex << 2); |
| 462 | LibAmdPciRead (AccessWidth32, PciAddress, &TargetNbPs, StdHeader); |
| 463 | PciAddress.Address.Register = NB_PSTATE_STATUS; |
| 464 | do { |
| 465 | LibAmdPciRead (AccessWidth32, PciAddress, &NbPsSts, StdHeader); |
| 466 | } while ((NbPsSts.CurNbPstate != PstateIndex || |
| 467 | (NbPsSts.CurNbFid != TargetNbPs.NbFid)) || |
| 468 | (NbPsSts.CurNbDid != TargetNbPs.NbDid)); |
| 469 | } |