zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * AMD CPU Cache Flush On Halt Function for Family 15h Trinity. |
| 6 | * |
| 7 | * Contains code to initialize Cache Flush On Halt feature for Family 15h Trinity. |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: CPU/Family/0x15/TN |
| 12 | * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ |
| 13 | * |
| 14 | */ |
| 15 | /* |
| 16 | ****************************************************************************** |
| 17 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 18 | * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. |
| 19 | * All rights reserved. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 20 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 21 | * Redistribution and use in source and binary forms, with or without |
| 22 | * modification, are permitted provided that the following conditions are met: |
| 23 | * * Redistributions of source code must retain the above copyright |
| 24 | * notice, this list of conditions and the following disclaimer. |
| 25 | * * Redistributions in binary form must reproduce the above copyright |
| 26 | * notice, this list of conditions and the following disclaimer in the |
| 27 | * documentation and/or other materials provided with the distribution. |
| 28 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 29 | * its contributors may be used to endorse or promote products derived |
| 30 | * from this software without specific prior written permission. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 31 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 32 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 33 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 34 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 35 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 36 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 37 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 38 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 39 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 40 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 41 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 42 | ****************************************************************************** |
| 43 | *---------------------------------------------------------------------------- |
| 44 | */ |
| 45 | |
| 46 | |
| 47 | /* |
| 48 | *---------------------------------------------------------------------------- |
| 49 | * MODULES USED |
| 50 | * |
| 51 | *---------------------------------------------------------------------------- |
| 52 | */ |
| 53 | #include "AGESA.h" |
| 54 | #include "amdlib.h" |
| 55 | #include "cpuRegisters.h" |
| 56 | #include "cpuServices.h" |
| 57 | #include "cpuFamilyTranslation.h" |
| 58 | #include "cpuPostInit.h" |
| 59 | #include "cpuF15PowerMgmt.h" |
| 60 | #include "cpuF15TnPowerMgmt.h" |
| 61 | #include "cpuFeatures.h" |
| 62 | #include "Filecode.h" |
| 63 | CODE_GROUP (G3_DXE) |
| 64 | RDATA_GROUP (G3_DXE) |
| 65 | |
| 66 | #define FILECODE PROC_CPU_FAMILY_0X15_TN_CPUF15TNCACHEFLUSHONHALT_FILECODE |
| 67 | |
| 68 | /*---------------------------------------------------------------------------- |
| 69 | * DEFINITIONS AND MACROS |
| 70 | * |
| 71 | *---------------------------------------------------------------------------- |
| 72 | */ |
| 73 | |
| 74 | |
| 75 | /*---------------------------------------------------------------------------- |
| 76 | * TYPEDEFS AND STRUCTURES |
| 77 | * |
| 78 | *---------------------------------------------------------------------------- |
| 79 | */ |
| 80 | |
| 81 | /*---------------------------------------------------------------------------------------- |
| 82 | * E X P O R T E D F U N C T I O N S |
| 83 | *---------------------------------------------------------------------------------------- |
| 84 | */ |
| 85 | |
| 86 | /*---------------------------------------------------------------------------- |
| 87 | * PROTOTYPES OF LOCAL FUNCTIONS |
| 88 | * |
| 89 | *---------------------------------------------------------------------------- |
| 90 | */ |
| 91 | VOID |
| 92 | SetF15TnCacheFlushOnHaltRegister ( |
| 93 | IN CPU_CFOH_FAMILY_SERVICES *FamilySpecificServices, |
| 94 | IN UINT64 EntryPoint, |
| 95 | IN PLATFORM_CONFIGURATION *PlatformConfig, |
| 96 | IN AMD_CONFIG_PARAMS *StdHeader |
| 97 | ); |
| 98 | |
| 99 | /*---------------------------------------------------------------------------------------- |
| 100 | * P U B L I C F U N C T I O N S |
| 101 | *---------------------------------------------------------------------------------------- |
| 102 | */ |
| 103 | |
| 104 | /* -----------------------------------------------------------------------------*/ |
| 105 | /** |
| 106 | * Enable Cpu Cache Flush On Halt Function |
| 107 | * |
| 108 | * @param[in] FamilySpecificServices The current Family Specific Services. |
| 109 | * @param[in] EntryPoint Timepoint designator. |
| 110 | * @param[in] PlatformConfig Contains the runtime modifiable feature input data. |
| 111 | * @param[in] StdHeader Config Handle for library, services. |
| 112 | */ |
| 113 | VOID |
| 114 | SetF15TnCacheFlushOnHaltRegister ( |
| 115 | IN CPU_CFOH_FAMILY_SERVICES *FamilySpecificServices, |
| 116 | IN UINT64 EntryPoint, |
| 117 | IN PLATFORM_CONFIGURATION *PlatformConfig, |
| 118 | IN AMD_CONFIG_PARAMS *StdHeader |
| 119 | ) |
| 120 | { |
| 121 | PCI_ADDR PciAddress; |
| 122 | CLK_PWR_TIMING_CTRL2_REGISTER ClkPwrTimingCtrl2; |
| 123 | CSTATE_POLICY_CTRL1_REGISTER CstatePolicyCtrl1; |
| 124 | CSTATE_CTRL1_REGISTER CstateCtrl1; |
| 125 | |
| 126 | if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) { |
| 127 | // Set D18F3xDC[CacheFlushOnHaltCtl] != 0 |
| 128 | // Set D18F3xDC[CacheFlushOnHaltTmr] |
| 129 | PciAddress.AddressValue = CPTC2_PCI_ADDR; |
| 130 | LibAmdPciRead (AccessWidth32, PciAddress, &ClkPwrTimingCtrl2, StdHeader); |
| 131 | ClkPwrTimingCtrl2.CacheFlushOnHaltCtl = 7; |
| 132 | ClkPwrTimingCtrl2.CacheFlushOnHaltTmr = 0x14; |
| 133 | LibAmdPciWrite (AccessWidth32, PciAddress, &ClkPwrTimingCtrl2, StdHeader); |
| 134 | |
| 135 | // Set D18F4x128[CacheFlushTmr, CacheFlushSucMonThreshold] |
| 136 | PciAddress.AddressValue = CSTATE_POLICY_CTRL1_PCI_ADDR; |
| 137 | LibAmdPciRead (AccessWidth32, PciAddress, &CstatePolicyCtrl1, StdHeader); |
| 138 | CstatePolicyCtrl1.CacheFlushTmr = 0x14; |
| 139 | CstatePolicyCtrl1.CacheFlushSucMonThreshold = 7; |
| 140 | LibAmdPciWrite (AccessWidth32, PciAddress, &CstatePolicyCtrl1, StdHeader); |
| 141 | |
| 142 | // Set cache flush bits in D18F4x118 |
| 143 | PciAddress.AddressValue = CSTATE_CTRL1_PCI_ADDR; |
| 144 | LibAmdPciRead (AccessWidth32, PciAddress, &CstateCtrl1, StdHeader); |
| 145 | // Set C-state Action Field 0 |
| 146 | CstateCtrl1.CacheFlushEnCstAct0 = 1; |
| 147 | CstateCtrl1.CacheFlushTmrSelCstAct0 = 2; |
| 148 | CstateCtrl1.ClkDivisorCstAct0 = 0; |
| 149 | // Set C-state Action Field 1 |
| 150 | CstateCtrl1.CacheFlushEnCstAct1 = 1; |
| 151 | CstateCtrl1.CacheFlushTmrSelCstAct1 = 1; |
| 152 | CstateCtrl1.ClkDivisorCstAct1 = 0; |
| 153 | LibAmdPciWrite (AccessWidth32, PciAddress, &CstateCtrl1, StdHeader); |
| 154 | |
| 155 | //Override the default setting |
| 156 | IDS_OPTION_HOOK (IDS_CACHE_FLUSH_HLT, NULL, StdHeader); |
| 157 | } |
| 158 | } |
| 159 | |
| 160 | CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F15TnCacheFlushOnHalt = |
| 161 | { |
| 162 | 0, |
| 163 | SetF15TnCacheFlushOnHaltRegister |
| 164 | }; |