zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * AMD Family_15 Models 0x10 - 0x1F Power Plane Initialization |
| 6 | * |
| 7 | * Performs the "BIOS Requirements for Power Plane Initialization" as described |
| 8 | * in the BKDG. |
| 9 | * |
| 10 | * @xrefitem bom "File Content Label" "Release Content" |
| 11 | * @e project: AGESA |
| 12 | * @e sub-project: CPU/Family/0x15/TN |
| 13 | * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ |
| 14 | * |
| 15 | */ |
| 16 | /* |
| 17 | ****************************************************************************** |
| 18 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 19 | * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. |
| 20 | * All rights reserved. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 21 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 22 | * Redistribution and use in source and binary forms, with or without |
| 23 | * modification, are permitted provided that the following conditions are met: |
| 24 | * * Redistributions of source code must retain the above copyright |
| 25 | * notice, this list of conditions and the following disclaimer. |
| 26 | * * Redistributions in binary form must reproduce the above copyright |
| 27 | * notice, this list of conditions and the following disclaimer in the |
| 28 | * documentation and/or other materials provided with the distribution. |
| 29 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 30 | * its contributors may be used to endorse or promote products derived |
| 31 | * from this software without specific prior written permission. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 32 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 33 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 34 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 35 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 36 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 37 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 38 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 39 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 40 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 41 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 42 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 43 | ****************************************************************************** |
| 44 | */ |
| 45 | |
| 46 | /*---------------------------------------------------------------------------------------- |
| 47 | * M O D U L E S U S E D |
| 48 | *---------------------------------------------------------------------------------------- |
| 49 | */ |
| 50 | #include "AGESA.h" |
| 51 | #include "amdlib.h" |
| 52 | #include "Ids.h" |
| 53 | #include "cpuRegisters.h" |
| 54 | #include "cpuF15PowerMgmt.h" |
| 55 | #include "cpuF15TnPowerMgmt.h" |
| 56 | #include "cpuApicUtilities.h" |
| 57 | #include "cpuServices.h" |
| 58 | #include "GeneralServices.h" |
| 59 | #include "cpuFamilyTranslation.h" |
| 60 | #include "Table.h" |
| 61 | #include "F15TnPowerPlane.h" |
| 62 | #include "Filecode.h" |
| 63 | CODE_GROUP (G2_PEI) |
| 64 | RDATA_GROUP (G2_PEI) |
| 65 | |
| 66 | #define FILECODE PROC_CPU_FAMILY_0X15_TN_F15TNPOWERPLANE_FILECODE |
| 67 | |
| 68 | /*---------------------------------------------------------------------------------------- |
| 69 | * D E F I N I T I O N S A N D M A C R O S |
| 70 | *---------------------------------------------------------------------------------------- |
| 71 | */ |
| 72 | |
| 73 | // Register encodings for D18F3xD8[VSRampSlamTime] |
| 74 | STATIC CONST UINT32 ROMDATA F15TnVSRampSlamWaitTimes[8] = |
| 75 | { |
| 76 | 500, // 000b: 5.00us |
| 77 | 375, // 001b: 3.75us |
| 78 | 300, // 010b: 3.00us |
| 79 | 240, // 011b: 2.40us |
| 80 | 200, // 100b: 2.00us |
| 81 | 150, // 101b: 1.50us |
| 82 | 120, // 110b: 1.20us |
| 83 | 100 // 111b: 1.00us |
| 84 | }; |
| 85 | |
| 86 | /*---------------------------------------------------------------------------------------- |
| 87 | * T Y P E D E F S A N D S T R U C T U R E S |
| 88 | *---------------------------------------------------------------------------------------- |
| 89 | */ |
| 90 | |
| 91 | /*---------------------------------------------------------------------------------------- |
| 92 | * P R O T O T Y P E S O F L O C A L F U N C T I O N S |
| 93 | *---------------------------------------------------------------------------------------- |
| 94 | */ |
| 95 | |
| 96 | /*---------------------------------------------------------------------------------------- |
| 97 | * E X P O R T E D F U N C T I O N S |
| 98 | *---------------------------------------------------------------------------------------- |
| 99 | */ |
| 100 | |
| 101 | /*---------------------------------------------------------------------------------------*/ |
| 102 | /** |
| 103 | * Family 15h core 0 entry point for performing power plane initialization. |
| 104 | * |
| 105 | * The steps are as follows: |
| 106 | * 1. Configure D18F3xD8[VSRampSlamTime] based on platform |
| 107 | * requirements. |
| 108 | * 2. Configure F3xD4[PowerStepUp & PowerStepDown] |
| 109 | * 3. Optionally configure F3xA0[PsiVidEn & PsiVid] |
| 110 | * |
| 111 | * @param[in] FamilySpecificServices The current Family Specific Services. |
| 112 | * @param[in] CpuEarlyParams Service parameters |
| 113 | * @param[in] StdHeader Config handle for library and services. |
| 114 | * |
| 115 | */ |
| 116 | VOID |
| 117 | F15TnPmPwrPlaneInit ( |
| 118 | IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, |
| 119 | IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams, |
| 120 | IN AMD_CONFIG_PARAMS *StdHeader |
| 121 | ) |
| 122 | { |
| 123 | PCI_ADDR PciAddress; |
| 124 | UINT32 SystemSlewRate; |
| 125 | UINT32 WaitTime; |
| 126 | UINT32 VSRampSlamTime; |
| 127 | UINT32 LocalPciRegister; |
| 128 | CLK_PWR_TIMING_CTRL1_REGISTER ClkPwrTimingCtrl1; |
| 129 | BOOLEAN SkipPowerPlan; |
| 130 | |
| 131 | |
| 132 | SkipPowerPlan = FALSE; |
| 133 | IDS_OPTION_CALLOUT (IDS_CALLOUT_POWER_PLAN_INIT, &SkipPowerPlan, StdHeader); |
| 134 | if (!SkipPowerPlan) { |
| 135 | // Step 1 - Configure D18F3xD8[VSRampSlamTime] based on platform requirements. |
| 136 | // Voltage Ramp Time = maximum time to change voltage by 15mV rounded to the next higher encoding. |
| 137 | SystemSlewRate = (CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].SlewRate <= |
| 138 | CpuEarlyParams->PlatformConfig.VrmProperties[NbVrm].SlewRate) ? |
| 139 | CpuEarlyParams->PlatformConfig.VrmProperties[CoreVrm].SlewRate : |
| 140 | CpuEarlyParams->PlatformConfig.VrmProperties[NbVrm].SlewRate; |
| 141 | |
| 142 | ASSERT (SystemSlewRate != 0); |
| 143 | |
| 144 | // First, calculate the time it takes to change 15mV using the VRM slew rate. |
| 145 | WaitTime = (15000 * 100) / SystemSlewRate; |
| 146 | if (((15000 * 100) % SystemSlewRate) != 0) { |
| 147 | WaitTime++; |
| 148 | } |
| 149 | |
| 150 | // Next, round it to the appropriate encoded value. We will start from encoding 111b which corresponds |
| 151 | // to the fastest slew rate, and work our way down to 000b, which represents the slowest an acceptable |
| 152 | // VRM can be. |
Patrick Georgi | 6b688f5 | 2021-02-12 13:49:11 +0100 | [diff] [blame] | 153 | for (VSRampSlamTime = (ARRAY_SIZE(F15TnVSRampSlamWaitTimes)- 1); VSRampSlamTime > 0; VSRampSlamTime--) { |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 154 | if (WaitTime <= F15TnVSRampSlamWaitTimes[VSRampSlamTime]) { |
| 155 | break; |
| 156 | } |
| 157 | } |
| 158 | |
| 159 | if (WaitTime > F15TnVSRampSlamWaitTimes[0]) { |
| 160 | // The VRMs on this motherboard are too slow for this CPU. |
| 161 | IDS_ERROR_TRAP; |
| 162 | } |
| 163 | |
| 164 | // Lastly, program D18F3xD8[VSRampSlamTime] with the appropriate encoded value. |
| 165 | PciAddress.AddressValue = CPTC1_PCI_ADDR; |
| 166 | LibAmdPciRead (AccessWidth32, PciAddress, &ClkPwrTimingCtrl1, StdHeader); |
| 167 | ClkPwrTimingCtrl1.VSRampSlamTime = VSRampSlamTime; |
| 168 | LibAmdPciWrite (AccessWidth32, PciAddress, &ClkPwrTimingCtrl1, StdHeader); |
| 169 | |
| 170 | // Configure PowerStepUp/PowerStepDown |
| 171 | PciAddress.AddressValue = CPTC0_PCI_ADDR; |
| 172 | LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); |
| 173 | ((CLK_PWR_TIMING_CTRL_REGISTER *) &LocalPciRegister)->PowerStepUp = 8; |
| 174 | ((CLK_PWR_TIMING_CTRL_REGISTER *) &LocalPciRegister)->PowerStepDown = 8; |
| 175 | LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); |
| 176 | } |
| 177 | } |
| 178 | |
| 179 | |
| 180 | |